A time-sharing digital error correction circuit for a high-speed pipelined analog-to-digital converter

Abstract

The invention provides a time-sharing digital error correction circuit device of a high-speed flow line type analog-digital converter, which meets the requirement of the extreme converting rate on transmission delay, can provide a simplified digital error correction circuit, effectively controls the chip area, reduces the complexity of the circuit design and improves the design efficiency. Analog signals are input to each level of multiplication digital-analog conversion circuit device, and the output signals of each level of multiplication digital-analog conversion circuit device comprise a high order and a low order. The invention is characterized in that by utilizing a delay link gap in time delay alignment, high orders output by the current level of multiplication digital-analog conversion circuit and all orders output by all preceding level of multiplication digital-analog conversion circuits are respectively processed by digital error correction in the respective level of digital error correction circuit, and then the high order output by the next level of multiplication digital-analog conversion circuit is processed by digital error correction by entering the next level of digital error correction circuit until complete output digital signals are finally output to finish complete digital-analog conversion.

Description

technical field [0001] The invention relates to the technical field of a pipelined analog-to-digital converter (Pipeline ADC), in particular to a time-sharing digital error correction circuit of a high-speed pipelined analog-to-digital converter. Background technique [0002] Due to its relatively moderate requirements and performance in terms of process requirements, chip area, power consumption and speed, pipelined analog-to-digital converters have achieved rapid development in recent years. Based on deep submicron complementary oxide semiconductor (CMOS) technology, the accuracy of the current pipelined analog-to-digital converter covers 8 to 14 bits, and the speed covers from 25MHz to 250MHz. Based on this structure, a single converter chip or an integrated SOC chip It is widely used in communication, industry, medical imaging and defense fields. [0003] The classic 4-stage 1.5-bit + 2-bit pipelined analog-to-digital converter system such as figure 1 As shown (in orde...

AI Technical Summary

Problems solved by technology

However, as the number of stages increases, this method will lead to a geometric increase in circuit complexity, which will have a negative impact on design complexity and chip area.

Images