Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Dual-channel time interleaved asynchronous assembly line flash analog-to-digital converter

An analog-to-digital converter and time-interleaved technology, applied in the direction of analog-to-digital conversion, code conversion, instruments, etc., can solve the problem of increased power consumption of operational amplifiers

Inactive Publication Date: 2017-01-18
SOUTHEAST UNIV WUXI INST OF TECH INTEGRATED CIRCUITS
View PDF6 Cites 7 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In high-speed applications, a sampling rate of GS / s is required, which makes the design of the operational amplifier very challenging, and the power consumption of the operational amplifier will increase significantly

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Dual-channel time interleaved asynchronous assembly line flash analog-to-digital converter
  • Dual-channel time interleaved asynchronous assembly line flash analog-to-digital converter
  • Dual-channel time interleaved asynchronous assembly line flash analog-to-digital converter

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0016] In order to better understand the technical content of the present invention, specific embodiments are given together with the attached drawings for description as follows.

[0017] figure 1 It is a two-channel time-interleaved asynchronous pipeline flash ADC structure. By multiplexing parallel ADC technology, time interleaving can well increase the effective conversion rate. The structure of the dual-channel time-interleaved asynchronous pipeline flash ADC is as follows: figure 1 As shown, the structure includes the first buffer, the second buffer, the first track and hold circuit, the second track and hold circuit, the first single-channel 6-bit asynchronous pipeline flash ADC, and the second single-channel 6-bit asynchronous pipeline flash ADC Flash ADC, the input of the first tracking and holding circuit and the second tracking and holding circuit are respectively connected to the first buffer and the second buffer, the 6-bit asynchronous pipeline flash ADC of the ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a dual-channel time interleaved asynchronous assembly line flash analog-to-digital converter comprising a first buffer, a second buffer, a first tracking and holding circuit, a second tracking and holding circuit, a first single-channel 6-bit asynchronous assembly line flash ADC and a second single-channel 6-bit asynchronous assembly line flash ADC. According to the ADC, the dual-channel time interleaved asynchronous assembly line flash structure is adopted, and multiple asynchronous sampling channels and low-power-consumption multiphase clock generators are adopted in the asynchronous assembly line flash structure of each channel so that a residue amplifier which is high in power consumption and limited in bandwidth can be eliminated, and the analog-to-digital converter is suitable for high-speed, low-power-consumption and medium resolution application.

Description

technical field [0001] The invention relates to an integrated circuit analog-to-digital converter (ADC) chip, in particular to a dual-channel time-interleaved asynchronous pipeline flash analog-to-digital converter with high speed and low power consumption. Background technique [0002] High-speed, low-power, medium-resolution analog-to-digital converters (Analog-to-Digital Converters, ADCs) ) has a wide range of applications. The main challenge is how to achieve the required high sampling rate of several GS / s while maintaining lower power consumption. [0003] Since conventional pipeline ADCs need to work in GHz bandwidth, each pipeline structure includes a large power consumption residual amplifier and a sample-and-hold circuit. Although the structure of the conventional flash ADC has high-speed conversion characteristics, the power consumption is higher due to the use of a large number of high-speed comparators. In flash ADCs, the sampling frequency is mainly limited b...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/38
CPCH03M1/38H03M1/002
Inventor 余浩严媚黄汐威
Owner SOUTHEAST UNIV WUXI INST OF TECH INTEGRATED CIRCUITS
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com