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Circuitry and method for reducing area and power of a pipeline ADC

A pipeline-type, predetermined voltage technology, applied in the direction of electrical components, analog/digital conversion, code conversion, etc., can solve the problems of increasing the cost and power dissipation of pipeline-type ADCs

Active Publication Date: 2015-06-03
TEXAS INSTR INC
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If reference scaling is used, then the cost and power dissipation of the pipelined ADC will increase substantially, since each flash ADC comparator will need to consist of a much larger and power-hungry circuit

Method used

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  • Circuitry and method for reducing area and power of a pipeline ADC
  • Circuitry and method for reducing area and power of a pipeline ADC
  • Circuitry and method for reducing area and power of a pipeline ADC

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Embodiment Construction

[0053] The present invention provides an improvement over conventional "pipelined ADC stages" for pipelined ADCs, which avoids flashing of the "next" pipelined ADC stage when redundant bits are used to improve the linearity of the pipelined ADC The number of ADC comparators needs to be doubled. This improvement is achieved by using a headroom voltage level detection circuit that detects an out-of-range excursion of the headroom voltage and provides accordingly after shifting the headroom voltage back to the first stage Feedback of the desired range for each pipelined ADC stage.

[0054] Figure 4A A new pipelined ADC stage 15 is shown in which the analog input signal V IN (which is typically the headroom voltage of the preceding pipelined ADC stage) is applied to the input of the sub-ADC 8 and also to the (+) input of the headroom amplifier 11A. The sub-ADC 8 can be implemented by a flash ADC 8 commonly used in conventional pipeline ADCs. Figure 4A The flash ADC 8 in is s...

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Abstract

A pipeline ADC (analog-to-digital converter) (14) includes a residue amplifier (7) for applying a first residue signal (Vres1) to a first input of a residue amplifier (11A) and to an input of a sub-ADC (8) for resolving a predetermined number (m) of bits and producing a redundancy bit in response to the first residue signal. A level-shifting MDAC (9A) converts the predetermined number of bits and the redundancy bit to an analog signal (10) on the a second input of the residue amplifier, which amplifies the difference between the first residue signal and the analog signal to generate a second residue signal (Vres2). The MDAC causes the residue amplifier to shift the second residue signal back within a predetermined voltage range (±Vref / 2) by the end of the amplifying if the second residue signal is outside of the predetermined voltage range.

Description

technical field [0001] The present invention generally relates to improvements in increasing the linearity of pipelined ADCs (analog-to-digital converters), and more specifically, to substantially reducing the number of "next-stage comparators" and the integrated circuit chip area of ​​pipelined ADCs and an improvement in the amount of power dissipated. Background technique [0002] A pipelined ADC includes a series of pipelined ADC stages. Figure 1 shows a single conventional pipelined ADC stage 1 where the analog input signal V IN is applied to the input of the sub-ADC 8 and to the (+) input of the residue amplifier 11 . The sub-ADC 8 is usually realized by a flash ADC (flash ADC). The digital output of sub-ADC 8 is applied to the input of conventional multiplier DAC (MDAC) 9, the output of conventional multiplier DAC (MDAC) 9 is applied to the (-) input of residual amplifier 11, which produces The headroom voltage V on wire 12 RES . A headroom graph for pipelined AD...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/12
CPCH03M1/0675H03M1/167H03M1/1009H03M1/12H03M1/10H03M1/164
Inventor G·S·南迪R·库拉纳
Owner TEXAS INSTR INC
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