The invention provides a digital-analog
hybrid simulation method and simulator based on a QEMU, a
SystemC and a
SystemC-AMS. The digital-analog
hybrid simulation method comprises the following steps: adding an external memory access interface and a
time sequence synchronization interface in the QEMU; the method comprises the following steps: constructing a virtual CPU (
Central Processing Unit) device in a
SystemC; a register interface function and a logic
signal function are realized by adopting a
systemc model in the equipment, and a port
analog signal function is realized by adopting a
systemc-am model; the starting parameters are analyzed in the main program, and the
simulation component is loaded; executing a
virtual target machine instruction in the instruction core environment; switching to a
systemc running environment, changing the value of an on-
chip device register, and updating the logic function state and the port state of the device; and exiting from the systemc operation environment, and entering the operation environment of the instruction core again. The technical advantages of the QEMU, the SystemC and the SystemC-AMS are combined, a QEMU
instruction set is reused, meanwhile, the
hardware description language characteristics of the SystemC and the
analog signal processing capacity of a simulation scheduler and the SystemC-AMS are utilized, digital-analog
hybrid simulation is achieved, and the
verification efficiency and accuracy of SoC design are improved.