Digitized photoelectric detector sensing circuit
A technology for photodetectors and readout circuits, which is applied in the direction of measuring circuits and using electric radiation detectors for photometry, etc., can solve the problems of large area and power consumption, improve the readout signal-to-noise ratio, and eliminate column fixed modes Noise, the effect of eliminating column read noise
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Publication Date
- 2010-02-17
- Estimated Expiration
- Not applicable · inactive patent
Smart Images
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Abstract
Description
technical field
[0001] The invention relates to a signal processing technology of a photodetector focal plane array readout circuit. In particular, it relates to a digitized photodetector readout circuit which eliminates column fixed pattern noise and column readout noise in the analog signal readout circuit and improves the readout signal-to-noise ratio. Background technique
[0002] The photodetector focal plane array consists of a detector array and a readout circuit. The function of the readout circuit is to integrate the weak signal output by the infrared detector, amplify, denoise and parallel / serial convert, and then transmit it to the A / D for digital conversion of the analog signal. The performance of the readout circuit will directly affect the quality of the infrared focal plane. With the continuous increase of infrared focal plane arrays and the continuous improvement of the integration level of the entire imaging system, higher requirements are placed on the pe...
Examples
Embodiment Construction
[0026] The digitized photodetector readout circuit of the present invention will be described in detail below in conjunction with the accompanying drawings of the embodiments.
[0027] Such as figure 1 As shown, the digitized photodetector readout circuit of the present invention has multiple signal channels, specifically including: a front-end readout unit B composed of a plurality of unit circuits Z, and a column-shared integration circuit C connected to the front-end readout unit B , a high-speed high-precision comparator D connected to the column sharing integration circuit C, a delay control unit H connected to the high-speed high-precision comparator D, a counter E connected to the delay control unit H, and an output buffer stage G connected to the counter E , the output buffer stage G is also connected to the column selection register F, the output buffer stage G constitutes the output terminal, and the plurality of unit circuits Z are also respectively connected to the...