Integrated circuit SoC chip circuit structure capable of realizing power reduction and method thereof

Abstract

The invention relates to an integrated circuit SoC chip circuit structure capable of realizing power reduction and a method thereof. The SoC chip contains at least one working domain which powers off when idle and at least one real-time-domain which continuously powers on, wherein an isolator is arranged between the working domain and the real-time-domain, and the working domain and the real-time-domain are separately connected with an external power supply source. The method of the invention comprises the processes of working domain power-off treatment and working domain wakeup power-on treatment. By adopting the integrated circuit SoC chip circuit structure capable of realizing power reduction and the method thereof, when the chip is idle, the working domain is in power-off state and the real-time-domain generates quiescent power drain; if the leakage of the real-time-domain is ensured to be as low as possible, the quiescent power drain of the chip can be reduced to be as low as possible and the quiescent power drain of the SoC chip can be effectively reduced; the structure is simple and practical, the control process is fast and convenient, the work performance is stable and reliable and the range of application is wide, thus the structure lays a solid foundation for the application of higher precision integrated circuit process technology in portable devices and the further development of portable devices.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to the technical field of power consumption control of integrated circuits, in particular to a circuit structure and method for reducing power consumption of an integrated circuit SoC (System on Chip) chip. Background technique [0002] In portable devices, power consumption has always been an important issue, and has even become a bottleneck in the development and promotion of certain products. [0003] In the application-specific integrated circuit (ASIC) chip with a precision technology of 180 nanometers and below, the leakage current of the chip is relatively low, and the static power consumption is not large. By turning off some dynamic modules, the power consumption can be better controlled. With the further development of technology, 130nm, 90nm, 65nm, 45nm and other technologies with higher precision and smaller volume have been applied more and more. At the same time, it...

AI Technical Summary

Problems solved by technology

However, for the higher precision technology above 130nm, the current leakage control cannot achieve the desired effect. The static power consumption of a single MCU is above 2 mA, which puts a lot of pressure on the battery.

[0005] Under the existing conditions, the function of a mobile phone is often limited by the battery and cannot expand more applications

If simply increasing the capacity of the battery will lead to bulky portable devices, this is obviously not what we want to see

Moreover, limited by technical conditions, the capacity of the battery cannot be increased casually.

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