87results about How to "Reduce wake up time" patented technology

Methods of preventing early awakenings, and improving sleep efficiency in hours 7 and 8 of a period of sleep, by administration of low doses of doxepin (e.g., 1-6 mg).

Methods of preventing early awakenings, and improving sleep efficiency in hours 7 and 8 of a period of sleep, by administration of low doses of doxepin (e.g., 1-6 mg).

A fast wake-up crystal oscillating circuit includes: a crystal oscillator for generating oscillation signal, an amplifier set, a feedback resistor, first and second triggers and an amplifier switch logic. The amplifier set amplifies the oscillation signal. The feedback resistor supplies DC operation bias to the amplifier set. The first trigger has an input connected to the output of the amplifier set so that the first trigger is triggered by the amplified oscillation signal to generate a first clock. The second trigger has an input connected the output of the amplifier set so that the second trigger is triggered by the amplified oscillation signal to generate a second clock, wherein the second trigger has a hysteresis voltage higher than a predetermined value. The amplifier switch logic is connected to the second trigger to gradually decrease the amplification of the amplifier set when detecting that the second trigger generates the second clock.

A therapy utilizing inhaled anesthetic agents (such as desflurane, sevoflurane, isoflurane, or xenon) for the sedation of patients outside of the immediate perioperative space such as in the medical intensive care unit (MICU) and the surgical intensive care unit (SICU). The therapy includes controlled delivery of volatile anesthetic agents to patients undergoing ventilatory support on an ICU ventilator over extended periods of time. A system which provides for the delivery of anesthetic agents includes an anesthetic agent vaporizer element, an anesthetic agent reflector, and a plug-in cassette which contains both a cartridge housing liquid phase volatile anesthetic agent and an anesthetic vapor scrubbing medium.

A delay locked loop circuit is disclosed. The circuit includes a phase detector for comparing the phase of an input clock signal with the phase of a feedback clock signal that is fed back into the phase detector, and for outputting a detection signal. The circuit also includes a control circuit unit for controlling a delay line in response to the detection signal, a delay line for delaying the input clock by a predetermined amount of delay in response to output impedance calibration codes applied to the delay line, and a replica circuit configured to have the same delay conditions as those of an actual clock path to a circuit of the semiconductor device, to receive a delay clock signal of the delay line, and to generate the feedback clock signal.

There is provided a band gap reference voltage generation circuit capable of reducing wake up time during transition from an idle mode to a normal mode and further capable of removing the RF noise of an output voltage. The band gap reference voltage generation circuit includes an operation amplifier for outputting a uniform voltage in accordance with a reference voltage input to an inversion terminal and a non-inversion terminal; a first-type first transistor for outputting a power source voltage in accordance a power down signal; a first-type second transistor for outputting bias current corresponding to an output voltage from the operation amplifier using an output voltage from the first-type first transistor; a reference voltage circuit for supplying a reference voltage to the inversion terminal and the non-inversion terminal using the bias current; a second-type first transistor different from the first-type first transistor for supplying a base voltage to the output port of the operation amplifier in accordance with the power down signal; a start up circuit for driving the entire circuit during power up; a first node between the second-type second transistor and the reference voltage circuit; and an output terminal connected to the first node.

There is provided a bit line voltage supply circuit for reducing leakage current flowing from bit lines to a memory cell without substantially deteriorating the performance of a semiconductor memory device. A bit line voltage switch applies a first supply voltage to a bit line pair in response to a first switch control signal, and applies a second supply voltage having a lower voltage than the first supply voltage to the bit line pair in response to a second switch control signal. A bit line voltage controller controls the first and second switch control signals so that the second supply voltage is supplied to the bit line pair during a standby mode, and the first supply voltage is supplied to the bit line pair when the semiconductor memory device changes from the standby mode to an operational mode for a predetermined time period.