Silicon-based millimeter wave digital attenuator and millimeter wave active phased array antenna

Abstract

The invention provides a silicon-based millimeter wave digital attenuator and a millimeter wave active phased-array antenna, and relates to the technical field of phased-array antennas. The attenuation function of the silicon-based millimeter wave digital attenuator is realized by switching two groups of identical A / B differential circuits of each core attenuation unit, that is, in the whole attenuation range, only one group of circuits of each working core attenuation unit are switched on, and the attenuator circuit formed by combining all the units can be switched on in the aspect of radio frequency small signals. The attenuator circuit is not changed in the aspects of a direct-current working circuit or a direct-current working circuit, that is, the change of radio frequency input and output impedance in the whole attenuation range is very small, the matching of the attenuator circuit and a front-stage circuit and a rear-stage circuit is easily maintained, meanwhile, the working current is basically kept unchanged, and the phase fluctuation is very small when the attenuator works.

Description

Technical Field

[0001] The present invention relates to the technical field of phased array antennas, and in particular to a silicon-based millimeter wave digital attenuator and a millimeter wave active phased array antenna. Background Art

[0002] In millimeter-wave low-cost active phased array antennas, chip integration technology based on silicon-based RF-CMOS technology is usually used to achieve single-chip integration of multi-channel multifunctional active sub-arrays. Taking the silicon-based 8-channel receiving active sub-array chip used in millimeter-wave satellite communication phased array receiving antenna as an example, a single silicon-based chip integrates 8 receiving channels, 8-way beamforming networks, and combined drive amplifiers and other functional units. Among them, a single receiving channel includes a receiving low-noise amplifier, a six-bit digital phase shifter, and a five-bit digital attenuator. The attenuation function of the millimeter-wave satellite communication phased array receiving antenna is mainly used when the phased array antenna is used to suppress the side lobes of the spatial beam, and to provide corresponding amplitude weighting (i.e., signal attenuation) for channels at different positions on the radiation aperture according to certain algorithm requirements. According to the continuity and control method of the attenuation action, it can be divided into analog attenuators and digital attenuators. The analog attenuation control signal is usually an analog signal, which provides a continuously variable attenuation within a certain range; while the digital attenuator is usually controlled by a digital signal, and provides a discrete variable attenuation within a certain range according to the set step. Digital attenuators are currently commonly used in phased array silicon-based CMOS chips because of their high control accuracy, strong anti-interference capability, good compatibility with silicon-based CMOS processes, and easy integration.

[0003] In the above application scenarios, considering the cascade requirements of the front and rear stage circuits, as well as the impact of the attenuator on other core indicators when working, the existing millimeter wave digital attenuator is difficult to meet the following requirements: 1. When the attenuation circuit is working, the input and output impedance does not change significantly to avoid affecting the matching of the front and rear stages and causing fluctuations in the in-band gain. 2. The phase fluctuation caused by setting different attenuation gears should be as small as possible, that is, to achieve the orthogonality of phase modulation and amplitude modulation in the RF link. 3. The circuit chip occupies a small area and is easy to integrate. The control and implementation are compatible with silicon-based CMOS technology. Summary of the invention

[0004] The present invention aims to solve at least one of the above-mentioned technical problems existing in the prior art.

[0005] To this end, a first aspect of the present invention provides a silicon-based millimeter-wave digital attenuator.

[0006] A second aspect of the present invention provides a millimeter wave active phased array antenna.

[0007] The present invention provides a silicon-based millimeter wave digital attenuator, comprising a plurality of core attenuation units connected in parallel between a differential input port and a differential output port; the core attenuation unit comprises: A first transistor having a first end, a second end and a control end, wherein the control end of the first transistor receives a DC bias signal and is coupled to the differential input port to feed a first RF differential input signal; A second transistor having a first end, a second end and a control end, wherein the control end of the second transistor receives a DC bias signal and is coupled to the differential input port to feed a second RF differential input signal; a third transistor having a first end, a second end and a control end, the first end of the third transistor being coupled to the first end of the second transistor, a common node of the third transistor and the second transistor being coupled to the first sub-differential output end, and the control end of the third transistor being coupled to the control end of the first transistor; a fourth transistor having a first end, a second end and a control end, the first end of the fourth transistor being coupled to the first end of the first transistor, a common node of the fourth transistor and the first end of the first transistor being coupled to the second sub-differential output end, and the control end of the fourth transistor being coupled to the control end of the second transistor; a fifth transistor having a first end, a second end and a control end, the first end of the fifth transistor being coupled to the second end of the first transistor and the second end of the second transistor respectively, the second end of the fifth transistor being coupled to the ground, and the control end of the fifth transistor receiving a switching signal; a sixth transistor having a first end, a second end and a control end, the first end of the sixth transistor being coupled to the second end of the third transistor and the second end of the fourth transistor respectively, the second end of the sixth transistor being coupled to the ground, and the control end of the sixth transistor receiving an inverted signal of the switching signal; The switching signal is used to control the fifth transistor and the sixth transistor to switch between an amplification state and a cut-off state; and the first RF differential input signal and the second RF differential input signal are opposite.

[0008] The silicon-based millimeter-wave digital attenuator according to the above technical solution of the present invention may also have the following additional technical features: In the above technical solution, the first transistor, the second transistor, the third transistor and the fourth transistor are defined as upper transistors of the core attenuation unit, and the fifth transistor and the sixth transistor are defined as lower transistors of the core attenuation unit; Among them, the sizes of all upper tubes in a single core attenuation unit are the same and the sizes of all lower tubes are the same, the size of the lower tube has a fixed ratio with the size of the upper tube, and the value of the fixed ratio is the same in each core attenuation unit.

[0009] In the above technical solution, the fixed ratio is set to 2; Among the core attenuation units, the first core attenuation unit and the second core attenuation unit have the same size structure, the size of the upper tube is w, and the size of the lower tube is 2w; The size of the upper tube in the i-th core attenuation unit is , the size of the lower tube is , where i is greater than or equal to 3 and less than or equal to n, and n represents the total number of core attenuation units.

[0010] In the above technical solution, the core attenuation unit further includes: A first inductor, one end of which is coupled to the second end of the first transistor, and the other end of which is coupled to the first end of the fifth transistor; a second inductor, one end of which is coupled to the second end of the second transistor, and the other end of which is coupled to the first end of the fifth transistor; a third inductor, one end of which is coupled to the second end of the third transistor, and the other end of which is coupled to the first end of the sixth transistor; The fourth inductor has one end coupled to the second end of the fourth transistor and the other end coupled to the first end of the sixth transistor.

[0011] In the above technical solution, the core attenuation unit further includes: A first capacitor, one end of which is coupled to the first end of the fifth transistor, and the other end of which is coupled to the second end of the fifth transistor; The second capacitor has one end coupled to the first end of the sixth transistor and the other end coupled to the second end of the sixth transistor.

[0012] In the above technical solution, each core attenuation unit adopts a different switching signal to achieve independent control of each core attenuation unit.

[0013] In the above technical solution, the differential input port includes a positive terminal of an input differential RF signal and a negative terminal of an input differential RF signal, and the differential output port includes a positive terminal of an output differential RF signal and a negative terminal of an output differential RF signal; The input differential RF signal positive terminal receives the first RF differential input signal and is coupled to the control terminal of the first transistor and the control terminal of the third transistor in each core attenuation unit; The negative terminal of the input differential RF signal receives the second RF differential input signal and is coupled to the control terminal of the second transistor and the control terminal of the fourth transistor in each core attenuation unit; The second sub-differential output end of each core attenuation unit is connected in parallel to the output differential RF signal positive end; The first sub-differential output terminal of each core attenuation unit is connected in parallel to the output differential RF signal negative terminal.

[0014] In the above technical solution, the differential input port includes a positive terminal of an input differential RF signal and a negative terminal of an input differential RF signal, and the differential output port includes a positive terminal of an output differential RF signal and a negative terminal of an output differential RF signal; The input differential RF signal positive terminal receives the second RF differential input signal and is coupled to the control terminal of the second transistor and the control terminal of the fourth transistor in each core attenuation unit; The input differential RF signal negative terminal receives the first RF differential input signal and is coupled to the control terminal of the first transistor and the control terminal of the third transistor in each core attenuation unit; The second sub-differential output terminal of each core attenuation unit is connected in parallel to the output differential RF signal negative terminal; The first sub-differential output terminal of each core attenuation unit is connected in parallel to the positive terminal of the output differential RF signal.

[0015] In the above technical solution, the first sub-differential output terminal and the second sub-differential output terminal of each core attenuation unit also receive a DC feed signal; The silicon-based millimeter-wave digital attenuator further includes: The circuit compensation unit adopts the same circuit structure and pipe size as the nth core attenuation unit, wherein the nth core attenuation unit is a core attenuation unit capable of providing a maximum number of radio frequency current components; the difference between the circuit compensation unit and the nth core attenuation unit is that the first sub-differential output end and the second sub-differential output end of the circuit compensation unit only receive a DC feed signal and are not connected to the differential output port.

[0016] The present invention provides a millimeter wave active phased array antenna, comprising a silicon-based millimeter wave digital attenuator as described in any one of the above technical solutions.

[0017] In summary, due to the adoption of the above technical features, the beneficial effects of the present invention are: The attenuation function of the present invention is realized by switching the two identical A / B differential circuits in each core attenuation unit, that is, in the entire attenuation range, there is only one differential circuit in each working core attenuation unit, and the attenuator circuit composed of all units is unchanged from the perspective of RF small signals or DC working circuits. Specifically, the RF input and output impedance of the digital attenuator using the circuit structure of the present invention changes very little in the entire attenuation range, and it is easy to maintain the matching of the attenuator circuit with the front and rear stage circuits; the working current remains basically unchanged; and based on the first two conditions, the phase fluctuation caused by the entire attenuator during operation is very small.

[0018] The source degenerate series inductor introduced in each core attenuation unit can effectively reduce the impedance of the differential trans-catheter gate input and improve the matching condition, which happens to be the input port of the attenuator RF differential signal. This will be beneficial to the cascade matching of the circuit in the chip.

[0019] When one group of A / B circuits in each core attenuation unit is in working state and the other group is in shutdown state, since the two groups of differential circuit structures are exactly the same in size and cross-connected in the gate-drain direction, the equivalent gate-drain parasitic capacitance of the shutdown group tube just plays the role of neutralizing capacitance of the working group tube, effectively improving the reverse isolation of the differential cross-tube and improving stability.

[0020] Since the corresponding paired tubes in each core attenuation unit and the peripheral routing cannot be absolutely symmetrical, the tail current tube (lower tube) also has a channel modulation effect. Therefore, the virtual ground effect of the Q point (common end of the upper tube) is not good due to symmetry. The capacitor connected in parallel to the ground provides a forced virtual ground effect, which improves the circuit's RF performance from the perspective of small signal circuits.

[0021] The introduction of the circuit compensation unit can maintain the working current when the attenuator circuit is in the downshift mode, thereby greatly reducing the change of the working state in this mode.

[0022] The differential transconductor can provide a certain amount of active gain, which can compensate for the small signal gain in the entire link.

[0023] The attenuation in the circuit is determined by the current share ratio corresponding to different core attenuation units, that is, the ratio of the tube size w. In the actual processing process, process fluctuations occur, but the ratio can be kept constant, thus providing the attenuation accuracy of the attenuation circuit.

[0024] Additional aspects and advantages of the present invention will become apparent from the following description or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 It is a schematic diagram of the circuit structure of a core attenuation unit in a silicon-based millimeter-wave digital attenuator according to an embodiment of the present invention; Figure 2 The figure is a schematic diagram of the circuit structure of a silicon-based millimeter-wave digital attenuator according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0027] References to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in an embodiment" that appear throughout this specification do not necessarily all refer to the same embodiment. The verbs "include" and "have" are used as open restrictions in this document, which neither exclude nor require the presence of undescribed features. Unless otherwise explicitly stated, the features recorded in the dependent claims can be freely combined with each other. The use of "one" or "an" (i.e., singular form) to define an element throughout the document does not exclude the possibility of multiple elements. Further, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the term "connection" is used to specify a direct electrical connection between circuit elements, while the terms "coupling" and "coupling" are used to specify an electrical connection between circuit elements that can be direct or can be via one or more other elements. In contrast, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intermediate element. The term "and / or" used here includes any and all combinations of one or more related listed items. When referring to the voltage of a node or terminal, unless otherwise indicated, the voltage is considered to be the voltage between the node and a reference potential (usually ground). In addition, when referring to the potential of a node or terminal, unless otherwise indicated, the potential is considered to refer to the reference potential. The voltage and potential of a given node or a given terminal will be further designated with the same reference numerals. A signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state) is referred to as a "logic signal". The high and low states of different logic signals of the same electronic circuit may be different. In particular, the high and low states of a logic signal may correspond to a voltage or current that may not be completely constant in the high or low state.

[0028] Refer to the following Figure 1 and Figure 2 The silicon-based millimeter-wave digital attenuator provided according to some embodiments of the present invention is described.

[0029] Some embodiments of the present application provide a silicon-based millimeter-wave digital attenuator.

[0030] like Figure 1 As shown, the first embodiment of the present invention proposes a silicon-based millimeter-wave digital attenuator, including a plurality of core attenuation units connected in parallel between a differential input port and a differential output port; the core attenuation unit includes at least a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6.

[0031] It should be noted that, except for transistors of specifically specified models in the present disclosure, the remaining transistors may be any suitable semiconductor switching devices, such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET), Junction Field Effect Transistor (JFET) or Insulated Gate Bipolar Transistor (IGBT) and other suitable power switching devices.

[0032] For the convenience of explanation, in the present disclosure, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are all MOS transistors for explanation. The above transistors all have a first end, a second end and a control end, wherein the first end corresponds to the drain of the MOS tube, the second end corresponds to the source of the MOS tube, and the control end corresponds to the gate of the MOS tube. It can be understood that the corresponding relationship between the terminals of the above transistors and the poles of the MOS tube is only a schematic representation, and those skilled in the art can refer to the circuit structure of the present invention to adjust the above corresponding relationship according to the model and polarity of the tube.

[0033] like Figure 1 As shown, in the core attenuation unit proposed in the present disclosure, the first transistor M1, the second transistor M2 and the fifth transistor M5 form a differential circuit group A, and the third transistor M3, the fourth transistor M4 and the sixth transistor M6 form a differential circuit group B. The two groups of differential circuits are structurally consistent, and the specific connection relationship is as follows: The control end of the first transistor M1 receives a DC bias signal and is coupled to the differential input port to feed a first RF differential input signal; the control end of the second transistor M2 receives a DC bias signal and is coupled to the differential input port to feed a second RF differential input signal. The first RF differential input signal and the second RF differential input signal are opposite, specifically, two signals with the same amplitude and opposite polarity.

[0034] The first end of the third transistor M3 is coupled to the first end of the second transistor M2, and the common node of the two is coupled to the first sub-differential output terminal DN, and the control end of the third transistor M3 is coupled to the control end of the first transistor M1; the first end of the fourth transistor M4 is coupled to the first end of the first transistor M1, and the common node of the two is coupled to the second sub-differential output terminal DP, and the control end of the fourth transistor M4 is coupled to the control end of the second transistor M2; the first sub-differential output terminal DN and the second sub-differential output terminal DP are coupled to the differential output port of the attenuator.

[0035] The DC bias signal is used to bias the first transistor M1 , the second transistor M2 , the third transistor M3 and the fourth transistor M4 in the amplification region, so that the four transistors are in an amplification state.

[0036] The first end of the fifth transistor M5 is coupled to the second end of the first transistor M1 and the second end of the second transistor M2 respectively, the second end of the fifth transistor M5 is coupled to the ground, and the control end of the fifth transistor M5 receives the switching signal Vct; the first end of the sixth transistor M6 is coupled to the second end of the third transistor M3 and the second end of the fourth transistor M4 respectively, the second end of the sixth transistor M6 is coupled to the ground, and the control end of the sixth transistor M6 receives the inverted signal of the switching signal The switching signal is used to control the fifth transistor M5 and the sixth transistor M6 to switch between the amplification state and the cut-off state. It can be understood that the states of the fifth transistor M5 and the sixth transistor M6 are opposite, that is, when the fifth transistor M5 is in the amplification state, the sixth transistor M6 is in the cut-off state.

[0037] The differential input port includes an input differential RF signal positive terminal GPi and an input differential RF signal negative terminal GNi, and the differential output port includes an output differential RF signal positive terminal DPo and an output differential RF signal negative terminal DNo.

[0038] In one embodiment, the input differential RF signal positive terminal GPi receives a first RF differential input signal, and is coupled to the control terminal of the first transistor M1 and the control terminal of the third transistor M3 in each core attenuation unit, and a common node of the control terminal of the first transistor M1 and the control terminal of the third transistor M3 is defined as a first sub-differential input terminal GP; the input differential RF signal negative terminal GNi receives a second RF differential input signal, and is coupled to the control terminal of the second transistor M2 and the control terminal of the fourth transistor M4 in each core attenuation unit, and a common node of the control terminal of the second transistor M2 and the control terminal of the fourth transistor M4 is defined as a second sub-differential input terminal GN; the second sub-differential output terminal DP of each core attenuation unit is connected in parallel to the output differential RF signal positive terminal DPo; the first sub-differential output terminal DN of each core attenuation unit is connected in parallel to the output differential RF signal negative terminal DNo.

[0039] It can be understood that the connection positions of the input differential RF signal positive terminal GPi and the input differential RF signal negative terminal GNi in the above embodiment can be swapped, but the connection positions of the output differential RF signal positive terminal DPo and the output differential RF signal negative terminal DNo should also be adjusted accordingly when swapping.

[0040] Specifically, in another embodiment, the positive end of the input differential RF signal receives the second RF differential input signal, and is coupled to the control end of the second transistor M2 and the control end of the fourth transistor M4 in each core attenuation unit; the negative end of the input differential RF signal receives the first RF differential input signal, and is coupled to the control end of the first transistor M1 and the control end of the third transistor M3 in each core attenuation unit; the second sub-differential output end of each core attenuation unit is connected in parallel to the negative end of the output differential RF signal; the first sub-differential output end of each core attenuation unit is connected in parallel to the positive end of the output differential RF signal.

[0041] In the above core attenuation unit, the differential circuit of group A is taken as an example for explanation. The differential circuit of group A constitutes a differential transconductance pair structure with a tail current source, wherein the first transistor M1 and the second transistor M2 constitute a differential transconductance pair, and the RF differential input signal enters the gates of the first transistor M1 and the second transistor M2 respectively, and the common end of the first transistor M1 and the second transistor M2 serves as the RF virtual ground node Q. Whether each group of differential circuits is turned on and the current size when turned on is determined by the tail current source tube (the lower tube, and the fifth transistor M5 for the differential circuit of group A). ​​The lower tube works in the saturation region to form a tail current source structure, that is, the voltage loaded on the gate end of the lower tube under the control of the switching signal Vct switches between the saturation region bias voltage and the ground potential. It can be understood that the switching signal Vct is a high-low level digital control signal.

[0042] It is defined that each core attenuator unit in the attenuator is in the base state when the differential circuit of group A is turned on and the differential circuit of group B is turned off (i.e., the output end is all positive current converging, and the attenuation is minimum at this time). If the differential circuit of group B is turned on and the differential circuit of group A is turned off in any core attenuator unit, the core attenuator unit provides a reverse RF amplification current, which switches from providing a positive enhancement current to a negative offset current from the final differential output port, thereby reducing the total output node RF current.

[0043] In some embodiments, the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are defined as upper transistors of the core attenuation unit, and the fifth transistor M5 and the sixth transistor M6 are defined as lower transistors of the core attenuation unit; Among them, the size of all upper tubes in a single core attenuation unit is the same and the size of all lower tubes is the same. The size of the lower tube has a fixed ratio with the size of the upper tube, and the value of the fixed ratio is the same in each core attenuation unit. What determines the attenuation in the circuit is the current share ratio corresponding to different core attenuation units, that is, the ratio of the size of the upper tube to the size of the lower tube. Even if process fluctuations occur in the actual processing process, the ratio can remain unchanged well, thereby ensuring the attenuation accuracy of the attenuation circuit.

[0044] The DC bias signal of the upper tube is biased to a suitable voltage position according to the amplification requirements. In some embodiments, each core attenuation unit uses a different switching signal Vct to achieve independent control of each core attenuation unit.

[0045] In a specific implementation, the fixed ratio is set to 2; Among the core attenuation units, the first core attenuation unit and the second core attenuation unit have the same size structure, the size of the upper tube is w, and the size of the lower tube is 2w; The size of the upper tube in the i-th core attenuation unit is , the size of the lower tube is , where i is greater than or equal to 3 and less than or equal to n, and n represents the total number of core attenuation units.

[0046] by Figure 2 The embodiment shown is used as an example for explanation. Figure 2 The digital attenuator shown includes core attenuation units K1, K2, K3...Kn placed in parallel, where w=2um (micrometer), n=7, and the structural dimensions of the core attenuation unit K1 and the core attenuation unit K2 are exactly the same. Assume that the number of RF currents provided by the core attenuation units K1 and K2 is 1, and the differential circuit of each core attenuation unit A group corresponds to the positive current, and the differential circuit of the group B corresponds to the negative current. Then the total current of the entire attenuator is 1, 1, 2, 4, 8, 16, 32, respectively, and the sign is determined by the opening of the differential circuit of the group A / B. By configuring the control signal of the tail current source tube (lower tube), a discrete current share (strength) combination can be obtained at the output end of the digital attenuator (i.e., the differential output port), including 32, 31, 30...3, 2, 1 (in units), with the RF signal power as the amplitude measurement standard, and the attenuation provided from small to large relative to the base state is 20lg (32 / 31), 20lg (32 / 30),...20lg (32 / 2), 20lg (32 / 1), 20lg (0). Note that the attenuation of 20lg (0) is used to indicate infinite attenuation.

[0047] In some embodiments, the core attenuation unit further includes a first inductor L1 , a second inductor L2 , a third inductor L3 and a fourth inductor L4 .

[0048] One end of the first inductor L1 is coupled to the second end of the first transistor M1, and the other end is coupled to the first end of the fifth transistor M5; one end of the second inductor L2 is coupled to the second end of the second transistor M2, and the other end is coupled to the first end of the fifth transistor M5; one end of the third inductor L3 is coupled to the second end of the third transistor M3, and the other end is coupled to the first end of the sixth transistor M6; one end of the fourth inductor L4 is coupled to the second end of the fourth transistor M4, and the other end is coupled to the first end of the sixth transistor M6.

[0049] The first inductor L1, the second inductor L2, the third inductor L3 and the fourth inductor L4 are used as source degenerate series inductors to effectively reduce the impedance of the differential transconductance pair tube gate input and improve the matching condition. The differential transconductance pair tube gate is just the input port of the attenuator RF differential signal, which will be beneficial to the cascade matching of the circuit in the chip.

[0050] In some embodiments, the core attenuation unit further includes a first capacitor C1 and a second capacitor C2.

[0051] One end of the first capacitor C1 is coupled to the first end of the fifth transistor M5, and the other end is coupled to the second end of the fifth transistor M5; one end of the second capacitor C2 is coupled to the first end of the sixth transistor M6, and the other end is coupled to the second end of the sixth transistor M6.

[0052] The above-mentioned first capacitor C1 and second capacitor C2 are both capacitors connected in parallel to the ground. Since the corresponding paired tubes in each core attenuation unit and the peripheral wiring cannot be absolutely symmetrical, the tail current source tube also has a channel modulation effect. Therefore, the RF virtual ground node Q does not have a good effect by relying on symmetrical virtual ground. The use of capacitors connected in parallel to the ground can provide a forced virtual ground effect, which improves the RF performance of the circuit from the perspective of small signal circuits.

[0053] Furthermore, the first sub-differential output terminal DN and the second sub-differential output terminal DP of each core attenuation unit both receive a DC feed signal Vdd. In some embodiments, the silicon-based millimeter-wave digital attenuator further includes a circuit compensation unit Kc.

[0054] The circuit compensation unit Kc adopts the same circuit structure and pipe size as the nth core attenuation unit, and the nth core attenuation unit is a core attenuation unit that can provide the maximum number of RF current components; Figure 2 As shown, the circuit compensation unit Kc has the same circuit structure as the core attenuation unit Kn, and the corresponding tubes have the same size, but the difference is that the first sub-differential output terminal DN and the second sub-differential output terminal DP of the circuit compensation unit Kc only receive the DC feed signal Vdd and are not connected to the differential output port. That is, the drain end of the differential transconductance pair tube in the circuit compensation unit Kc is not connected to the output differential RF signal positive terminal DPo and the output differential RF signal negative terminal DNo, but is only connected to the drain-level DC feed end to receive the DC feed signal Vdd.

[0055] When the core attenuation units K1~K7 are all working, the internal A / B differential circuits are both in the off state. When all the K7 core attenuation units (A / B groups) are turned off, one of the current compensation units is turned on. At this time, the attenuator changes to a downshift working state, that is, the attenuator composed of the core attenuation units K1~K6 works according to the aforementioned principle, and the current compensation unit provides current compensation, that is, the RF input impedance, output impedance, and working current outside the attenuator remain unchanged.

[0056] A second embodiment of the present invention provides a millimeter wave active phased array antenna, comprising the silicon-based millimeter wave digital attenuator as described in any of the above embodiments.

[0057] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0058] Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A silicon-based millimeter-wave digital attenuator, characterized in that: It includes a plurality of core attenuation units connected in parallel between the differential input port and the differential output port; The core attenuation unit comprises: A first transistor having a first end, a second end and a control end, wherein the control end of the first transistor is fed with a DC bias signal and is coupled to the differential input port to receive a first RF differential input signal; A second transistor having a first end, a second end and a control end, wherein the control end of the second transistor is fed with a DC bias signal and is coupled to the differential input port to receive a second RF differential input signal; a third transistor having a first end, a second end and a control end, the first end of the third transistor being coupled to the first end of the second transistor, a common node of the third transistor and the second transistor being coupled to the first sub-differential output end, and the control end of the third transistor being coupled to the control end of the first transistor; a fourth transistor having a first end, a second end and a control end, the first end of the fourth transistor being coupled to the first end of the first transistor, a common node of the fourth transistor and the first end of the first transistor being coupled to the second sub-differential output end, and the control end of the fourth transistor being coupled to the control end of the second transistor; a fifth transistor having a first end, a second end and a control end, the first end of the fifth transistor being coupled to the second end of the first transistor and the second end of the second transistor respectively, the second end of the fifth transistor being coupled to the ground, and the control end of the fifth transistor receiving a switching signal; a sixth transistor having a first end, a second end and a control end, the first end of the sixth transistor being coupled to the second end of the third transistor and the second end of the fourth transistor respectively, the second end of the sixth transistor being coupled to the ground, and the control end of the sixth transistor receiving an inverted signal of the switching signal; The switching signal is used to control the fifth transistor and the sixth transistor to switch between an amplification state and a cut-off state; and the first RF differential input signal and the second RF differential input signal are opposite.

2. The silicon-based millimeter-wave digital attenuator according to claim 1, characterized in that: The first transistor, the second transistor, the third transistor and the fourth transistor are defined as upper transistors of the core attenuation unit, and the fifth transistor and the sixth transistor are defined as lower transistors of the core attenuation unit; Among them, the sizes of all upper tubes in a single core attenuation unit are the same and the sizes of all lower tubes are the same, the size of the lower tube has a fixed ratio with the size of the upper tube, and the value of the fixed ratio is the same in each core attenuation unit.

3. The silicon-based millimeter-wave digital attenuator according to claim 2, characterized in that: The fixed ratio has a value of 2; Among the core attenuation units, the first core attenuation unit and the second core attenuation unit have the same size structure, the size of the upper tube is w, and the size of the lower tube is 2w; The size of the upper tube in the i-th core attenuation unit is , the size of the lower tube is , where i is greater than or equal to 3 and less than or equal to n, and n represents the total number of core attenuation units.

4. The silicon-based millimeter-wave digital attenuator according to claim 1, characterized in that: The core attenuation unit also includes: A first inductor, one end of which is coupled to the second end of the first transistor, and the other end of which is coupled to the first end of the fifth transistor; a second inductor, one end of which is coupled to the second end of the second transistor, and the other end of which is coupled to the first end of the fifth transistor; a third inductor, one end of which is coupled to the second end of the third transistor, and the other end of which is coupled to the first end of the sixth transistor; The fourth inductor has one end coupled to the second end of the fourth transistor and the other end coupled to the first end of the sixth transistor.

5. The silicon-based millimeter-wave digital attenuator according to claim 1, characterized in that: The core attenuation unit also includes: A first capacitor, one end of which is coupled to the first end of the fifth transistor, and the other end of which is coupled to the second end of the fifth transistor; The second capacitor has one end coupled to the first end of the sixth transistor and the other end coupled to the second end of the sixth transistor.

6. The silicon-based millimeter-wave digital attenuator according to claim 1, characterized in that: Each core attenuation unit uses a different switching signal to achieve independent control of each core attenuation unit.

7. The silicon-based millimeter-wave digital attenuator according to claim 1, characterized in that: The differential input port includes a positive terminal for inputting differential radio frequency signals and a negative terminal for inputting differential radio frequency signals, and the differential output port includes a positive terminal for outputting differential radio frequency signals and a negative terminal for outputting differential radio frequency signals; The input differential RF signal positive terminal receives the first RF differential input signal and is coupled to the control terminal of the first transistor and the control terminal of the third transistor in each core attenuation unit; The negative terminal of the input differential RF signal receives the second RF differential input signal and is coupled to the control terminal of the second transistor and the control terminal of the fourth transistor in each core attenuation unit; The second sub-differential output end of each core attenuation unit is connected in parallel to the output differential RF signal positive end; The first sub-differential output terminal of each core attenuation unit is connected in parallel to the output differential RF signal negative terminal.

8. The silicon-based millimeter-wave digital attenuator according to claim 1, characterized in that: The differential input port includes a positive terminal for inputting differential radio frequency signals and a negative terminal for inputting differential radio frequency signals, and the differential output port includes a positive terminal for outputting differential radio frequency signals and a negative terminal for outputting differential radio frequency signals; The input differential RF signal positive terminal receives the second RF differential input signal and is coupled to the control terminal of the second transistor and the control terminal of the fourth transistor in each core attenuation unit; The input differential RF signal negative terminal receives the first RF differential input signal and is coupled to the control terminal of the first transistor and the control terminal of the third transistor in each core attenuation unit; The second sub-differential output terminal of each core attenuation unit is connected in parallel to the output differential RF signal negative terminal; The first sub-differential output terminal of each core attenuation unit is connected in parallel to the positive terminal of the output differential RF signal.

9. The silicon-based millimeter-wave digital attenuator according to claim 7 or 8, characterized in that: The first sub-differential output terminal and the second sub-differential output terminal of each core attenuation unit also receive a DC feed signal; The silicon-based millimeter-wave digital attenuator further includes: The circuit compensation unit adopts the same circuit structure and pipe size as the nth core attenuation unit, wherein the nth core attenuation unit is a core attenuation unit capable of providing a maximum number of radio frequency current components; the difference between the circuit compensation unit and the nth core attenuation unit is that the first sub-differential output end and the second sub-differential output end of the circuit compensation unit only receive a DC feed signal and are not connected to the differential output port.

10. A millimeter wave active phased array antenna, characterized in that: The invention comprises the silicon-based millimeter-wave digital attenuator as claimed in any one of claims 1 to 9.

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