Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication

Abstract

Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Provisional Patent Application No. 60 / 681,940, filed May 17, 2005, the entire disclosure of which is incorporated herein by reference. technical field [0003] The present invention relates to lattice mismatched semiconductor heterostructures, and more particularly to selective channel material regrowth associated with integration of dissimilar semiconductor materials. Background technique [0004] As the operating speed and computing power of microelectronic devices increase, there is a demand for increasing the complexity and functionality of semiconductor structures used to manufacture the devices. The heterogeneous integration of dissimilar semiconductor materials, such as III-V materials such as gallium arsenide, gallium nitride, indium aluminum arsenide and / or germanium with silicon or silicon germanium substrates, is important for increasing the functionality and performanc...

AI Technical Summary

Problems solved by technology

However, an important limitation of epitaxial necks is the size of the area to be applied

Images