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Systems, processes and integrated circuits for improved packet scheduling of media over packet

a technology of integrated circuits and media over packets, applied in the field of integrated circuits, systems and processes for packet communication, can solve problems such as delay jitter, packet loss, and packets not only being lost, and never reaching their destination

Inactive Publication Date: 2006-01-12
WELIN ANDREW M
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The packets arrive out of order sometimes. The packets are not only merely delayed relative to the source, but also have delay jitter.
Delay jitter is variability in packet delay, or variation in timing of packets relative to each other due to buffering within nodes in the same routing path, and differing delays and / or numbers of hops in different routing paths.
Packets may even be actually lost and never reach their destination.
Packets that are not literally lost, but are substantially delayed when received, may have to be discarded at the destination nonetheless because they have lost their usefulness at the receiving end.
The user can rarely tolerate as much as half a second (500 milliseconds) of delay, and even then may avoid using VOP if its quality is perceptibly inferior to other readily available and albeit more expensive transmission alternatives.
Such avoidance may occur with delays of 250 milliseconds or even less, while Internet phone technology hitherto may have suffered from end-to-end delays of as much as 600 milliseconds or more.
Hitherto, one approach has stored the arriving packets in a buffer, but if the buffer is too short, packets are lost.
If the buffer is too long, it contributes to delay.
However, the delay inherent in the request-for-retransmission process currently may reduce the usefulness of TCP and other ARQ (automatic retransmission request) approaches as a means of enhancing VOP communications.
For every frame of compressed speech in a packet, loss of that packet means loss of each frame in that packet.
There then arises the problem how to create 160 bits or more of lost compressed speech.
Reduction of packet loss and late packet handling strategy are very important challenges in advancing VOP technology.

Method used

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  • Systems, processes and integrated circuits for improved packet scheduling of media over packet
  • Systems, processes and integrated circuits for improved packet scheduling of media over packet
  • Systems, processes and integrated circuits for improved packet scheduling of media over packet

Examples

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implementation examples

[0475] The system description herein follows a single packet from its arrival to decoding, inclusion into a voice stream and return of the storage occupied by the packet. Below the phrases “linked list”, “list” and “queue” are used interchangeably.

[0476] Details are described in three phases. Phase 1“Packet entities and lists” follows a single packet from arrival to its inclusion in the egress data stream. The packet is described as it “visits” different data structures. Phase 1 bypasses a layer of problems and solutions added on by the special constraints of real-time processing. Thus Phase 2 “Real Time behavior” describes underlying real-time issues and the system solutions. Phase 3 adds more description of “The four linked lists.”

[0477] Phase 1—Packet Entities and Lists

[0478] The arrival of packets is unpredictable. Advantageously, the selected data structures used in this example are linked lists. Linked lists are well suited to handle unpredictable variations of order.

[0479]...

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PUM

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Abstract

A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.

Description

[0001] This application is a divisional of prior application Ser. No. 09 / 785,768, filed on Feb. 16, 2001, which claimed priority from Provisional Application No. 60 / 191,375, filed Mar. 22, 2000.FIELD OF THE INVENTION [0002] The present invention relates to the fields of integrated circuits, networking, systems and processes for packet communications, and especially communication of real time information such as voice, audio, images, video and other real time information over packet. BACKGROUND OF THE INVENTION [0003] The Internet has long been usable for Internet file transfers and e-mail by packet switched communication. A different technology called circuit switched communication is used in the PSTN (public switched telephone network) wherein a circuit is dedicated to each phone call regardless of whether the circuit is being communicated over in silent periods. Packet switched networks do not dedicate a channel, thereby sharing a pipe or channel among many communications and thei...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G01R31/08H04L12/66H04L12/28G10L11/02H04L12/56H04L12/64H04L47/2416H04L47/32H04L47/56H04M3/00
CPCG10L25/78H04M1/2535H04L12/6418H04L29/06027H04L47/10H04L47/24H04L47/2416H04L47/245H04L47/28H04L47/32H04L47/34H04L47/564H04L2012/6464H04L2012/6481H04L2012/6489H04L65/80H04L47/62H04L2012/6494H04M1/253H04L12/5693H04L47/50H04L47/6235H04L47/562H04L47/283H04L65/1101
Inventor WELIN, ANDREW M.
Owner WELIN ANDREW M
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