Packaging processing method and system for storage chip and medium

Abstract

The invention provides a packaging processing method and system for a storage chip and a medium, and belongs to the technical field of semiconductor packaging. The method comprises the following steps: constructing an initial three-dimensional model of a packaging body, cleaning and detecting a bare chip, and correcting the model after laser cutting; electrical, thermal and stress performances are simulated and optimized, multiple chips are integrated by adopting an SiP technology, and three-dimensional wiring of a substrate is completed; and after three times of cleaning, a molding process is optimized through mold flow simulation, a system-level mainboard is connected by utilizing a BGA technology, and finally, a full-performance test is completed. Through multi-stage simulation and process collaborative optimization, the packaging density, reliability and manufacturing yield of the storage chip are improved, and the method is suitable for industrial production of high-density integrated storage devices.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a packaging and processing method, system, and medium for a memory chip. Background Art

[0002] As semiconductor technology evolves toward higher density and higher performance, memory chip packaging faces the dual challenges of multi-chip integration and process precision. On the one hand, a single chip cannot meet complex functional requirements. While system-in-package (SiP) technology can achieve functional modularization by integrating memory chips and control chips, it can easily lead to issues such as signal interference, thermal management, and interconnect reliability. On the other hand, traditional packaging processes rely on empirical design, often leading to package stress concentration and molding compound fill defects, which affect the long-term stability of the chip. Existing technologies lack systematic planning for the sequence of multi-chip integration and substrate interconnection, which can easily lead to layout conflicts or a surge in interconnect complexity. Furthermore, the application of simulation technology is limited, lacking a closed-loop optimization process from "structural design to process simulation to manufacturing verification," making it difficult to simultaneously address electrical performance, thermal performance, and process feasibility. Therefore, a simulation-driven memory chip packaging and processing method is urgently needed. Summary of the Invention

[0003] This application aims to provide a method, system, and medium for packaging and processing memory chips. First, an initial three-dimensional model of the package is constructed based on the die design specifications. The die is cleaned and inspected once, then laser-cut and cleaned again to obtain individual chip units. The actual chip parameters are extracted to modify the three-dimensional model. Simulation technology is used to analyze electrical, thermal, and stress distribution to optimize the package structure. Multiple functional chip units are integrated using SiP technology, and signal interaction and power distribution are achieved through substrate 3D routing based on optimized design. The interconnected package substrate is cleaned three times, and the molding process is completed by optimizing the molding compound flow path through mold flow simulation. BGA packaging technology is used to electrically connect the package to the system-level motherboard. Finally, the package undergoes performance testing, fault diagnosis, and extreme environmental stability testing. This method, through multi-stage simulation-driven design, coordinated SiP and BGA processes, staged cleaning control, and a full-process testing system, effectively addresses signal interference, thermal management, and process reliability issues in multi-chip integration, improving packaging density, yield, and device environmental adaptability. It is suitable for the industrialized packaging production of advanced memory chips.

[0004] The present application provides a method for packaging and processing a memory chip, comprising the following steps: An initial three-dimensional virtual model of the package is constructed based on the design specifications and target performance indicators of the chip die, and the chip die is cleaned and inspected once, then cut using a laser stealth cutting process and cleaned twice to obtain independent chip units; Extracting actual size and position parameters of the independent chip unit, revising the initial three-dimensional virtual model, and obtaining a revised three-dimensional virtual model; Using simulation technology to analyze the electrical performance, thermal performance and stress distribution of the modified three-dimensional virtual model to optimize the packaging structure design; Adopt SiP technology to integrate multiple types of functional chip units, and realize signal interaction and power distribution through three-dimensional wiring of substrate based on optimized design; The interconnected package substrate is cleaned three times, and the mold flow simulation technology is used to optimize the flow path of the molding compound to complete the molding process to form a protective shell; Using BGA packaging technology, the package is connected to the system-level motherboard through a solder ball array to achieve electrical connection between the package and the motherboard; The packaged body is fully tested, including performance testing, fault diagnosis, and testing its stability, durability and wide temperature adaptability by simulating extreme environments.

[0005] In the memory chip packaging and processing method described in this application, the three-dimensional virtual model of the package is constructed based on the design specifications and target performance indicators of the chip die, specifically: Use 3D modeling software to build an initial 3D model of the package, combining the die dimensions, pinout, functional partitions, and pre-set package size limits. In the initial three-dimensional model, a preliminary layout of the electrical connection structure, heat dissipation channels and stress buffering areas is pre-set.

[0006] Among them, in the packaging and processing method of a memory chip described in this application, the cleaning and testing of the chip die once includes: Plasma-assisted cleaning technology is used to excite an inert gas using a radio frequency power supply to generate plasma to remove the surface oxide layer of the chip die; Cleaning the chip die with ultrasonic deionized water to remove surface particle contaminants and organic residues; The chip die is scanned and imaged line by line by automatic optical inspection equipment, and surface defects are identified by image processing algorithms and compared with standard templates, and unqualified chips are automatically marked.

[0007] Among them, in the packaging and processing method of a memory chip described in this application, the cutting using the laser invisible cutting process is specifically as follows: According to the material properties of the chip die, a laser with an appropriate wavelength is selected and the laser power and cutting speed are adjusted; The chip die is moved by a high-precision motion platform and observed in real time by a coaxial visual monitoring system to complete high-precision cutting of the chip unit.

[0008] In the memory chip packaging and processing method described in the present application, the actual size and position parameters of the independent chip unit are extracted, and the initial three-dimensional virtual model is corrected to obtain the corrected three-dimensional virtual model, specifically: Obtain the actual size, cutting accuracy and pin position deviation data of the chip unit through micro-measuring equipment; The data is imported into the three-dimensional modeling software, the chip unit part in the initial model is sized and calibrated, and the matching parameters of the electrical connection structure and the package body are updated synchronously.

[0009] Among them, in the packaging and processing method of a memory chip described in this application, the SiP technology is used to integrate multiple types of functional chip units, including: Based on simulation-optimized packaging structure design, layout planning is performed for power management chips, data processing chips, and storage chips to shorten the signal transmission path between chips; Multi-layer wiring of the substrate is performed using 3D wiring design software, and simulation software is used to verify the signal integrity and power integrity of the wiring to achieve stable signal interaction and power distribution among multiple chips.

[0010] Among them, in the packaging and processing method of a memory chip described in the present application, the molding and forming of the protective shell is completed by optimizing the flow path of the molding material through mold flow simulation technology, specifically: Establish a fluid dynamics simulation model for the package and set the location and number of molding compound injection points based on the package structure; The flow state of the molding compound under different injection speeds and pressures is simulated, and the changes in its flow front, pressure and temperature are analyzed. After simulation and comparison of multiple sets of process parameters, the optimal molding process parameters are determined.

[0011] Among them, in the packaging and processing method of a memory chip described in this application, the use of BGA packaging technology includes: Preheating the package and system-level motherboard by infrared heating; The solder ball array is placed on the corresponding pad with the help of high-precision placement equipment; The package body and the system-level motherboard are placed in a reflow oven and sequentially go through preheating, temperature equalization, reflow, cooling and other temperature zone treatments to achieve welding of the package body and the system-level motherboard.

[0012] In a second aspect, the present application provides a memory chip packaging and processing system, the system comprising: a memory and a processor, the memory comprising a program for a memory chip packaging and processing method, the program for a memory chip packaging and processing method, when executed by the processor, implementing the following steps: An initial three-dimensional virtual model of the package is constructed based on the design specifications and target performance indicators of the chip die, and the chip die is cleaned and inspected once, then cut using a laser stealth cutting process and cleaned twice to obtain independent chip units; Extracting actual size and position parameters of the independent chip unit, revising the initial three-dimensional virtual model, and obtaining a revised three-dimensional virtual model; Using simulation technology to analyze the electrical performance, thermal performance and stress distribution of the modified three-dimensional virtual model to optimize the packaging structure design; Adopt SiP technology to integrate multiple types of functional chip units, and realize signal interaction and power distribution through three-dimensional wiring of substrate based on optimized design; The interconnected package substrate is cleaned three times, and the mold flow simulation technology is used to optimize the flow path of the molding compound to complete the molding process to form a protective shell; Using BGA packaging technology, the package is connected to the system-level motherboard through a solder ball array to achieve electrical connection between the package and the motherboard; The packaged body is fully tested, including performance testing, fault diagnosis, and testing its stability, durability and wide temperature adaptability by simulating extreme environments.

[0013] In a third aspect, the present application also provides a computer-readable storage medium, which includes a packaging and processing method program for a memory chip. When the packaging and processing method program for a memory chip is executed by a processor, the steps of the packaging and processing method for a memory chip as described in any one of the above items are implemented.

[0014] As can be seen from the above, the core of the memory chip packaging and processing method, system, and medium provided in the embodiments of this application is to improve packaging performance through multi-stage cleaning and testing, simulation-driven design optimization, SiP and BGA collaborative processes, and a full-process testing system. First, an initial three-dimensional model of the package is constructed. The die is cleaned and tested once, and then cleaned again after laser cutting. The actual parameters are extracted to correct the model. Simulation technology is used to analyze electrical performance, thermal performance, and stress distribution to optimize the structural design. SiP technology is used to integrate multiple types of chip units, and signal interaction and power distribution are achieved through three-dimensional wiring of the substrate. The interconnected substrate is cleaned three times, and the molding compound flow path is optimized through mold flow simulation to complete the molding process. The package is connected to the system-level motherboard using BGA technology. Finally, a comprehensive test is carried out, including performance testing, fault diagnosis, and extreme environment stability testing. This method forms a "design-simulation-manufacturing-testing" closed loop through the coordination of electrical / thermal / stress simulation and mold flow simulation, a reasonable sequence of SiP integration and BGA interconnection, a phased cleaning strategy and full-process testing, thereby improving packaging density, signal integrity, environmental adaptability and process yield, and is suitable for the industrial production of high-density integrated memory devices.

[0015] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or understood by practicing the embodiments of the present application. The objectives and other advantages of the present application can be achieved and obtained through the structures particularly pointed out in the written description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A flowchart of a memory chip packaging and processing method provided in an embodiment of the present application; Figure 2 A flowchart of a packaging method for a memory chip provided in an embodiment of the present application for constructing a three-dimensional virtual model of a packaging body; Figure 3 A flowchart of a method for packaging and processing a memory chip provided in an embodiment of the present application for performing a cleaning and inspection on the chip die; Figure 4 A flowchart of a memory chip packaging and processing method using a laser invisible cutting process is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work fall within the scope of protection of the present application.

[0019] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions.

[0020] Please refer to Figure 1 , Figure 1 This is a flow chart of a memory chip packaging and processing method in some embodiments of the present application. This memory chip packaging and processing method is used in terminal devices, such as computers, mobile phone terminals, etc. This memory chip packaging and processing method includes the following steps: S101, constructing an initial three-dimensional virtual model of the package body based on the design specifications and target performance indicators of the chip bare die, cleaning and inspecting the chip bare die once, then cutting the chip bare die using a laser stealth cutting process and performing a secondary cleaning to obtain independent chip units; S102, extracting actual size and position parameters of the independent chip unit, correcting the initial three-dimensional virtual model, and obtaining a corrected three-dimensional virtual model; S103, using simulation technology to analyze the electrical performance, thermal performance and stress distribution of the modified three-dimensional virtual model to optimize the packaging structure design; S104, using SiP technology to integrate multiple types of functional chip units, based on the optimized design and through the substrate three-dimensional wiring to achieve signal interaction and power distribution; S105, the interconnected packaging substrate is cleaned three times, and the molding flow path is optimized through a mold flow simulation technology to complete molding forming a protective shell; S106, using BGA packaging technology, the package is connected to the system-level mainboard through a solder ball array to achieve electrical connection between the package and the mainboard; S107, the completed package is comprehensively tested, including performance testing, fault diagnosis, and detection of stability, durability, and wide temperature adaptability through simulation of extreme environments.

[0021] The present invention systematically improves packaging performance and reliability with simulation-driven and multi-process collaboration as its core. First, based on the design specifications of the die, such as the die dimensions, pin distribution, functional partitioning, and the preset package size restrictions, a 3D modeling software is used to construct an initial 3D virtual model of the package body. The preliminary layout of the electrical connection structure, heat dissipation channel, and stress buffer area is pre-set in the model. Subsequently, the die is sequentially cleaned with plasma-assisted cleaning technology to remove the surface oxide layer, and ultrasonic deionized water cleaning is used to remove particulate contaminants and organic residues. Surface defects are then identified by line-by-line scanning and imaging using automated optical inspection equipment. Unqualified chips are then marked, completing a single cleaning and inspection. Next, a laser with an appropriate wavelength is selected based on the material properties of the die, and the laser power and cutting speed are adjusted. The die movement is controlled by a high-precision motion platform, and a coaxial visual monitoring system is used for real-time observation. After the laser stealth cutting is completed, a secondary cleaning is performed to obtain an independent chip unit. After obtaining the independent chip unit, its actual size, cutting accuracy and pin position deviation data are obtained through micro-measurement equipment. The data is imported into the 3D modeling software, and the chip unit part in the initial model is corrected in size and calibrated in position. The matching parameters of the electrical connection structure and the package body are simultaneously updated to obtain a corrected 3D virtual model. Then, simulation technology is used to analyze the electrical performance (such as signal integrity), thermal performance (such as heat dissipation path) and stress distribution (such as solder joint stress concentration points) of the corrected 3D virtual model to optimize the package structure design. On the basis of structural design optimization, the layout planning of power management chip, data processing chip and storage chip is carried out based on the simulation optimization results, the signal transmission path between chips is shortened, and SiP technology is used to integrate multiple types of functional chip units. The substrate multi-layer wiring is carried out through 3D wiring design software. The signal integrity and power integrity of the wiring are verified by simulation software to achieve stable signal interaction and power distribution between multiple chips. After the chip interconnection is completed, the package substrate is cleaned three times to remove solder residue and other contaminants. By establishing a fluid dynamics simulation model of the package, the position and number of molding compound injection points are set according to the package structure, the flow state of the molding compound under different injection speeds and pressures is simulated, and the flow front, pressure and temperature changes are analyzed. After multiple sets of process parameter simulations and comparisons, the optimal molding process parameters are determined, and the molding is completed to form a protective shell. Finally, the package and system-level motherboard are preheated by infrared heating. The solder ball array is placed on the corresponding pad with the help of high-precision placement equipment. The package and motherboard are placed in a reflow oven and sequentially processed through preheating, temperature averaging, reflow, cooling and other temperature zones. Packaging technology realizes the electrical connection between the package body and the motherboard, and conducts comprehensive testing on the packaged body, covering performance testing, fault diagnosis, and stability, durability and wide temperature adaptability testing under simulated extreme environments (such as high and low temperatures, humidity, and vibration) to ensure that the product meets performance requirements.It should be noted that the three-step cleaning process in the present invention is designed with differentiated features based on the contamination characteristics of different stages: the first cleaning is for the bare die before dicing, using plasma + ultrasonic cleaning to remove the oxide layer, particles, and organic matter, and detect defects; the second cleaning is for the chip units after dicing, using ultrasonic / megasonic waves to remove cutting debris and thermal damage layers; the third cleaning is for the substrate after interconnection, using chemical cleaning to remove flux and other residues, improve molding bonding, and control contamination in stages to ensure packaging quality.

[0022] Please refer to Figure 2 , Figure 2 This is a flowchart of a method for packaging and processing a memory chip in some embodiments of the present application, for constructing a three-dimensional virtual model of the package. According to an embodiment of the present invention, the three-dimensional virtual model of the package is constructed based on the design specifications and target performance indicators of the chip die, specifically: S201, using 3D modeling software, combining the chip die's dimensions, pinout, functional partitions, and pre-set package size limits to create an initial 3D model of the package; S202 : Preset a preliminary layout of electrical connection structures, heat dissipation channels, and stress buffering areas in the initial three-dimensional model.

[0023] First, using professional 3D modeling software (such as AutoCAD and SolidWorks), an initial 3D model of the package is created, combining the die's dimensions (e.g., length, width, height), pinout (e.g., number of pins, arrangement, and spacing), functional partitions (e.g., storage area, control area, I / O area), and pre-set package size constraints (e.g., maximum dimensions and thickness). This model must accurately reflect the spatial relationship between the die and the package structure. Within this initial 3D model, the preliminary layout of electrical connections (e.g., wire bonding paths, flip-chip bump layout), heat dissipation channels (e.g., heat sink location, thermal via distribution), and stress buffering areas (e.g., filler material area, flexible structure location) is pre-defined, providing a foundational model for subsequent simulation analysis and structural optimization. This 3D virtual model enables digital design and verification of the package structure before physical manufacturing, effectively shortening the R&D cycle and reducing trial-and-error costs.

[0024] Please refer to Figure 3 , Figure 3 The present invention provides a flowchart of a method for packaging and processing a memory chip in some embodiments of the present application, wherein the chip bare die is cleaned and inspected once. According to an embodiment of the present invention, the cleaning and inspection of the chip bare die includes: S301, using plasma-assisted cleaning technology to excite an inert gas using a radio frequency power supply to generate plasma, thereby removing the surface oxide layer of the chip die; S302, cleaning with ultrasonic deionized water to remove surface particle contaminants and organic residues from the chip die; S303 , scanning and imaging the chip die line by line by automatic optical inspection equipment, identifying surface defects through image processing algorithms and comparing them with standard templates, and automatically marking unqualified chips.

[0025] First, plasma-assisted cleaning technology is employed. An RF power source is used to excite inert gases such as argon and nitrogen to generate a plasma. High-energy particles in the plasma physically sputter or chemically react with the die surface, effectively removing oxide layers (such as silicon oxide and metal pad oxide films), improving adhesion during subsequent cutting and interconnection processes. This is followed by ultrasonic deionized water cleaning. The die is immersed in deionized water, where the cavitation effect generated by ultrasonic vibrations removes surface contaminants (such as silicon chips and metal dust) and organic residues (such as photoresist residue and organic matter from the cutting fluid), ensuring submicron surface cleanliness standards. Finally, automated optical inspection (AOI) equipment scans the die line by line and compares the captured image with a standard template using image processing algorithms (such as edge detection and template matching). Surface defects such as cracks, dents, and residual contaminants are automatically identified, and rejected chips are marked to prevent defective products from entering subsequent processes, thereby ensuring packaging yield from the source. This combined process, through a multi-dimensional control process of "chemical cleaning, physical cleaning, and visual inspection," achieves precise control of die surface cleanliness and quality.

[0026] Please refer to Figure 4 , Figure 4 This is a flow chart of a memory chip packaging processing method using a laser stealth cutting process in some embodiments of the present application. According to an embodiment of the present invention, the laser stealth cutting process is specifically as follows: S401, selecting a laser with an appropriate wavelength according to the material properties of the chip die, and adjusting the laser power and cutting speed; S402, relying on a high-precision motion platform to control the movement of the chip die, cooperating with a coaxial visual monitoring system for real-time observation, to complete high-precision cutting of the chip unit.

[0027] First, based on the material properties of the chip die (such as the different optical absorption characteristics of silicon-based chips and compound semiconductor chips), a laser with an appropriate wavelength is selected (e.g., ultraviolet lasers are suitable for organic materials, and infrared lasers are suitable for silicon materials), and the laser power and cutting speed are adjusted to balance cutting efficiency and the heat-affected zone. A high-precision motion platform is then used to control the movement of the chip die, while a coaxial visual monitoring system is used to observe the cutting path in real time. The laser focus position and motion trajectory are dynamically adjusted using an image recognition algorithm to compensate for positional deviations caused by chip warping or clamping errors. Ultimately, high-precision cutting of the chip unit is completed, achieving a debris-free, low-stress cutting effect. This process effectively avoids defects such as edge collapse and cracking associated with traditional mechanical cutting through the coordinated optimization of laser parameters and motion control, making it suitable for cutting ultra-thin chips and high-density packaging.

[0028] According to an embodiment of the present invention, extracting the actual size and position parameters of the independent chip unit, correcting the initial three-dimensional virtual model, and obtaining the corrected three-dimensional virtual model are specifically as follows: Obtain the actual size, cutting accuracy and pin position deviation data of the chip unit through micro-measuring equipment; The data is imported into the three-dimensional modeling software, the chip unit part in the initial model is sized and calibrated, and the matching parameters of the electrical connection structure and the package body are updated synchronously.

[0029] Among them, first, use microscopic measurement equipment such as atomic force microscope (AFM) and laser scanning microscope to perform three-dimensional morphology scanning on the cut independent chip units to obtain actual dimensions (such as chip thickness, edge length accuracy), cutting accuracy (such as cutting line width deviation, verticality deviation) and pin position deviation data (such as pad offset, coplanarity); then import the above measured data into the three-dimensional modeling software, and perform geometric correction on the chip unit part in the initial model through parameter-driven method: adjust the solid model parameters according to size deviation, and calibrate the coordinate system and spatial posture according to position deviation; synchronously update the electrical connection structure parameters (such as wire bonding length tolerance compensation, flip chip bump position remapping) and package matching parameters (such as gap adjustment between heat sink and chip surface, volume correction of molding compound filling area).

[0030] Through this correction process, the geometric accuracy and physical parameters of the three-dimensional virtual model are brought close to those of the real device, reducing simulation analysis errors, providing a basis for subsequent accurate simulation of electrical performance, thermal performance, and stress distribution, and effectively improving the reliability and iteration efficiency of packaging design.

[0031] According to an embodiment of the present invention, the method of integrating multiple types of functional chip units using SiP technology includes: Based on simulation-optimized packaging structure design, layout planning is performed for power management chips, data processing chips, and storage chips to shorten the signal transmission path between chips; Multi-layer wiring of the substrate is performed using 3D wiring design software, and simulation software is used to verify the signal integrity and power integrity of the wiring to achieve stable signal interaction and power distribution among multiple chips.

[0032] First, based on simulation-optimized package structure design, a collaborative analysis method of thermodynamics and electromagnetic fields was used to perform three-dimensional layout planning for the power management chip, data processing chip, and memory chip. Thermal simulation was used to identify hotspots, prioritizing the alignment of high-power chips (such as the CPU) with heat dissipation channels. Based on signal integrity simulation, high-frequency signal transmission chips (such as the DDR controller and memory chip) were placed in adjacent locations to shorten signal transmission paths, while crosstalk was reduced through orthogonal wiring. For the power management chip, independent power planes and decoupling capacitor layouts were planned to reduce power supply noise. Subsequently, three-dimensional wiring design software was used for multi-layer wiring of the substrate. Differential pair routing, impedance matching networks, and via structures (such as blind and buried vias) were designed in the high-density interconnect substrate to achieve three-dimensional interconnection between chips. Simulation software was used to verify the signal and power integrity of the routing. Stable signal interaction and power distribution between multiple chips were ensured by optimizing routing spacing and adding impedance matching networks (such as terminal resistors). This process reduces signal transmission delay and improves power supply noise suppression ratio through a closed-loop process of "simulation-driven layout-3D wiring-multi-physics field verification", meeting the needs of high-speed and high-density applications such as 5G communications and AI computing.

[0033] According to an embodiment of the present invention, the molding process to form the protective housing by optimizing the flow path of the molding material through mold flow simulation technology is specifically as follows: Establish a fluid dynamics simulation model for the package and set the location and number of molding compound injection points based on the package structure; The flow state of the molding compound under different injection speeds and pressures is simulated, and the changes in its flow front, pressure and temperature are analyzed. After simulation and comparison of multiple sets of process parameters, the optimal molding process parameters are determined.

[0034] First, a fluid dynamics simulation model was constructed using specialized software based on a 3D geometric model of the package. The location and number of molding compound injection points (e.g., single-point injection at the edge, multiple-point injection at the center) were determined based on the package's structural characteristics (e.g., chip layout density, substrate topography). Material properties (e.g., epoxy resin viscosity-temperature curve) and process boundary conditions (e.g., mold temperature, initial molding compound temperature) were also defined. The flow of the molding compound at various injection speeds and pressures was then simulated, and CFD algorithms were used to analyze the flow front morphology (e.g., whether turbulence or stagnant flow areas were formed), pressure distribution, and temperature changes. The weld mark location was monitored in high-density chip gaps (by tracking the convergence points of different flow fronts), and injection parameters were optimized to avoid critical electrical connection areas. Multiple orthogonal experimental designs were used to compare fill time, encapsulation efficiency, residual stress, and other indicators under different parameter combinations to ultimately determine the optimal process parameters. This approach significantly reduces the number of mold modifications required by traditional trial-and-error methods, lowers the fill defect rate, and effectively controls package warpage through residual stress optimization, significantly improving molding quality and production efficiency.

[0035] According to an embodiment of the present invention, the use of BGA packaging technology includes: Preheating the package and system-level motherboard by infrared heating; The solder ball array is placed on the corresponding pad with the help of high-precision placement equipment; The package body and the system-level motherboard are placed in a reflow oven and sequentially go through preheating, temperature equalization, reflow, cooling and other temperature zone treatments to achieve welding of the package body and the system-level motherboard.

[0036] First, the package and system-level motherboard are preheated using infrared heating to eliminate moisture, activate the pad surface, and reduce soldering thermal stress. High-precision placement equipment then places the solder ball array on the pads on the bottom of the package, with a vision-based alignment system ensuring precise alignment between the balls and pads. Finally, the package and motherboard assembly is placed in a reflow oven, undergoing four temperature zones: preheating, equalizing, reflow, and cooling. The preheating zone removes flux solvents and activates the flux; the equalizing zone evens out the component temperature and evaporates impurities; the reflow zone melts the solder balls to form a liquid alloy, which self-aligns with the pad through surface tension to form an intermetallic compound layer; and the cooling zone solidifies the solder joint structure. The entire soldering process is performed under an inert gas atmosphere, with real-time monitoring of the furnace temperature profile to ensure soldering quality and achieve stable electrical interconnection between the package and motherboard, meeting the requirements of high-reliability applications.

[0037] According to an embodiment of the present invention, the further embodiment includes: Embed a sensor array in the packaging process. The sensor array includes temperature sensors and stress sensors for real-time monitoring of chip temperature and solder joint stress inside the package. The sensor array is connected to the edge computing system via a wireless module. The edge computing system has a built-in AI algorithm for analyzing sensor data and predicting potential failure risks. The edge computing system is in communication with the packaging equipment and is used to reversely control the packaging equipment to adjust process parameters according to the analysis results, so as to achieve dynamic adaptive adjustment of the process parameters; The edge computing system is also used to upload the optimization data to the cloud to establish a packaging process database.

[0038] Among them, the present invention innovatively introduces intelligent monitoring and adaptive control systems based on the traditional memory chip packaging process, and realizes dynamic optimization of the entire process through sensor arrays, edge computing and cloud collaboration. Micro temperature sensors (such as thin-film thermocouples) and stress sensors (such as piezoresistive strain gauges) are embedded inside or on the surface of the packaging substrate. These sensors are deployed in the chip's heat source area (such as the CPU core) and at the edges of solder joints where stress concentration is likely to occur, respectively, to collect temperature fluctuation data and microstrain signals in real time. The sensor array transmits the data to the edge computing system via a low-power Bluetooth module. The system conducts in-depth analysis of multi-dimensional data based on a neural network algorithm, establishes a temperature-stress-failure probability prediction model, and identifies potential risk points (such as the trend of solder joint fatigue crack initiation) in advance. The edge computing system communicates with packaging equipment (such as reflow ovens and molding presses) via industrial Ethernet. When parameter anomalies are detected, the process parameters are automatically adjusted to form a closed-loop control. At the same time, the edge computing system regularly encrypts and uploads the optimized data to the cloud database, combines historical production data to build a process knowledge base, and continuously optimizes the prediction model through a transfer learning algorithm, realizing process iteration from "experience-driven" to "data-driven", effectively solving the quality fluctuation problem caused by static parameter solidification in the traditional packaging process.

[0039] According to an embodiment of the present invention, the further embodiment includes: A microfluidic channel network is provided inside the packaging substrate, and microcapsules containing a repair agent are filled in the microfluidic channel network; A crack-sensitive material is provided at a key position of the package body. When microcracks are generated in the package body, the crack-sensitive material triggers the microcapsule to rupture and releases a repair agent to fill the microcracks. The repair agent includes liquid metal alloy or polymer adhesive; Optimizing the layout of the microfluidic channel network through mold flow simulation; The repair agent and the packaging material form a chemical bond through molecular self-assembly technology.

[0040] Among them, the present invention innovatively integrates a self-repair function on the basis of the traditional memory chip packaging structure, realizes autonomous damage repair of the package body through microfluidic networks and intelligent response materials, and significantly improves long-term reliability. Specifically, a microfluidic channel network is formed inside the packaging substrate through micromachining technology, and its layout is optimized through mold flow simulation to ensure coverage of high-risk areas such as solder joints and chip edges; the channel is filled with microcapsules containing repair agents, and the repair agents can be selected from low-melting-point liquid metal alloys or polymer adhesives according to the application scenario. Special materials that are sensitive to cracks are deployed in key areas such as the interface between the chip and the substrate and around the solder balls. When microcracks occur in the package body, the material will trigger the rupture of the microcapsules and release the repair agent. The repair agent quickly fills the cracks under the action of physical driving force, and forms a chemical bond with the packaging material through molecular self-assembly technology to achieve a repair effect. This self-repairing structure effectively inhibits the expansion of cracks inside the package body, reduces the change in thermal resistance, and significantly improves the service life and reliability of the memory chip in extreme environments.

[0041] The present invention also discloses a memory chip packaging and processing system, comprising a memory and a processor. The memory includes a memory chip packaging and processing method program. When the memory chip packaging and processing method program is executed by the processor, the following steps are implemented: An initial three-dimensional virtual model of the package is constructed based on the design specifications and target performance indicators of the chip die, and the chip die is cleaned and inspected once, then cut using a laser stealth cutting process and cleaned twice to obtain independent chip units; Extracting actual size and position parameters of the independent chip unit, revising the initial three-dimensional virtual model, and obtaining a revised three-dimensional virtual model; Using simulation technology to analyze the electrical performance, thermal performance and stress distribution of the modified three-dimensional virtual model to optimize the packaging structure design; Adopt SiP technology to integrate multiple types of functional chip units, and realize signal interaction and power distribution through three-dimensional wiring of substrate based on optimized design; The interconnected package substrate is cleaned three times, and the mold flow simulation technology is used to optimize the flow path of the molding compound to complete the molding process to form a protective shell; Using BGA packaging technology, the package is connected to the system-level motherboard through a solder ball array to achieve electrical connection between the package and the motherboard; The packaged body is fully tested, including performance testing, fault diagnosis, and testing its stability, durability and wide temperature adaptability by simulating extreme environments.

[0042] The present invention systematically improves packaging performance and reliability with simulation-driven and multi-process collaboration as its core. First, based on the design specifications of the die, such as the die dimensions, pin distribution, functional partitioning, and the preset package size restrictions, a 3D modeling software is used to construct an initial 3D virtual model of the package body. The preliminary layout of the electrical connection structure, heat dissipation channel, and stress buffer area is pre-set in the model. Subsequently, the die is sequentially cleaned with plasma-assisted cleaning technology to remove the surface oxide layer, and ultrasonic deionized water cleaning is used to remove particulate contaminants and organic residues. Surface defects are then identified by line-by-line scanning and imaging using automated optical inspection equipment. Unqualified chips are then marked, completing a single cleaning and inspection. Next, a laser with an appropriate wavelength is selected based on the material properties of the die, and the laser power and cutting speed are adjusted. The die movement is controlled by a high-precision motion platform, and a coaxial visual monitoring system is used for real-time observation. After the laser stealth cutting is completed, a secondary cleaning is performed to obtain an independent chip unit. After obtaining the independent chip unit, its actual size, cutting accuracy and pin position deviation data are obtained through micro-measurement equipment. The data is imported into the 3D modeling software, and the chip unit part in the initial model is corrected in size and calibrated in position. The matching parameters of the electrical connection structure and the package body are simultaneously updated to obtain a corrected 3D virtual model. Then, simulation technology is used to analyze the electrical performance (such as signal integrity), thermal performance (such as heat dissipation path) and stress distribution (such as solder joint stress concentration points) of the corrected 3D virtual model to optimize the package structure design. On the basis of structural design optimization, the layout planning of power management chip, data processing chip and storage chip is carried out based on the simulation optimization results, the signal transmission path between chips is shortened, and SiP technology is used to integrate multiple types of functional chip units. The substrate multi-layer wiring is carried out through 3D wiring design software. The signal integrity and power integrity of the wiring are verified by simulation software to achieve stable signal interaction and power distribution between multiple chips. After the chip interconnection is completed, the package substrate is cleaned three times to remove solder residue and other contaminants. By establishing a fluid dynamics simulation model of the package, the position and number of molding compound injection points are set according to the package structure, the flow state of the molding compound under different injection speeds and pressures is simulated, and the flow front, pressure and temperature changes are analyzed. After multiple sets of process parameter simulations and comparisons, the optimal molding process parameters are determined, and the molding is completed to form a protective shell. Finally, the package and system-level motherboard are preheated by infrared heating. The solder ball array is placed on the corresponding pad with the help of high-precision placement equipment. The package and motherboard are placed in a reflow oven and sequentially processed through preheating, temperature averaging, reflow, cooling and other temperature zones. Packaging technology realizes the electrical connection between the package body and the motherboard, and conducts comprehensive testing on the packaged body, covering performance testing, fault diagnosis, and stability, durability and wide temperature adaptability testing under simulated extreme environments (such as high and low temperatures, humidity, and vibration) to ensure that the product meets performance requirements.It should be noted that the three-step cleaning process in the present invention is designed with differentiated features based on the contamination characteristics of different stages: the first cleaning is for the bare die before dicing, using plasma + ultrasonic cleaning to remove the oxide layer, particles, and organic matter, and detect defects; the second cleaning is for the chip units after dicing, using ultrasonic / megasonic waves to remove cutting debris and thermal damage layers; the third cleaning is for the substrate after interconnection, using chemical cleaning to remove flux and other residues, improve molding bonding, and control contamination in stages to ensure packaging quality.

[0043] According to an embodiment of the present invention, the three-dimensional virtual model of the package is constructed based on the design specifications and target performance indicators of the chip die, specifically: Use 3D modeling software to build an initial 3D model of the package, combining the die dimensions, pinout, functional partitions, and pre-set package size limits. In the initial three-dimensional model, a preliminary layout of the electrical connection structure, heat dissipation channels and stress buffering areas is pre-set.

[0044] First, using professional 3D modeling software (such as AutoCAD and SolidWorks), an initial 3D model of the package is created, combining the die's dimensions (e.g., length, width, height), pinout (e.g., number of pins, arrangement, and spacing), functional partitions (e.g., storage area, control area, I / O area), and pre-set package size constraints (e.g., maximum dimensions and thickness). This model must accurately reflect the spatial relationship between the die and the package structure. Within this initial 3D model, the preliminary layout of electrical connections (e.g., wire bonding paths, flip-chip bump layout), heat dissipation channels (e.g., heat sink location, thermal via distribution), and stress buffering areas (e.g., filler material area, flexible structure location) is pre-defined, providing a foundational model for subsequent simulation analysis and structural optimization. This 3D virtual model enables digital design and verification of the package structure before physical manufacturing, effectively shortening the R&D cycle and reducing trial-and-error costs.

[0045] According to an embodiment of the present invention, the cleaning and testing of the chip die includes: Plasma-assisted cleaning technology is used to excite an inert gas using a radio frequency power supply to generate plasma to remove the surface oxide layer of the chip die; Cleaning the chip die with ultrasonic deionized water to remove surface particle contaminants and organic residues; The chip die is scanned and imaged line by line by automatic optical inspection equipment, and surface defects are identified by image processing algorithms and compared with standard templates, and unqualified chips are automatically marked.

[0046] First, plasma-assisted cleaning technology is employed. An RF power source is used to excite inert gases such as argon and nitrogen to generate a plasma. High-energy particles in the plasma physically sputter or chemically react with the die surface, effectively removing oxide layers (such as silicon oxide and metal pad oxide films), improving adhesion during subsequent cutting and interconnection processes. This is followed by ultrasonic deionized water cleaning. The die is immersed in deionized water, where the cavitation effect generated by ultrasonic vibrations removes surface contaminants (such as silicon chips and metal dust) and organic residues (such as photoresist residue and organic matter from the cutting fluid), ensuring submicron surface cleanliness standards. Finally, automated optical inspection (AOI) equipment scans the die line by line and compares the captured image with a standard template using image processing algorithms (such as edge detection and template matching). Surface defects such as cracks, dents, and residual contaminants are automatically identified, and rejected chips are marked to prevent defective products from entering subsequent processes, thereby ensuring packaging yield from the source. This combined process, through a multi-dimensional control process of "chemical cleaning, physical cleaning, and visual inspection," achieves precise control of die surface cleanliness and quality.

[0047] According to an embodiment of the present invention, the cutting process using the laser invisible cutting process is specifically as follows: According to the material properties of the chip die, a laser with an appropriate wavelength is selected and the laser power and cutting speed are adjusted; The chip die is moved by a high-precision motion platform and observed in real time by a coaxial visual monitoring system to complete high-precision cutting of the chip unit.

[0048] First, based on the material properties of the chip die (such as the different optical absorption characteristics of silicon-based chips and compound semiconductor chips), a laser with an appropriate wavelength is selected (e.g., ultraviolet lasers are suitable for organic materials, and infrared lasers are suitable for silicon materials), and the laser power and cutting speed are adjusted to balance cutting efficiency and the heat-affected zone. A high-precision motion platform is then used to control the movement of the chip die, while a coaxial visual monitoring system is used to observe the cutting path in real time. The laser focus position and motion trajectory are dynamically adjusted using an image recognition algorithm to compensate for positional deviations caused by chip warping or clamping errors. Ultimately, high-precision cutting of the chip unit is completed, achieving a debris-free, low-stress cutting effect. This process effectively avoids defects such as edge collapse and cracking associated with traditional mechanical cutting through the coordinated optimization of laser parameters and motion control, making it suitable for cutting ultra-thin chips and high-density packaging.

[0049] According to an embodiment of the present invention, extracting the actual size and position parameters of the independent chip unit, correcting the initial three-dimensional virtual model, and obtaining the corrected three-dimensional virtual model are specifically as follows: Obtain the actual size, cutting accuracy and pin position deviation data of the chip unit through micro-measuring equipment; The data is imported into three-dimensional modeling software, and the size of the chip unit part in the initial model is corrected and the position is calibrated, and the matching parameters of the electrical connection structure and the package are updated synchronously.

[0050] Wherein, first, the three-dimensional topography of the cut independent chip unit is scanned by using atomic force microscope (AFM), laser scanning microscope and other microscopic measuring equipment, and the actual size (such as chip thickness, edge length accuracy), cutting accuracy (such as cutting path width deviation, perpendicularity deviation) and pin position deviation data (such as pad offset, coplanarity) are obtained; then the above measured data is imported into three-dimensional modeling software, and the chip unit part in the initial model is geometrically corrected by parameterized driving mode: for size deviation, adjust the entity model parameters, and for position deviation, coordinate system and space pose calibration; update the electrical connection structure parameters (such as wire bonding length tolerance compensation, flip chip bump position remapping) and package matching parameters (such as fin and chip surface gap adjustment, molding compound filling area volume correction) synchronously.

[0051] Through the correction process, the geometric accuracy and physical parameters of the three-dimensional virtual model are close to the real device, the simulation analysis error is reduced, the accurate simulation of the subsequent electrical performance, thermal performance and stress distribution is provided, and the reliability and iteration efficiency of the package design are effectively improved.

[0052] According to the embodiment of the application, the SiP technology is used to integrate multiple types of functional chip units, including: Based on the simulation-optimized package structure design, the power management chip, data processing chip and storage chip are laid out and planned, and the signal transmission path between chips is shortened. Through three-dimensional wiring design software, multi-layer wiring of the substrate is performed, and the signal integrity and power integrity of the wiring are verified by using simulation software, so that stable signal interaction and power distribution between multiple chips are realized.

[0053] First, based on simulation-optimized package structure design, a collaborative analysis method of thermodynamics and electromagnetic fields was used to perform three-dimensional layout planning for the power management chip, data processing chip, and memory chip. Thermal simulation was used to identify hotspots, prioritizing the alignment of high-power chips (such as the CPU) with heat dissipation channels. Based on signal integrity simulation, high-frequency signal transmission chips (such as the DDR controller and memory chip) were placed in adjacent locations to shorten signal transmission paths, while crosstalk was reduced through orthogonal wiring. For the power management chip, independent power planes and decoupling capacitor layouts were planned to reduce power supply noise. Subsequently, three-dimensional wiring design software was used for multi-layer wiring of the substrate. Differential pair routing, impedance matching networks, and via structures (such as blind and buried vias) were designed in the high-density interconnect substrate to achieve three-dimensional interconnection between chips. Simulation software was used to verify the signal and power integrity of the routing. Stable signal interaction and power distribution between multiple chips were ensured by optimizing routing spacing and adding impedance matching networks (such as terminal resistors). This process reduces signal transmission delay and improves power supply noise suppression ratio through a closed-loop process of "simulation-driven layout-3D wiring-multi-physics field verification", meeting the needs of high-speed and high-density applications such as 5G communications and AI computing.

[0054] According to an embodiment of the present invention, the molding process to form the protective housing by optimizing the flow path of the molding material through mold flow simulation technology is specifically as follows: Establish a fluid dynamics simulation model for the package and set the location and number of molding compound injection points based on the package structure; The flow state of the molding compound under different injection speeds and pressures is simulated, and the changes in its flow front, pressure and temperature are analyzed. After simulation and comparison of multiple sets of process parameters, the optimal molding process parameters are determined.

[0055] First, a fluid dynamics simulation model was constructed using specialized software based on a 3D geometric model of the package. The location and number of molding compound injection points (e.g., single-point injection at the edge, multiple-point injection at the center) were determined based on the package's structural characteristics (e.g., chip layout density, substrate topography). Material properties (e.g., epoxy resin viscosity-temperature curve) and process boundary conditions (e.g., mold temperature, initial molding compound temperature) were also defined. The flow of the molding compound at various injection speeds and pressures was then simulated, and CFD algorithms were used to analyze the flow front morphology (e.g., whether turbulence or stagnant flow areas were formed), pressure distribution, and temperature changes. The weld mark location was monitored in high-density chip gaps (by tracking the convergence points of different flow fronts), and injection parameters were optimized to avoid critical electrical connection areas. Multiple orthogonal experimental designs were used to compare fill time, encapsulation efficiency, residual stress, and other indicators under different parameter combinations to ultimately determine the optimal process parameters. This approach significantly reduces the number of mold modifications required by traditional trial-and-error methods, lowers the fill defect rate, and effectively controls package warpage through residual stress optimization, significantly improving molding quality and production efficiency.

[0056] According to an embodiment of the present invention, the use of BGA packaging technology includes: Preheating the package and system-level motherboard by infrared heating; The solder ball array is placed on the corresponding pad with the help of high-precision placement equipment; The package body and the system-level motherboard are placed in a reflow oven and sequentially go through preheating, temperature equalization, reflow, cooling and other temperature zone treatments to achieve welding of the package body and the system-level motherboard.

[0057] First, the package and system-level motherboard are preheated using infrared heating to eliminate moisture, activate the pad surface, and reduce soldering thermal stress. High-precision placement equipment then places the solder ball array on the pads on the bottom of the package, with a vision-based alignment system ensuring precise alignment between the balls and pads. Finally, the package and motherboard assembly is placed in a reflow oven, undergoing four temperature zones: preheating, equalizing, reflow, and cooling. The preheating zone removes flux solvents and activates the flux; the equalizing zone evens out the component temperature and evaporates impurities; the reflow zone melts the solder balls to form a liquid alloy, which self-aligns with the pad through surface tension to form an intermetallic compound layer; and the cooling zone solidifies the solder joint structure. The entire soldering process is performed under an inert gas atmosphere, with real-time monitoring of the furnace temperature profile to ensure soldering quality and achieve stable electrical interconnection between the package and motherboard, meeting the requirements of high-reliability applications.

[0058] According to an embodiment of the present invention, the further embodiment includes: Embed a sensor array in the packaging process. The sensor array includes temperature sensors and stress sensors for real-time monitoring of chip temperature and solder joint stress inside the package. The sensor array is in communication connection with an edge computing system through a wireless module, the edge computing system is built-in AI algorithm, for analyzing sensor data and predicting potential failure risk; The edge computing system is in communication connection with a packaging device, for reversely controlling the packaging device to adjust process parameters according to the analysis result, so as to realize dynamic self-adaptive adjustment of process parameters; The edge computing system is also used for uploading optimization data to the cloud to establish a packaging process database.

[0059] In the application, an intelligent monitoring and self-adaptive control system is innovatively introduced on the basis of a traditional storage chip packaging process, and full-process dynamic optimization is realized through cooperation of a sensor array, edge computing and the cloud. Micro temperature sensors (such as thin-film thermocouples) and stress sensors (such as piezoresistive strain gauges) are embedded in the interior or surface of a packaging substrate, and are respectively arranged at a chip heat source area (such as a CPU core) and a solder joint edge prone to stress concentration, so as to collect temperature fluctuation data and micro-strain signals in real time. The sensor array transmits data to an edge computing system through a low-power Bluetooth module, the system performs deep analysis on multidimensional data based on a neural network algorithm, establishes a temperature-stress-failure probability prediction model, and identifies potential risk points (such as a solder joint fatigue crack initiation trend) in advance. The edge computing system is in communication connection with a packaging device (such as a reflow soldering furnace or a molding press) through an industrial Ethernet, and automatically adjusts process parameters when detecting parameter abnormalities, so as to form a closed-loop control. Meanwhile, the edge computing system regularly uploads optimization data to a cloud database after encryption, constructs a process knowledge base in combination with historical production data, continuously optimizes the prediction model through a transfer learning algorithm, realizes process iteration from “experience-driven” to “data-driven”, and effectively solves the quality fluctuation problem caused by static solidification of parameters in a traditional packaging process.

[0060] According to the embodiment of the application, further comprising: A microfluidic channel network is arranged in the interior of the packaging substrate, and the microfluidic channel network is filled with microcapsules containing a repairing agent; A crack-sensitive material is arranged at a key position of the packaging body, and when the packaging body produces a microcrack, the crack-sensitive material triggers the microcapsules to break, and the repairing agent is released to fill the microcrack; The repairing agent includes a liquid metal alloy or a polymer adhesive; The layout of the microfluidic channel network is optimized through mold flow simulation; The repairing agent and the packaging material form a chemical bond through a molecular self-assembly technology.

[0061] Among them, the present invention innovatively integrates a self-repair function on the basis of the traditional memory chip packaging structure, realizes autonomous damage repair of the package body through microfluidic networks and intelligent response materials, and significantly improves long-term reliability. Specifically, a microfluidic channel network is formed inside the packaging substrate through micromachining technology, and its layout is optimized through mold flow simulation to ensure coverage of high-risk areas such as solder joints and chip edges; the channel is filled with microcapsules containing repair agents, and the repair agents can be selected from low-melting-point liquid metal alloys or polymer adhesives according to the application scenario. Special materials that are sensitive to cracks are deployed in key areas such as the interface between the chip and the substrate and around the solder balls. When microcracks occur in the package body, the material will trigger the rupture of the microcapsules and release the repair agent. The repair agent quickly fills the cracks under the action of physical driving force, and forms a chemical bond with the packaging material through molecular self-assembly technology to achieve a repair effect. This self-repairing structure effectively inhibits the expansion of cracks inside the package body, reduces the change in thermal resistance, and significantly improves the service life and reliability of the memory chip in extreme environments.

[0062] The third aspect of the present invention provides a computer-readable storage medium, which includes a program for a packaging and processing method for a memory chip. When the program for the packaging and processing method for a memory chip is executed by a processor, the steps of the packaging and processing method for a memory chip as described in any one of the above items are implemented.

[0063] The present invention discloses a packaging and processing method, system and medium for a memory chip, the core of which is to achieve high-performance packaging through simulation-driven and multi-process collaboration. The specific steps include: first, based on the design specifications such as the chip bare die's external dimensions, pin distribution and package size restrictions, use 3D modeling software to build an initial 3D virtual model, and preset the preliminary layout of the electrical connection structure, heat dissipation channel and stress buffer area; the chip bare die is sequentially subjected to plasma-assisted cleaning to remove the oxide layer, ultrasonic deionized water cleaning to remove contaminants and automatic optical detection to mark defects. After completing one cleaning and inspection, an adapted laser wavelength is selected and the power and speed are adjusted according to the material properties. Laser invisible cutting and secondary cleaning are achieved through a high-precision motion platform and coaxial visual monitoring to obtain an independent chip unit. Then, a microscopic measurement device is used to obtain the actual size, cutting accuracy and pin position deviation data of the chip unit, and the initial model is imported into the 3D modeling software to correct it, forming a corrected 3D virtual model, and simulation technology is used to analyze its electrical properties, thermal properties and stress distribution to optimize the packaging structure design. Based on the optimized design, SiP technology is used to plan the layout of the power management chip, data processing chip and storage chip, shorten the signal transmission path, complete the multi-layer wiring of the substrate through 3D wiring design software, and use simulation software to verify the signal integrity and power integrity to achieve stable signal interaction and power distribution between multiple chips; the interconnected package substrate is cleaned three times to remove solder residue, and a fluid dynamics simulation model is established to simulate the flow state of the molding compound under different injection speeds and pressures. The molding compound flow path and process parameters are optimized, and the molding is completed to form a protective shell; using BGA packaging technology, after preheating the package body and the motherboard, the solder ball array is placed by high-precision placement equipment, and the electrical connection is achieved through multi-temperature zone treatment in the reflow oven; finally, the package body is subjected to performance testing, fault diagnosis and stability testing under simulated extreme environments. Furthermore, this method can embed temperature and stress sensor arrays into the packaging process, communicating with edge computing systems via wireless modules. AI algorithms analyze the data and reverse-control the packaging equipment to adjust process parameters. The optimized data is then uploaded to the cloud to establish a process database. Alternatively, a microfluidic channel network can be incorporated into the packaging substrate, filled with microcapsules containing a repair agent. Crack-sensitive materials trigger the release of the repair agent, filling microcracks. The repair agent and the packaging material form chemical bonds through molecular self-assembly, improving package reliability. This method, through a closed-loop "design-simulation-manufacturing-testing" system and innovative technologies such as intelligent monitoring and self-repair, effectively addresses signal interference, thermal management, and process reliability issues in multi-chip integration, improving packaging density, yield, and device environmental adaptability. It is suitable for the industrialized packaging production of advanced memory chips.

[0064] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0065] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0066] In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0067] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories, random access memories, magnetic disks or optical disks, and other media that can store program codes.

[0068] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as standalone products, they can also be stored on a readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present invention, or the portion that contributes to the prior art, can be embodied in the form of a software product. This software product, stored on a storage medium, includes instructions for enabling a computer device (such as a personal computer, server, or network device) to execute all or part of the methods described in the various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as removable storage devices, ROM, RAM, magnetic disks, or optical disks.

Claims

1. A packaging and processing method for a memory chip, characterized in that: The following steps are involved: An initial three-dimensional virtual model of the package is constructed based on the design specifications and target performance indicators of the chip die, and the chip die is cleaned and inspected once, then cut using a laser stealth cutting process and cleaned twice to obtain independent chip units; Extracting actual size and position parameters of the independent chip unit, correcting the initial three-dimensional virtual model, and obtaining a corrected three-dimensional virtual model; Using simulation technology to analyze the electrical performance, thermal performance and stress distribution of the modified three-dimensional virtual model to optimize the packaging structure design; Adopt SiP technology to integrate multiple types of functional chip units, and realize signal interaction and power distribution through three-dimensional wiring of substrate based on optimized design; The interconnected package substrate is cleaned three times, and the mold flow simulation technology is used to optimize the flow path of the molding compound to complete the molding process to form a protective shell; Using BGA packaging technology, the package is connected to the system-level motherboard through a solder ball array to achieve electrical connection between the package and the motherboard; The packaged body is fully tested, including performance testing, fault diagnosis, and testing its stability, durability and wide temperature adaptability by simulating extreme environments.

2. The packaging and processing method of a memory chip according to claim 1, characterized in that: The three-dimensional virtual model of the package is constructed based on the design specifications and target performance indicators of the chip die, specifically: Use 3D modeling software to build an initial 3D model of the package based on the die dimensions, pinout, functional partitions, and pre-set package size limits. In the initial three-dimensional model, a preliminary layout of the electrical connection structure, heat dissipation channels and stress buffering areas is pre-set.

3. The packaging and processing method of a memory chip according to claim 1, characterized in that: The cleaning and testing of the chip bare die includes: Plasma-assisted cleaning technology is used to generate plasma by stimulating an inert gas with a radio frequency power supply to remove the surface oxide layer of the chip die; Cleaning the chip die with ultrasonic deionized water to remove surface particle contaminants and organic residues; The chip die is scanned and imaged line by line by automatic optical inspection equipment, and surface defects are identified by image processing algorithms and compared with standard templates, and unqualified chips are automatically marked.

4. The packaging and processing method of a memory chip according to claim 1, wherein: The laser invisible cutting process is used for cutting, specifically: According to the material properties of the chip die, a laser with an appropriate wavelength is selected and the laser power and cutting speed are adjusted; The chip die is moved by a high-precision motion platform and observed in real time by a coaxial visual monitoring system to complete high-precision cutting of the chip unit.

5. The memory chip packaging and processing method according to claim 1, wherein: The extracting of the actual size and position parameters of the independent chip unit, and correcting the initial three-dimensional virtual model to obtain the corrected three-dimensional virtual model is specifically as follows: Obtain the actual size, cutting accuracy and pin position deviation data of the chip unit through micro-measuring equipment; The data is imported into the three-dimensional modeling software, the chip unit part in the initial model is sized and calibrated, and the matching parameters of the electrical connection structure and the package body are updated synchronously.

6. The memory chip packaging and processing method according to claim 1, characterized in that: The SiP technology is used to integrate multiple types of functional chip units, including: Based on simulation-optimized packaging structure design, layout planning is performed for power management chips, data processing chips, and storage chips to shorten the signal transmission path between chips; Multi-layer wiring of the substrate is performed using 3D wiring design software, and simulation software is used to verify the signal integrity and power integrity of the wiring to achieve stable signal interaction and power distribution among multiple chips.

7. The memory chip packaging and processing method according to claim 1, characterized in that: The method of optimizing the flow path of the molding material by using mold flow simulation technology to complete the molding process to form the protective housing is specifically as follows: Establish a fluid dynamics simulation model for the package and set the location and number of molding compound injection points based on the package structure; The flow state of the molding compound under different injection speeds and pressures is simulated, and the changes in its flow front, pressure and temperature are analyzed. After simulation and comparison of multiple sets of process parameters, the optimal molding process parameters are determined.

8. The memory chip packaging and processing method according to claim 1, wherein: The BGA packaging technology includes: Preheating the package and system-level motherboard by infrared heating; The solder ball array is placed on the corresponding pad with the help of high-precision placement equipment; The package body and the system-level motherboard are placed in a reflow oven and sequentially go through preheating, temperature equalization, reflow, cooling and other temperature zone treatments to achieve welding of the package body and the system-level motherboard.

9. A memory chip packaging and processing system, characterized in that: The invention comprises a memory and a processor, wherein the memory comprises a memory chip packaging and processing method program, and when the memory chip packaging and processing method program is executed by the processor, the following steps are implemented: An initial three-dimensional virtual model of the package is constructed based on the design specifications and target performance indicators of the chip die, and the chip die is cleaned and inspected once, then cut using a laser stealth cutting process and cleaned twice to obtain independent chip units; Extracting actual size and position parameters of the independent chip unit, correcting the initial three-dimensional virtual model, and obtaining a corrected three-dimensional virtual model; Using simulation technology to analyze the electrical performance, thermal performance and stress distribution of the modified three-dimensional virtual model to optimize the packaging structure design; Adopt SiP technology to integrate multiple types of functional chip units, and realize signal interaction and power distribution through three-dimensional wiring of substrate based on optimized design; The interconnected package substrate is cleaned three times, and the mold flow simulation technology is used to optimize the flow path of the molding compound to complete the molding process to form a protective shell; Using BGA packaging technology, the package is connected to the system-level motherboard through a solder ball array to achieve electrical connection between the package and the motherboard; The packaged body is fully tested, including performance testing, fault diagnosis, and testing its stability, durability and wide temperature adaptability by simulating extreme environments.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a packaging and processing method program for a memory chip. When the packaging and processing method program for a memory chip is executed by a processor, the steps of the packaging and processing method for a memory chip as described in any one of claims 1 to 8 are implemented.

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