Memristor memory chip aging prediction method based on artificial intelligence and memory chip aging calculation device based on artificial intelligence

Abstract

The invention provides a memristor memory chip aging prediction method and a computing device based on artificial intelligence, and belongs to the technical field of integrated circuits, the method comprises the steps of obtaining multi-dimensional device operation data by monitoring a device erasing process when a memristor memory chip executes a reasoning task in a working process, and performing aging prediction on the memristor memory chip; and constructing a data set containing the aging characteristics of the device, and predicting and classifying the aging state of the device based on an artificial intelligence algorithm. The computing device comprises a plurality of memristor storage / storage macros and a global aging prediction control / processing module, the memristor storage / storage macros can be configured as reasoning computing units for aging prediction, and real-time aging state prediction is carried out on other memristor storage / storage macros for processing actual edge AI tasks. And real-time aging state prediction can be carried out by the global aging prediction control / processing module. Through data-driven aging prediction and a systematic load balancing strategy, the overall service life and reliability of the memristor storage system can be effectively improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to an artificial intelligence-based method and computing device for predicting the aging of memristor-based memory chips. Background Technology

[0002] Memristors, as core devices for realizing in-memory computing architectures, have demonstrated significant advantages in edge computing applications such as traditional machine learning, deep neural networks (DNNs), and spiking neural networks (SNNs) inference due to their low power consumption, high density, and non-volatility. However, memristors are prone to aging under frequent erase and write operations, exhibiting problems such as resistance drift and operating voltage threshold deviation, leading to decreased computing accuracy or even device failure. This has become a key bottleneck restricting the long-term reliable operation of in-memory computing systems.

[0003] Currently, research on memristor aging prediction mainly focuses on the construction and optimization of device failure models at the storage application level. For example, by collecting parameters such as memristor resistance fluctuations and operating voltage changes, machine learning models are used to assess the device's aging state, thereby improving the accuracy and efficiency of model predictions. However, existing methods can only predict whether memristor failure will occur in subsequent operating stages based on the aging characteristics of the memristor within the current operating stage, and their accuracy decreases significantly with the increase in the prediction span. Furthermore, in memristor-based in-memory computing systems for AI inference applications, the aging process of multiple memristor storage / computing macros working collaboratively exhibits significant differences. That is, storage / computing macros undertaking high-frequency data refresh tasks or inference and training tasks age much faster than other low-workload storage / computing macros due to more frequent writes and erases, resulting in the overall system lifespan being limited by a few high-load devices. Existing methods lack real-time monitoring and dynamic load balancing strategies for the aging state in systems with multiple macro arrays working collaboratively, making it difficult to achieve optimal aging management at the system level.

[0004] In summary, firstly, existing memristor aging prediction methods employ limited models and are unsuitable for in-situ prediction within memristor storage / in-memory computing macroarrays. Secondly, these methods only address device failure modeling for single macroarrays, failing to consider aging issues caused by uneven load distribution in multi-macroarray chip system applications. Finally, at the memristor in-memory computing system level, there is a lack of mechanisms to dynamically adjust the workload and load of multiple storage / in-memory computing macroarrays based on aging prediction results, thus hindering the extension of the overall system lifespan through load balancing.

[0005] Therefore, how to ensure that memristor-based AI in-memory computing chips can efficiently perform inference tasks in practical applications while avoiding the impact of high-frequency erase and write operations on chip reliability, especially the problem of uneven aging caused by uneven load in chip systems with multiple macroarrays working together, remains a key issue that urgently needs to be addressed in the field of memristor in-memory computing technology. Summary of the Invention

[0006] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides an artificial intelligence-based method and computing device for predicting the aging of memristor memory chips, thereby solving the technical problem of short system life caused by device degradation due to frequent erasure and writing of memristor memory chips.

[0007] To achieve the above objectives, according to one aspect of the present invention, an artificial intelligence-based method for predicting the aging of memristor-based computing chips is provided, comprising the following steps: The operation parameters of each storage / computing macro record of the memristor in-memory computing chip during the execution of the inference task are obtained. Based on the operation parameters, an original dataset Data_Measure containing device aging characteristics is constructed. The original dataset Data_Measure contains multi-dimensional operation information of each memristor bit cell in each write cycle. The measurement data of the original dataset Data_Measure is normalized and classified and labeled to obtain the multidimensional training dataset Data_Training for training artificial intelligence models; The artificial intelligence algorithm model is trained using the multidimensional training dataset Data_Training to obtain an inference model for predicting the aging state of memristor memory chips. The real-time collected memristor memory chip operation data is input into the inference model, and the aging status classification results of each memristor storage / computing macro are output.

[0008] Preferably, the data structure in the original dataset Data_Measure is C×D×T, where C is the total number of memristor storage / computation macro cells, and T is the number of memristor write cycles included in the measurement data within a measurement phase; the original dataset Data_Measure contains measurement data A in D dimensions. n Where n is the nth measurement stage, the measurement data includes the operating voltage of bit cell forming, setting and resetting operations, the resistance value after the operation and the number of write verifications, and other operating conditions and results.

[0009] Preferably, the method for constructing the original dataset Data_Measure includes the following steps: S11, Perform initial shaping operation on the bit unit in the storage / computation macro, and record the operation conditions and operation results of the shaping operation; S12, perform a bit setting operation on the formed storage / computation macro bit unit, and record the operation conditions and operation results of the bit setting operation; S13, perform a reset operation on the formed storage / computation macro-bit unit, and record the operation conditions and operation results of the reset operation; S14, the bit cells in the storage / computation macro cyclically execute the operations of S12 to S13, and execute a total of T write loop cycles, which are recorded as one measurement stage; the dataset Data_Measure contains a total of N measurement stages.

[0010] Preferably, the multidimensional training dataset Data_Training contains multidimensional input data B. n Multi-dimensional input data B n It is obtained by normalizing the original dataset Data_Measure.

[0011] Preferably, the classification labeling includes the following steps: Based on the operating conditions and results of each bit cell c in the nth measurement stage and subsequent measurement stages, a risk metric function is used to label the aging state of the input data of the bit cell in the nth measurement stage, so as to realize the construction of the multidimensional training dataset Data_Training and the training of subsequent artificial intelligence algorithm models.

[0012] Preferably, the formula for the risk measurement function is: ,in As a comprehensive risk measurement function, it can reflect the operational failure tendency and physical drift risk of the unit in the current operation stage; This is an indicator of the frequency of operation failures. These are indicators of the volatility and mean characteristics of operational behavior, as well as the degree of deviation from the mean. and This is the adjustment coefficient.

[0013] Preferably, the operational behavior characteristics of the bit unit are statistically analyzed during the nth measurement stage, and multiple measurement stages after the current measurement stage are used as future prediction windows. The evolution trend and operation failure frequency of the operational behavior characteristics of the bit unit within the future prediction window are statistically analyzed to form a comprehensive degradation feature sequence. Based on the feature sequence, the failure risk measurement function value corresponding to the nth measurement stage is calculated to measure the tendency of the bit unit to undergo permanent failure or near failure within the prediction window, and is used as the failure risk label value corresponding to the nth measurement stage.

[0014] According to another aspect of the present invention, a computing device for predicting the aging of memristor memory computing chips based on artificial intelligence is provided, including a memristor memory / computing macro array of multiple memristor memory / computing macros and inter-chip routing modules, a global aging prediction control / processing module, and an on-chip memory. The memristor storage / in-memory computation macros are all independent storage or in-memory computation functional units; the memristor storage macros are used to store regular data, or to store weight data of aging prediction models and artificial intelligence algorithm models; the memristor in-memory computation macros can be configured to aging prediction mode to execute aging prediction methods, or to normal operation mode to execute regular inference tasks of artificial intelligence algorithm models. The inter-chip routing module is used to realize data interaction and instruction distribution between multiple storage / computing macros; The global aging prediction control / processing module dynamically switches the working mode of each memory-accelerator macro or the data storage type within the memory-accelerator macro based on the aging status classification results of each memory-accelerator macro. It can also deploy a digital logic PE array within the module to execute the aging prediction method and achieve equalization of the aging process of each memory-accelerator macro.

[0015] Preferably, the memristor storage / computation macro includes a storage / computation function module and a local configuration module; the storage / computation function module includes a memristor array and peripheral circuitry, the memristor array being composed of memristor bit cells; the memristor array of the storage function module is used to store conventional data or weight data of aging prediction models and artificial intelligence algorithm models, the memristor array of the computation function module is used to store weights and perform weighted summation or logical operations; the peripheral circuitry includes a read / write driver module, an address decoding and gating module, and an auxiliary calculation module; the local configuration module is used to control the operation of the storage / computation function module and dynamically switch the operating mode or data storage type of each memristor storage / computation macro.

[0016] According to another aspect of the present invention, a dynamic switching mechanism for storage / computing macro tasks of a memristor in-memory computing chip based on artificial intelligence aging prediction is provided. The aging degree of each storage / computing macro is evaluated by periodically executing an aging prediction method, and the operating conditions and workload of each storage / computing macro are adjusted in real time according to the aging state classification results, so as to achieve the balancing of the memristor aging process within the system.

[0017] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects: 1. The artificial intelligence-based memristor in-memory computing chip aging prediction method proposed in this invention trains the artificial intelligence algorithm model by preprocessing the measurement dataset of memristor bit cell read and write operations during actual operation to construct a multi-dimensional training dataset. This results in an inference model that predicts the aging process of each storage / computing macro in the memristor in-memory computing device. This method is based on a lightweight artificial intelligence algorithm model, such as a spiking neural network (SNN), to process multi-dimensional device operation characteristics and predict device aging. It has higher power efficiency in processing timing characteristics and is more suitable for deployment in edge intelligence scenarios, effectively improving the overall lifespan and reliability of the memristor in-memory computing system.

[0018] 2. The computing device for predicting the aging of memristor in-memory computing chips based on artificial intelligence proposed in this invention has a real-time aging monitoring function. It can collect device operation data during the reasoning process of real-time artificial intelligence algorithm model inference task and complete the aging state prediction in combination with artificial intelligence algorithm model. The device integrates conventional in-memory computing / storage and reliability assessment mechanisms, thereby improving the stability and reliability of computing and storage.

[0019] 3. The dynamic switching mechanism for storage / in-memory computing macro tasks based on aging state prediction proposed in this invention can adjust the workload and operating conditions of storage / in-memory computing macros in the computing device according to the aging degree of the device, avoid high-frequency tasks being concentrated on some storage / in-memory computing macros, reduce the risk of local aging, and achieve task balance and life extension within the system. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of the computing device for predicting the aging of memristor memory chips based on artificial intelligence in an embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram of an aging prediction method using a spiking neural network (SNN) as an example in this invention.

[0022] Figure 3 This is a flowchart of the dynamic switching and control mechanism for in-memory macro-tasks based on aging state prediction in an embodiment of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0024] like Figure 1-3As shown, this invention proposes an artificial intelligence-based method for predicting the aging of memristor-based in-memory computing chips. This method is used to predict the aging degree of each memristor within a memristor macro during actual inference applications of memristor-based in-memory computing chips and output a device failure risk classification. The method includes the following steps: (1) During the execution of the artificial intelligence algorithm model inference task, the local configuration modules of each memory macro record the key operating parameters of the device to form the original dataset Data_Measure, which contains the multi-dimensional operating information of each memristor bit cell in each write cycle.

[0025] More specifically, the original dataset Data_Measure is A n ={A n [0], A n [1],…, A n [M-1]}, where A n [i]={VF_SEL[i], VF_WRT[i], RF[i], VS_SEL[i], VS_WRT[i], RS[i], NS[i], VR_SEL[i], VR_WRT[i], RR[i], NR[i]} n It contains 11 dimensions of device operation information, where n is the nth measurement stage, n∈[0, N-1]; M is the number of memory macros in the memristor memory chip, where i is the i-th memory macro, i∈[0, M-1]; A n The data structure of [i] is C×11×T, where C is the number of memristor bit cells in the storage macro and T is the number of memristor write cycles in a measurement phase. More specifically, VF_SEL c t VF_WRT is the gate voltage for the bit cell in the molding operation. c t Write voltage to the bit cell for the molding operation, RF c t VS_SEL is the bit cell resistance value for the molding operation. c t VS_WRT is the gate voltage for the bit cell in the set operation. c t Write voltage to the bit cell for the set operation, RS c t NS represents the resistance value of the bit cell after setting. c t VR_SEL is the number of verification attempts set. c t VR_WRT is the bit cell gate voltage for the reset operation. c t The write voltage to the bit cell for the reset operation, RRc t NR is the resistance value of the bit cell after reset. c t The number of reset verifications is given; where c is the c-th memristor bit cell in the stored macro, c∈[0, C-1], and t is the t-th memristor write cycle, t∈[0, T-1]; this embodiment takes a one-transistor-one-memristor (1T1R) bit cell structure as an example, and the measurement data A n [i] is characterized by: A. Perform an initial forming operation on the c-th bit cell of the stored-function macro, and record the transistor gate voltage VF_SEL during the forming operation. c The bit cell write voltage VF_WRT for the molding operation c And the resistance RF of the formed unit c And record the result of the molding operation O; B. Perform a set operation on the c-th macro-bit cell after forming, and record the transistor gate voltage VR_SEL of the set operation. c t Write voltage VR_WRT for the bit cell during the set operation c t The resistance value RS of the set bit unit c t And the number of verification operations NS c t And record the result O of the molding operation; where the number of verifications is the number of set-verification cycles by gradually increasing the transistor gate voltage and the bit cell write voltage; C. Perform a reset operation on the formed in-memory macrocell and record the transistor gate voltage VR_SEL during the reset operation. c t Bit cell write voltage VR_WRT during reset operation c t The resistance value RR of the reset unit c t And the number of verification operations RS for reset operations c t And record the result of the molding operation O; D. The bit cells in the storage macro perform operations (B) to (C) in a loop, and execute a total of T write loop cycles, which are recorded as one measurement stage. The dataset Data_Measure contains a total of N measurement stages. (2) Preprocess the operational data of the memristor bit cells to construct a dataset Data_Training for training the aging prediction model. More specifically, the dataset Data_Training contains input data B for multiple measurement stages.n ={B n [0], B n [1],…,B n [M-1]}, where n is the nth measurement stage, n∈[0,N-1], and M is the number of memory macros in the memristor memory chip; where B n [i]={VF_SEL_NOM[i], VF_WRT_NOM[i], RF_NOM[i], VS_SEL_NOM[i], VS_WRT_NOM[i], RS_NOM[i], NS_NOM[i], VR_SEL_NOM[i], VR_WRT_NOM[i], RR_NOM[i], NR_NOM[i]} n Let i be the i-th stored macro, i∈[0,M-1]; B n The data structure of [i] is C×11×T, where C is the number of memristor bit cells in the macro memory and T is the number of memristor write cycles in one measurement phase; B n The data characteristics of [i] are: A. VF_SEL_NOM c VS_SEL_NOM c t VR_SEL_NOM c t These are the transistor gate voltages VF_SEL. c VS_SEL c t VR_SEL c t After normalization, we obtain: where c is the c-th memristor bit cell within the memory macro, c∈[0, C-1], and t is the t-th memristor write cycle period, t∈[0, T-1]. The normalization method is as follows: ; ; ; Among them VF_SEL min and VF_SEL max These are the minimum and maximum transistor gate voltages for memristor shaping operations, VS_SEL, respectively. min and VS_SEL max VR_SEL represents the minimum and maximum transistor gate voltages for the memristor set operation, respectively. min and VR_SEL max These are the minimum and maximum transistor gate voltages for the memristor reset operation, respectively; B. VF_WRT_NOM cVS_WRT_NOM c t VR_WRT_NOM c t The write voltage VF_WRT for each bit cell c VS_WRT c t VR_WRT c t The result is obtained after normalization; the normalization method is as follows: ; ; ; VF_WRT min and VF_WRT max These are the minimum and maximum bit cell write voltages for memristor shaping operations, VS_WRT. min and VS_WRT max VR_WRT represents the minimum and maximum bit cell write voltages for the memristor set operation, respectively. min and VR_WRT max These are the minimum and maximum bit cell write voltages for the memristor reset operation, respectively. C. VF_WRT_NOM c VS_WRT_NOM c t VR_WRT_NOM c t The write voltage VF_WRT for each bit cell c VS_WRT c t VR_WRT c t The result is obtained after normalization; the normalization method is as follows: ; ; ; RF min and RF max These are the minimum and maximum bit cell resistance values ​​for the memristor shaping operation, respectively, RS min and RS max These are the minimum and maximum bit cell resistance values ​​for the memristor set operation, RR. min and RR max These are the minimum and maximum bit cell resistance values ​​for the memristor reset operation, respectively; D.NS_NOM c t NR_NOMc t The number of verifications (NS) are respectively c t NR c t The result is obtained after normalization; the normalization method is as follows: ; ; Among them NS min and NS max These represent the minimum and maximum number of verifications for a memristor set operation, respectively, NR. min and NR max These are the minimum and maximum bit cell resistance values ​​for the memristor reset operation, respectively; (3) Based on the operational behavior of each bit cell c in the current measurement stage n and the following x measurement stages, an aging state label is applied to the input data of the bit cell in the nth measurement stage using a risk metric function, so as to achieve refined construction of the training dataset and efficient training of subsequent artificial intelligence algorithm models, such as the SNN model in this embodiment; where c∈[0, C-1], n∈[0, N-1]; the formula is as follows:

[0026] in This is a comprehensive risk measurement function that reflects the operational failure tendency and physical drift risk across multiple measurement phases following the current phase; among which... This is an indicator of the frequency of operation failures. It is a characteristic indicator of volatility and mean correlation; and This is the adjustment coefficient.

[0027] Preferably, It can be defined as:

[0028] The value is 1 if the t-th write operation fails in the (n+k)-th measurement phase, and 0 otherwise. To explain further, It can be defined as a polynomial that includes the variance and mean of the operating conditions and results of the bit unit in the current operating phase, the degree of deviation of these variances from the data of the first operating phase, and the trend of the change of the variances of the operating conditions and results in future multi-measurement phases, and is used to assess the failure risk characteristics of the bit unit. Risk score is used to adapt to the training of artificial intelligence algorithm models. The normalization process is performed using the following formula:

[0029] The obtained labels ∈ [0, 1]; Preferably, the labels can be classified into multiple levels according to their numerical values, namely healthy, mildly degraded, severely degraded and about to fail, for training the artificial intelligence algorithm model; the artificial intelligence algorithm model can be the SNN model provided in this embodiment, or it can be a traditional machine learning, deep neural network (DNN) and other algorithm models.

[0030] (4) such as Figure 2 As shown, the data B n The pulse is converted into a T-step time sequence using frequency encoding and then input to... Figure 3 The SNN model shown contains a multi-layered neuron structure. Each input dimension corresponds to an input spiking neuron; the model generates an output spiking sequence through time-step propagation, and counts the number of spiking neurons or the final membrane potential as the prediction result.

[0031] As a supplement to the above-described SNN-based aging prediction method embodiment, this invention proposes another embodiment of an aging prediction method based on a deep neural network (DNN). Steps (1) to (3) of the deep neural network (DNN)-based aging prediction method embodiment are the same as those of the SNN model embodiment. For step (4), the DNN model directly receives the aforementioned continuous value feature vector B. n As input, feature mapping and nonlinear transformation are performed through multiple fully connected layers or convolutional layers, without the need for pulse frequency encoding; the output layer generates a continuous risk score and performs the multi-category risk level prediction. After forward propagation of the network, the output layer directly generates the risk prediction value or risk classification result for the memristor bit cell.

[0032] It is understood that the DNN-based aging prediction method implementation differs from the SNN-based implementation in terms of input / output signal types, neuron computation mechanisms, and model inference methods, but its training data, risk label construction methods, and prediction targets are the same, and thus fall within the scope of protection of this invention.

[0033] Another embodiment of the present invention proposes a computing device for predicting the aging of memristor-based memory chips based on artificial intelligence, such as... Figure 1As shown, this device dynamically adjusts the workload of each memory-based computing macro at the system level based on the aging analysis and prediction results of an artificial intelligence algorithm model. It prioritizes reducing the write / erase load of memory-based computing macros with higher aging levels and failure risks, thereby balancing the aging process of memory-based computing macros within the system. In this embodiment, the memristor-based memory-based computing aging prediction calculation device includes a memristor storage / computing macro array, a global aging prediction control / processing module, and on-chip memory. The memristor-based computing macro array includes two or more memristor-based computing macro modules 1 and the same number of inter-chip routing modules 2 as the computing macros. Each computing macro is used to perform inference calculations for the artificial intelligence model, including a storage / computing function module 11 and a local configuration module 12.

[0034] Figure 1 The storage / computation macro shown has two operating modes when it is a storage / computation function macro: normal operating mode and aging prediction mode. The storage / computation macro in normal operating mode is the core of storage and computation in the computing device that processes actual AI inference tasks based on an artificial intelligence algorithm model. The storage / computation macro in aging prediction mode is the core of computation in the computing device embodiment that performs aging prediction inference on the storage / computation macro in normal operating mode based on an artificial intelligence algorithm model, and the weight data of the trained aging prediction model is stored in this storage / computation macro. The weight data stored in different storage / computation macros needs to have different update frequencies depending on the specific task and model mapping, resulting in different degrees of bit cell aging.

[0035] In each of the stored-component macros shown, the memristor array in the stored-component function module 11 is a transistor-memristor (1T1R) array, used to store weight data of the artificial intelligence algorithm model or aging prediction model for executing the aging prediction method. It is understood that the memristor-based in-memory computing system in this embodiment may also include other forms and different sizes of memristor arrays. The peripheral circuits in the shown stored-component function module 11 include an address decoding and gating module, a read / write driver module, and an auxiliary computing module, used for gating bit units, reading and writing bit units, and completing the inference calculation tasks of the algorithm model, respectively. The shown local configuration module 12 is used to control the operation of the stored-component macro and simultaneously record and upload the key parameters of the bit unit operations within the stored-component function module.

[0036] The global aging prediction control / processing module shown is used to record and process key operating parameters of the global device, store the recorded parameters in the on-chip memory module, and control the local configuration module to adjust the operating conditions of each storage macro. Alternatively, a digital logic PE array can be deployed in the global aging prediction control / processing module to execute the aging prediction method.

[0037] The inter-chip routing module 3 shown corresponds one-to-one with the in-memory macro, providing an inter-chip communication interface for the in-memory macro and realizing the following functions: (1) Data interaction: obtain key parameters of device operation of the in-memory macro through inter-chip routing, or transmit data for aging prediction method and AI inference calculation task; (2) Instruction distribution: send task allocation instructions (such as switching working mode) to each in-memory macro through inter-chip routing; (3) Result feedback: feed back inference error to the global aging prediction control / processing module through inter-chip routing to verify the accuracy of aging prediction.

[0038] Combination Figure 2 and Figure 3 This document provides a detailed description of the workflow of the computing device and the dynamic switching mechanism for in-memory macro-tasks based on artificial intelligence aging state prediction in this embodiment. The workflow of the computing device is divided into a normal operation phase and an aging prediction execution phase, which is triggered periodically. The specific process is as follows: (1) During the normal operation phase, the stored-component macros configured in aging prediction mode within the computing device are turned off, while other stored-component macros configured in normal operation mode execute the AI ​​inference task normally. The inference results are transmitted to the output of the computing device through the inter-chip routing module 2. At the same time, the local configuration module 12 of the stored-component macros records the device erase / write voltage and cycle number, read resistance, and other device operating conditions and operation result parameters A for this inference. n The data is uploaded to the global aging prediction control / processing module via the inter-chip routing module 2; device operation parameter A n B was obtained after preprocessing. n The data is then stored in on-chip memory. The computing device maintains this stage until the number of weight updates for the stored-macro 1 in normal operating mode reaches N_update_macro, which serves as the trigger condition for the aging prediction execution stage.

[0039] (2) During the aging prediction execution phase, the stored-value macro or digital logic PE array that enables the aging prediction mode will store multi-dimensional data B. n After pulse frequency encoding, the data is input into the SNN aging prediction model, which outputs a failure risk classification for each in-memory macro. Further, the computing device reallocates inference tasks and AI model mappings based on the failure risk classification results of the in-memory macros. In-memory macros that are about to fail are shut down, and the operating conditions of mildly and severely degraded in-memory macros are adjusted. Severely degraded in-memory macros are assigned light workload inference tasks, while healthy and mildly degraded in-memory macros are assigned heavy workload inference tasks. After completing scheduling and updating the routing configuration, the system automatically switches back to the normal operating phase and enters the next cycle.

[0040] As a supplement to the above-described embodiment of the AI-based memristor in-memory computing macro aging prediction method computing device, this invention proposes another embodiment of the AI-based memristor storage macro aging prediction method computing device. The memristor storage macro is used to store regular data or weight data of a regular AI model and an aging prediction model. The aging prediction method is executed by a digital logic PE array deployed within a global aging prediction control / processing module, used to monitor the aging state of the AI-based memristor in-memory computing chip in real time. The workflow of the storage macro task dynamic switching mechanism based on aging state prediction includes a normal operation phase and an aging prediction execution phase. The aging prediction execution phase is triggered by the number of data updates within the storage macro reaching a preset value. During the aging prediction execution phase, the digital logic PE array is enabled to execute the aging prediction method to classify the aging state of the storage macro. The global aging prediction control / processing module adjusts the operating conditions of the storage macro according to the classification results, and adjusts the workload of each storage macro according to the data refresh frequency of different data types.

[0041] It is understood that the embodiment of the memristor storage macro aging prediction method computing device based on artificial intelligence differs from the embodiment of the storage macro aging prediction method computing device only in the functional type of the memristor macro module, and is also within the protection scope of this invention.

[0042] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An artificial intelligence-based aging prediction method for a resistive memory computing chip, characterized in that, The method comprises the following steps: Obtaining operation parameters of each storage / computing macro of the memristor storage / computing chip in the process of executing an inference task, and constructing an original data set Data_Measure containing device aging characteristics according to the operation parameters, wherein the original data set Data_Measure contains multi-dimensional operation information of each memristor bit cell in each write cycle period; Normalizing and classifying the measurement data of the original data set Data_Measure to obtain a multi-dimensional training data set Data_Training for artificial intelligence model training; Training an artificial intelligence algorithm model using the multi-dimensional training data set Data_Training to obtain an inference model for predicting the aging state of the memristor storage / computing chip; Inputting real-time collected operation data of the memristor storage / computing chip into the inference model to output the aging state classification result of each memristor storage / computing macro.

2. The artificial intelligence-based aging prediction method for memristor in-memory computing chips according to claim 1, characterized in that, The data structure in the original data set Data_Measure is CxDxT, wherein C is the total number of bit cells in the memristor storage / computing macro, T is the number of periods of the memristor write cycle contained in the measurement data in one measurement stage; the original data set Data_Measure contains measurement data A of D dimensions n ; wherein n is the nth measurement stage, and the measurement data contains the operation condition and operation result of the bit cell.

3. The method of claim 2, wherein the method is based on artificial intelligence. The method for constructing the original data set Data_Measure comprises the following steps: S11, performing an initial shaping operation on the bit cells in the storage / computing macro, and recording the operation conditions and operation results of the shaping operation; S12, performing a setting operation on the shaped storage / computing macro bit cells, and recording the operation conditions and operation results of the setting operation; S13, performing a resetting operation on the shaped storage / computing macro bit cells, and recording the operation conditions and operation results of the resetting operation; S14, the bit cells in the storage / computing macro cyclically perform the operations of S12-S13, a total of T write cycle periods are executed and recorded as one measurement stage; the data set Data_Measure contains a total of N measurement stages.

4. The artificial intelligence-based aging prediction method for memristor computing-in-memory chips according to claim 3, characterized in that, The multi-dimensional training data set Data_Training includes multi-dimensional input data B n ; multi-dimensional input data B n obtained by normalizing the original data set Data_Measure.

5. The artificial intelligence-based aging prediction method for memristor computing-in-memory chips according to claim 4, wherein The classification and labeling comprises the following steps: Based on the operation conditions and operation results of each bit cell c in the nth measurement stage and a plurality of measurement stages after the nth measurement stage, a risk measurement function is used to label the input data of the bit cell in the nth measurement stage to realize the construction of the multi-dimensional training data set Data_Training and the subsequent training of the artificial intelligence algorithm model.

6. The artificial intelligence-based aging prediction method for memristor computing-in-memory chips according to claim 5, wherein The formula of the risk metric function is: wherein is a comprehensive risk metric function, which can reflect the operation failure tendency of the bit cell in the current operation phase and the physical drift risk; is an operation failure frequency index; is a volatility and mean characteristic of the operation behavior, and a mean deviation degree characteristic index; and is an adjustment coefficient.

7. The artificial intelligence-based aging prediction method for memristor computing-in-memory chips according to claim 6, characterized in that, In the nth measurement stage, the operation behavior characteristics of the bit cell are counted, and a plurality of measurement stages after the current measurement stage are taken as a future prediction window, the evolution trend and operation failure frequency of the operation behavior characteristics of the bit cell in the future prediction window are counted to form a comprehensive degradation characteristic sequence; According to the characteristic sequence, the failure risk measurement function value corresponding to the nth measurement stage is calculated, which is used to measure the tendency strength of the bit cell to occur permanent failure or near failure in the prediction window, and is used as the failure risk label value corresponding to the nth measurement stage.

8. An artificial intelligence-based aging prediction computing device for memristor in-memory computing chips, comprising: The method comprises the following steps: A plurality of memristor storage / computing macros and a memristor storage / computing macro array of an inter-chip routing module, a global aging prediction control / processing module, and an on-chip memory; The memory resistor storage / computing macro is an independent storage or in-memory computing functional unit; the memory resistor storage macro is used for storing conventional data or storing weight data of an aging prediction model and an artificial intelligence algorithm model; the memory resistor storage / computing macro can be configured as an aging prediction mode and used for executing an aging prediction method, and can also be configured as a normal working mode and used for executing a conventional inference task of the artificial intelligence algorithm model; The inter-chip routing module is used for realizing data interaction and instruction distribution among the plurality of memory resistor storage / computing macros. The global aging prediction control / processing module dynamically switches the working mode of each memory resistor storage / computing macro or the data storage type in the storage macro according to the aging state classification result of each memory resistor storage / computing macro; a digital logic PE array can also be deployed in the module and used for executing the aging prediction method, so as to realize equalization of the aging process of each memory resistor storage / computing macro.

9. The computing device for artificial intelligence based memristor storage computing chip aging prediction of claim 8, wherein, The memory resistor storage / computing macro comprises a storage / computing functional module and a local configuration module; the storage / computing functional module comprises a memory resistor array and a peripheral circuit, and the memory resistor array is composed of memory resistor bit cells; the memory resistor array of the storage functional module is used for storing conventional data or weight data of an aging prediction model and an artificial intelligence algorithm model, and the memory resistor array of the storage / computing functional module is used for storing weight and executing weighted summation or logical operation; the peripheral circuit comprises a read / write driving module, an address decoding and gating module and an auxiliary computing module; and the local configuration module is used for controlling the work of the storage / computing functional module and dynamically switching the working mode of each memory resistor storage / computing macro or the data storage type.

10. A storage / computing macro task dynamic switching mechanism of an artificial intelligence aging prediction based memristor storage / computing chip, characterized in that, The aging degree of each memory resistor storage / computing macro is evaluated by periodically executing an aging prediction method, and the operation condition and working load of each memory resistor storage / computing macro are adjusted in real time according to the aging state classification result, so as to realize equalization of the aging process of the memory resistors in the system.

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