Back side power chip package structure and method of manufacturing the same

Abstract

The application provides a back power supply chip packaging structure and a preparation method thereof. The back power supply logic chip is composed of a first semiconductor substrate, a first transistor layer, a passivation layer, a first signal wiring layer and a first power supply wiring layer, and the back power supply logic chip is used to stack a memory chip, so that the packaging thickness is effectively reduced and the packaging structure size is reduced. The back power supply logic chip and the metal column penetrating through the inside of the first transistor layer can effectively shorten the transmission distance and reduce the power consumption.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor manufacturing, and relates to a backside power supply chip packaging structure and a preparation method thereof. BACKGROUND

[0002] In traditional 2.5D or 3D advanced packaging, most of the wiring is on the front side of the wafer, and the signal lines and power supply lines are vertically stacked and connected to form a semiconductor device of two or more layers of active electronic elements of an integrated circuit, and the chip is supplied with power through the power supply line to form a power supply network, but there is a signal network formed by the signal lines in the front area of the chip, that is, the signal network layer and the power supply network layer are both located on the same side of the chip, and the power supply network is made on the front side of the chip, which means that the power supply network and the signal network in the chip must share space, and it is difficult to further reduce the volume of the entire packaging structure, making the miniaturization and high-density integration of the semiconductor packaging structure face more and more challenges. Therefore, the industry has begun to explore transferring the power supply network to the back side to make backside power supply (Backside PDN) a popular technical issue.

[0003] Therefore, it is necessary to provide a backside power supply chip packaging structure and a preparation method thereof. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a backside power supply chip packaging structure and a preparation method thereof, which can solve the problem that the semiconductor packaging structure is difficult to realize miniaturization and high-density integration in the prior art.

[0005] To achieve the above-mentioned purpose and other related purposes, the present application provides a preparation method of a backside power supply chip packaging structure, comprising the following steps:

[0006] providing a first semiconductor substrate;

[0007] forming a first transistor layer on the front side of the first semiconductor substrate;

[0008] forming a first signal wiring layer on the first transistor layer, and the first signal wiring layer is electrically connected with the first transistor layer;

[0009] forming a first re-wiring layer on the first signal wiring layer, and the first re-wiring layer is electrically connected with the first signal wiring layer;

[0010] providing a chip, the chip comprising a second semiconductor substrate, a second transistor layer and a composite wiring layer stacked, the composite wiring layer comprising a second signal wiring layer and a second power supply wiring layer, and the second signal wiring layer and the second power supply wiring layer are both electrically connected with the second transistor layer;

[0011] forming a second re-wiring layer on the composite wiring layer, and the second re-wiring layer is electrically connected with the second signal wiring layer and the second power wiring layer;

[0012] bonding the first re-wiring layer and the second re-wiring layer, and the first re-wiring layer and the second re-wiring layer are electrically connected;

[0013] thinning the first semiconductor substrate from the back surface thereof;

[0014] forming a passivation layer on the back surface of the first semiconductor substrate;

[0015] forming a metal pillar penetrating through the passivation layer, the first semiconductor substrate and the first transistor layer, and a first end of the metal pillar is electrically connected with the first signal wiring layer and the first transistor layer;

[0016] forming a first power wiring layer on the surface of the passivation layer, and the first power wiring layer is electrically connected with a second end of the metal pillar;

[0017] forming a metal bump on the surface of the first power wiring layer, and the metal bump is electrically connected with the first power wiring layer.

[0018] Optionally, the method for thinning the first semiconductor substrate comprises one or a combination of mechanical grinding and CMP method; the thickness of the thinned first semiconductor substrate is 1-10 μm.

[0019] Optionally, the first semiconductor substrate comprises a silicon substrate; and the second semiconductor substrate comprises a silicon substrate.

[0020] Optionally, the passivation layer comprises an epoxy layer, a polyamide layer, a silicon nitride layer or a silicon oxide layer.

[0021] Optionally, the first signal wiring layer, the first power wiring layer, the second signal wiring layer, the second power wiring layer, the first re-wiring layer and the second re-wiring layer are prepared by Damascene process.

[0022] Optionally, the method further comprises a cutting process, wherein the cutting method comprises one or a combination of mechanical cutting and laser cutting.

[0023] The application further provides a back surface power supply chip packaging structure, which comprises:

[0024] a first semiconductor substrate;

[0025] a first transistor layer on the front surface of the first semiconductor substrate;

[0026] a passivation layer located on the back surface of the first semiconductor substrate;

[0027] a first signal wiring layer located on the first transistor layer, and the first signal wiring layer and the first transistor layer are electrically connected;

[0028] a first rewiring layer located on the first signal wiring layer, and the first rewiring layer and the first signal wiring layer are electrically connected;

[0029] a chip is provided, which comprises a second semiconductor substrate, a second transistor layer and a composite wiring layer, the composite wiring layer comprises a second signal wiring layer and a second power supply wiring layer, and the second signal wiring layer and the second power supply wiring layer are electrically connected with the second transistor layer;

[0030] a second rewiring layer located on the composite wiring layer, the second rewiring layer is electrically connected with the second signal wiring layer and the second power supply wiring layer, wherein the first rewiring layer and the second rewiring layer are bonded and electrically connected;

[0031] a metal column penetrating through the passivation layer, the first semiconductor substrate and the first transistor layer, and a first end of the metal column is electrically connected with the first signal wiring layer and the first transistor layer;

[0032] a first power supply wiring layer located on the surface of the passivation layer, and the first power supply wiring layer is electrically connected with a second end of the metal column;

[0033] a metal bump located on the surface of the first power supply wiring layer, and the metal bump is electrically connected with the first power supply wiring layer.

[0034] Optionally, the thickness of the first semiconductor substrate is 1-10 μm; the first semiconductor substrate comprises a silicon substrate; and the second semiconductor substrate comprises a silicon substrate.

[0035] Optionally, the passivation layer comprises an epoxy resin layer, a polyamide layer, a silicon nitride layer or a silicon oxide layer.

[0036] Optionally, the chip is a memory chip; and the first semiconductor substrate, the first transistor layer, the passivation layer, the first signal wiring layer and the first power supply wiring layer constitute a back surface power supply logic chip.

[0037] As described above, the back power supply chip packaging structure and the preparation method thereof, the back power supply logic chip is formed by the first semiconductor substrate, the first transistor layer, the passivation layer, the first signal wiring layer and the first power supply wiring layer, and the back power supply logic chip is used to stack the memory chip, so that the packaging thickness is effectively reduced, and the packaging structure size is reduced; the back power supply logic chip and the metal column penetrating through the inside of the first transistor layer can effectively shorten the transmission distance and reduce the power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 A process flow diagram for preparing the back power supply chip packaging structure in the embodiment of the present application is shown.

[0039] Figure 2 A structure diagram after forming the first transistor layer in the embodiment of the present application is shown.

[0040] Figure 3 A structure diagram after forming the first re-wiring layer in the embodiment of the present application is shown.

[0041] Figure 4 A structure diagram after bonding the first re-wiring layer and the second re-wiring layer in the embodiment of the present application is shown.

[0042] Figure 5 A structure diagram after thinning the first semiconductor substrate in the embodiment of the present application is shown.

[0043] Figure 6 A structure diagram after forming the metal column in the embodiment of the present application is shown.

[0044] Figure 7 A structure diagram after forming the metal bump in the embodiment of the present application is shown.

[0045] REFERENCE SIGNS

[0046] 100 back power supply logic chip

[0047] 101 first semiconductor substrate

[0048] 102 first transistor layer

[0049] 103 first signal wiring layer

[0050] 104 passivation layer

[0051] 105 first power supply wiring layer

[0052] 200 memory chip

[0053] 201 second semiconductor substrate

[0054] 202 second transistor layer

[0055] 203 Composite Wiring Layer

[0056] 301 First Rerouting Layer

[0057] 302 Second Rerouting Layer

[0058] 400 metal column

[0059] 500 metal bumps Detailed Implementation

[0060] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0062] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0063] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0064] The embodiment provides a preparation method of a back power supply chip packaging structure, wherein the back power supply chip takes a back power supply logic chip as an example, a storage chip adopting a single-side stacked signal / power supply wiring layer is integrated and packaged with the back power supply logic chip, and the types of the back power supply chip and the chip combined with the back power supply chip are not limited to this.

[0065] In the embodiment, the back power supply logic chip stacks the storage chip, so that the packaging thickness can be effectively reduced, the packaging structure size can be reduced, the transmission distance can be effectively shortened, and power consumption can be reduced.

[0066] The following is described in combination with the specification Figures 1-7 Further description is provided for the back power supply chip packaging structure and the preparation method thereof in the embodiment.

[0067] Firstly, referring to Figure 1 and Figure 2 , a first semiconductor substrate 101 is provided in step S1.

[0068] Specifically, the first semiconductor substrate 101 can include a silicon substrate, a germanium substrate and the like, in the embodiment, the first semiconductor substrate 101 adopts a silicon substrate, but is not limited to this.

[0069] Preferably, the size of the first semiconductor substrate 101 is wafer level, so that the production efficiency can be improved through subsequent processes such as cutting, but the size of the first semiconductor substrate 101 is not limited to this.

[0070] Then, referring to Figure 1 and Figure 2 , a first transistor layer 102 is formed on the front surface of the first semiconductor substrate 101 in step S2.

[0071] Specifically, a plurality of transistors (not shown) can be arranged in the first transistor layer 102, that is, the first transistor layer 102 can have a plurality of source regions, drain regions and gate regions, and the transistors adjacent to each other can be isolated through an isolation structure (not shown) or the like. The specific types, preparation, structure and distribution of the transistors are not limited here.

[0072] Then, referring to Figure 1 and Figure 3 , a first signal wiring layer 103 is formed on the first transistor layer 102 in step S3, and the first signal wiring layer 103 is electrically connected with the first transistor layer 102.

[0073] Specifically, the first signal wiring layer 103 comprises a dielectric layer and a metal wiring, the material of the dielectric layer can comprise polymers such as polybenzoxazole, polyimide, or inorganic dielectric materials such as silicon nitride, silicon oxide, etc., which are not limited herein. The material of the metal wiring can comprise aluminum, copper, tungsten, or their alloys, which are not limited herein.

[0074] The specific structure, material and preparation method of the first signal wiring layer 103 are not limited herein, and can be referred to the prior art, such as the process formed by combining photolithography, etching, electroplating or deposition, etc.

[0075] Specifically, the metal wiring in the first signal wiring layer 103 comprises a metal signal wiring for transmitting signals to the backside power supply logic chip, and a metal power supply wiring for transmitting power to the memory chip 200.

[0076] Then, referring to Figure 1 and Figure 3 , step S4 is performed to form a first re-wiring layer 301 on the first signal wiring layer 103, and the first re-wiring layer 301 is electrically connected with the first signal wiring layer 103.

[0077] Specifically, the first re-wiring layer 301 can comprise a dielectric layer and a metal wiring, the material of the dielectric layer can comprise polymers such as polybenzoxazole, polyimide, or inorganic dielectric materials such as silicon nitride, silicon oxide, etc., which are not limited herein. The material of the metal wiring can comprise aluminum, copper, tungsten, or their alloys, which are not limited herein. The specific structure, material and preparation method of the first re-wiring layer 301 are not limited herein, and can be referred to the prior art, such as the process formed by combining photolithography, etching, electroplating or deposition, etc.

[0078] Then, referring to Figure 1 and Figure 4 , step S5 is performed to provide a chip comprising a second semiconductor substrate 201, a second transistor layer 202 and a composite wiring layer 203 stacked in sequence, the composite wiring layer 203 comprises a second signal wiring layer and a second power supply wiring layer, and the second signal wiring layer and the second power supply wiring layer are both electrically connected with the second transistor layer 202.

[0079] Specifically, the second semiconductor substrate 201 can comprise a silicon substrate, a germanium substrate, etc., in the embodiment, the second semiconductor substrate 201 adopts a silicon substrate, but is not limited thereto. The size of the second semiconductor substrate 201 is preferably wafer level, so as to improve the production efficiency by subsequent processes such as cutting, but the size of the second semiconductor substrate 201 is not limited thereto.

[0080] The second transistor layer 202 can be provided with a plurality of transistors (not shown), i.e. a plurality of source regions, drain regions, and gate regions, and adjacent transistors can be isolated by an isolation structure (not shown). The specific type, preparation, structure, and distribution of the transistors are not limited herein.

[0081] The composite wiring layer 203 is located on the same side of the second transistor layer 202, and includes a second signal wiring layer for transmitting signals to the memory chip and a second power wiring layer for transmitting power to the memory chip, and the second signal wiring layer and the second power wiring layer are electrically connected to the second transistor layer 202.

[0082] The composite wiring layer 203 includes a dielectric layer and a metal wiring. The material of the dielectric layer can include polymers such as polybenzoxazole and polyimide, or inorganic dielectric materials such as silicon nitride and silicon oxide, which are not limited herein. The material of the metal wiring can include aluminum, copper, tungsten, or alloys thereof, which are not limited herein.

[0083] The specific structure, material, and preparation method of the composite wiring layer 203 are not limited herein, and can be referred to existing technologies, such as a process combining photolithography, etching, electroplating, or deposition.

[0084] Next, referring to Figure 1 and Figure 4 , step S6 is performed to form a second re-wiring layer 302 on the composite wiring layer 203, and the second re-wiring layer 302 is electrically connected to the second signal wiring layer and the second power wiring layer.

[0085] Specifically, the second re-wiring layer 302 can include a dielectric layer and a metal wiring. The material of the dielectric layer can include polymers such as polybenzoxazole and polyimide, or inorganic dielectric materials such as silicon nitride and silicon oxide, which are not limited herein. The material of the metal wiring can include aluminum, copper, tungsten, or alloys thereof, which are not limited herein. The specific structure, material, and preparation method of the second re-wiring layer 302 are not limited herein, and can be referred to existing technologies, such as a process combining photolithography, etching, electroplating, or deposition.

[0086] Next, referring to Figure 1 and Figure 4 , step S7 is performed to bond the first re-wiring layer 301 and the second re-wiring layer 302, and the first re-wiring layer 301 and the second re-wiring layer 302 are electrically connected.

[0087] Specifically, the bonding method of the first re-wiring layer 301 and the second re-wiring layer 302 is preferably a hybrid bonding process to realize high-density and high-performance interconnection between the first re-wiring layer 301 and the second re-wiring layer 302, but the bonding method of the first re-wiring layer 301 and the second re-wiring layer 302 is not limited thereto.

[0088] Wherein, through the bonding of the first re-wiring layer 301 and the second re-wiring layer 302, a transition path for signal and power transmission between the memory chip and the backside power supply logic chip can be formed to realize power supply and signal transmission of the backside power supply logic chip.

[0089] Next, referring to Figure 1 and Figure 5 , step S8 is performed to thin the first semiconductor substrate 101 from the back surface of the first semiconductor substrate 101.

[0090] As an example, the method for thinning the first semiconductor substrate 101 can include one or a combination of mechanical grinding and CMP.

[0091] Specifically, in this embodiment, the mechanical grinding method is first used to coarsely grind the first semiconductor substrate 101 to quickly perform the thinning process and improve efficiency, and then the CMP method is used to finely grind to improve the flatness of the grinding surface, but the thinning method of the first semiconductor substrate 101 is not limited thereto.

[0092] Through the thinning operation of the first semiconductor substrate 101, the thickness of the packaging structure can be effectively reduced, and in the vertical direction, due to the thinning of the first semiconductor substrate 101, the transmission path of the power supply and the signal can be effectively shortened, the transmission efficiency is improved, and the power consumption is reduced.

[0093] As an example, the thickness of the thinned first semiconductor substrate 101 can be 1-10 μm.

[0094] Specifically, the thickness of the thinned first semiconductor substrate 101 is preferably, for example, 1 μm, 2 μm, 3 μm, 5 μm, 8 μm, 10 μm, etc. The first semiconductor substrate 101 reserved after thinning can protect the first transistor layer 102 to avoid damaging the first transistor layer 102. The specific thickness of the reserved first semiconductor substrate 101 is preferably 1-3 μm in this embodiment to shorten the transmission path of the power supply and the signal as much as possible and reduce the packaging size.

[0095] Next, referring to Figure 1 and Figure 6Step S9 is executed to form a passivation layer 104 on the back side of the first semiconductor substrate 101.

[0096] Specifically, since the first semiconductor substrate 101 has low insulation properties and a thin thickness, when the passivation layer 104 is formed on the back side of the first semiconductor substrate 101, the passivation layer 104 can prevent the metal material from diffusing into the first transistor layer 102 in subsequent processes, such as causing short circuits when the metal pillar 400 is subsequently fabricated.

[0097] As an example, the passivation layer 104 may include an epoxy resin layer, a polyamide layer, a silicon nitride layer, or a silicon oxide layer, etc. The material, thickness, and preparation method of the passivation layer 104 are not excessively limited here.

[0098] Next, refer to Figure 1 and Figure 6 In step S10, a metal pillar 400 is formed that penetrates the passivation layer 104, the first semiconductor substrate 101 and the first transistor layer 102, and the first end of the metal pillar 400 is electrically connected to both the first signal wiring layer 103 and the first transistor layer 102.

[0099] Specifically, since the metal pillar 400 is electrically connected to the first transistor layer 102, power can be supplied to the transistor layer in the first transistor layer 102 through the metal pillar 400. Furthermore, since the metal pillar 400 includes a metal pillar 400 electrically connected to the first signal wiring layer 103, power can be supplied to the metal power wiring in the first signal wiring layer 103 through the metal pillar 400, so as to transmit power to the memory chip 200.

[0100] The metal pillar 400 can be prepared by methods such as electroplating to create nano-through silicon pores (n-TSV), but is not limited to this method. The method for preparing the metal pillar 400 and the distribution of the metal pillar 400 are not limited here.

[0101] Next, refer to Figure 1 and Figure 7 In step S11, a first power wiring layer 105 is formed on the surface of the passivation layer 104, and the first power wiring layer 105 is electrically connected to the second end of the metal pillar 400.

[0102] Specifically, the first power routing layer 105 can include a dielectric layer and a metal routing, the material of the dielectric layer can include polymers such as polybenzoxazole, polyimide, or inorganic dielectric materials such as silicon nitride, silicon oxide, etc., which are not limited here; the material of the metal routing can include aluminum, copper, tungsten, or their alloys, which are not limited here.

[0103] The specific structure, material and preparation method of the first power routing layer 105 are not limited here, and can refer to the prior art, such as using a combination of photolithography, etching, electroplating or deposition processes.

[0104] Among them, the metal routing in the first power routing layer 105 includes metal routing for supplying power to the first transistor layer 102, and includes metal routing for supplying power to the metal power routing.

[0105] Next, referring to Figure 1 and Figure 7 , step S12 is performed to form a metal bump 500 on the surface of the first power routing layer 105, and the metal bump 500 is electrically connected to the first power routing layer 105.

[0106] Specifically, the metal bump 500 can include solder ball bumps, C4 metal bumps, etc., and the specific types and materials of the metal bump 500 are not limited here.

[0107] As an example, the first signal routing layer 103, the first power routing layer 105, the second signal routing layer, the second power routing layer, the first re-routing layer 301 and the second re-routing layer 302 can all be prepared by Damascene process to improve production efficiency, improve product performance, and prolong the service life of the packaging structure.

[0108] Further, when the first semiconductor substrate 101 is a wafer-level or substrate-level substrate, after the metal bump 500 is formed, a cutting process step can also be included to divide the overall large-size packaging structure into multiple independent packaging unit structures, improving process efficiency.

[0109] Among them, the cutting method can include one or a combination of mechanical cutting and laser cutting, and the specific cutting method can be selected as needed.

[0110] Referring to Figures 2-7 , the embodiment also provides a backside power supply chip packaging structure, which can be prepared by the above-mentioned preparation method for the backside power supply chip packaging structure, such as Figures 2-7The embodiment directly uses the preparation process to prepare the back power supply chip packaging structure, and thus the preparation, material and specific structure of the back power supply chip packaging structure can be referred to the above method.

[0111] Specifically, the back power supply chip packaging structure comprises:

[0112] a first semiconductor substrate 101;

[0113] a first transistor layer 102 located on the front surface of the first semiconductor substrate 101;

[0114] a passivation layer 104 located on the back surface of the first semiconductor substrate 101;

[0115] a first signal wiring layer 103 located on the first transistor layer 102, and the first signal wiring layer 103 is electrically connected with the first transistor layer 102;

[0116] a first re-wiring layer 301 located on the first signal wiring layer 103, and the first re-wiring layer 301 is electrically connected with the first signal wiring layer 103;

[0117] a chip comprising a second semiconductor substrate 201, a second transistor layer 202 and a composite wiring layer 203 stacked, the composite wiring layer 203 comprising a second signal wiring layer and a second power supply wiring layer, and the second signal wiring layer and the second power supply wiring layer are electrically connected with the second transistor layer 202;

[0118] a second re-wiring layer 302 located on the composite wiring layer 203, the second re-wiring layer 302 is electrically connected with the second signal wiring layer and the second power supply wiring layer, wherein the first re-wiring layer 301 is bonded with the second re-wiring layer 302, and the first re-wiring layer 301 is electrically connected with the second re-wiring layer 302;

[0119] a metal column 400 penetrating the passivation layer 104, the first semiconductor substrate 101 and the first transistor layer 102, and the first end of the metal column 400 is electrically connected with the first signal wiring layer 103 and the first transistor layer 102;

[0120] a first power supply wiring layer 105 located on the surface of the passivation layer 104, and the first power supply wiring layer 105 is electrically connected with the second end of the metal column 400;

[0121] A metal bump 500 is located on the surface of the first power wiring layer 105, and the metal bump 500 is electrically connected with the first power wiring layer 105.

[0122] For example, the first semiconductor substrate 101 has a thickness of 1-10 microns; the first semiconductor substrate 101 comprises a silicon substrate; and the second semiconductor substrate 201 comprises a silicon substrate.

[0123] For example, the passivation layer 104 comprises an epoxy layer, a polyamide layer, a silicon nitride layer or a silicon oxide layer.

[0124] For example, the chip is a memory chip 200; and the first semiconductor substrate 101, the first transistor layer 102, the passivation layer 104, the first signal wiring layer 103 and the first power wiring layer 105 constitute a backside power logic chip 100.

[0125] In summary, the backside power chip packaging structure and the preparation method thereof, by the first semiconductor substrate, the first transistor layer, the passivation layer, the first signal wiring layer and the first power wiring layer, the backside power logic chip is constituted, and the memory chip is stacked by the backside power logic chip, the packaging thickness is effectively reduced, and the packaging structure size is reduced; the backside power logic chip and the metal column penetrating through the inside of the first transistor layer can effectively shorten the transmission distance and reduce the power consumption.

[0126] The above-mentioned embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A method for fabricating a back-side power supply chip packaging structure, characterized in that, Includes the following steps: Provide a first semiconductor substrate; A first transistor layer is formed on the front side of the first semiconductor substrate; A first signal wiring layer is formed on the first transistor layer, and the first signal wiring layer is electrically connected to the first transistor layer; A first rerouting layer is formed on the first signal routing layer, and the first rerouting layer is electrically connected to the first signal routing layer; A chip is provided, the chip comprising a stacked second semiconductor substrate, a second transistor layer and a composite wiring layer, the composite wiring layer comprising a second signal wiring layer and a second power wiring layer, and the second signal wiring layer and the second power wiring layer being electrically connected to the second transistor layer; A second rerouting layer is formed on the composite wiring layer, and the second rerouting layer is electrically connected to both the second signal wiring layer and the second power wiring layer. The first redistribution layer is bonded to the second redistribution layer, and the first redistribution layer is electrically connected to the second redistribution layer. Thinning of the first semiconductor substrate from its back side; A passivation layer is formed on the back side of the first semiconductor substrate; A metal pillar is formed that penetrates the passivation layer, the first semiconductor substrate, and the first transistor layer, and the first end of the metal pillar is electrically connected to both the first signal wiring layer and the first transistor layer. A first power wiring layer is formed on the surface of the passivation layer, and the first power wiring layer is electrically connected to the second end of the metal pillar; Metal bumps are formed on the surface of the first power wiring layer, and the metal bumps are electrically connected to the first power wiring layer. The chip is a memory chip; the first semiconductor substrate, the first transistor layer, the passivation layer, the first signal wiring layer, and the first power wiring layer constitute a back-side power supply logic chip; The metal wiring in the first signal wiring layer includes metal signal wiring for transmitting signals to the back-side power supply logic chip and metal power wiring for transmitting power to the memory chip. The metal wiring in the first power wiring layer includes metal wiring for supplying power to the first transistor layer and includes metal wiring for supplying power to the metal power wiring. Power is supplied to the metal power wiring through the metal pillar.

2. The method for fabricating the back-side power supply chip packaging structure according to claim 1, characterized in that: The method for thinning the first semiconductor substrate includes one or a combination of mechanical polishing and CMP; the thickness of the first semiconductor substrate after thinning is 1 to 10 μm.

3. The method for fabricating the back-side power supply chip packaging structure according to claim 1, characterized in that: The first semiconductor substrate includes a silicon substrate; the second semiconductor substrate includes a silicon substrate.

4. The method for fabricating the back-side power supply chip packaging structure according to claim 1, characterized in that: The passivation layer includes an epoxy resin layer, a polyamide layer, a silicon nitride layer, or a silicon oxide layer.

5. The method for fabricating the back-side power supply chip packaging structure according to claim 1, characterized in that: The first signal routing layer, the first power routing layer, the second signal routing layer, the second power routing layer, the first rerouting layer, and the second rerouting layer are all fabricated using the damascus process.

6. The method for fabricating the back-side power supply chip packaging structure according to claim 1, characterized in that: It also includes the cutting process steps, wherein the cutting methods include one or a combination of mechanical cutting and laser cutting.

7. A rear-side power supply chip packaging structure, characterized in that, The rear power supply chip packaging structure includes: First semiconductor substrate; A first transistor layer, wherein the first transistor layer is located on the front side of the first semiconductor substrate; A passivation layer is located on the back side of the first semiconductor substrate; A first signal routing layer is located on the first transistor layer, and the first signal routing layer and the first transistor layer are electrically connected. A first rerouting layer is located on the first signal routing layer and is electrically connected to the first signal routing layer. A chip is provided, the chip comprising a stacked second semiconductor substrate, a second transistor layer and a composite wiring layer, the composite wiring layer comprising a second signal wiring layer and a second power wiring layer, and the second signal wiring layer and the second power wiring layer being electrically connected to the second transistor layer; The second rerouting layer is located on the composite routing layer and is electrically connected to both the second signal routing layer and the second power routing layer. The first rerouting layer is bonded to the second rerouting layer and is electrically connected to the second rerouting layer. A metal pillar, which penetrates the passivation layer, the first semiconductor substrate and the first transistor layer, and the first end of the metal pillar is electrically connected to both the first signal wiring layer and the first transistor layer; A first power wiring layer is located on the surface of the passivation layer and is electrically connected to the second end of the metal pillar. A metal bump, the metal bump being located on the surface of the first power wiring layer and electrically connected to the first power wiring layer; The chip is a memory chip; the first semiconductor substrate, the first transistor layer, the passivation layer, the first signal wiring layer, and the first power wiring layer constitute a back-side power supply logic chip; The metal wiring in the first signal wiring layer includes metal signal wiring for transmitting signals to the back-side power supply logic chip and metal power wiring for transmitting power to the memory chip. The metal wiring in the first power wiring layer includes metal wiring for supplying power to the first transistor layer and metal wiring for supplying power to the metal power wiring. Power is supplied to the metal power wiring through the metal pillar.

8. The back-side power supply chip packaging structure according to claim 7, characterized in that: The thickness of the first semiconductor substrate is 1 to 10 μm; the first semiconductor substrate includes a silicon substrate; the second semiconductor substrate includes a silicon substrate.

9. The back-side power supply chip packaging structure according to claim 7, characterized in that: The passivation layer includes an epoxy resin layer, a polyamide layer, a silicon nitride layer, or a silicon oxide layer.

Images