A memory, storage device, and electronic device

Abstract

The application discloses a memory, a storage device and an electronic device, and relates to the technical field of memories, and specifically discloses a memory, which comprises a memory module, wherein the memory module comprises a circuit board, a memory chip and an auxiliary circuit; one side of the circuit board is provided with electrically connected pins for establishing electrical connection with a memory backboard; the memory chip and the auxiliary circuit are attached to the other side of the circuit board; and the cross-sectional dimension of the circuit board is smaller than that of the memory backboard. In the manner, the memory module can be produced independently, the architecture of the corresponding memory backboard is simpler, the number of layers is smaller, and the manufacturing cost is lower; and because the cross-sectional dimension of the circuit board is smaller than that of the memory backboard, the length of the data command address line for electrical connection of the memory chip can be reduced, so that the overall performance of the memory is improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and more particularly to a memory, storage device, and electronic device. Background Technology

[0002] Currently, memory modules in storage generally include UDIMM (desktop memory modules) and SODIMM (laptop memory modules). They are usually designed according to JEDEC (Joint Electron Device Engineering Council) specifications and include multiple memory chips, SPD EEPROM (Serial Presence Detection Programmable Read-Only Memory), series resistors, terminal resistors, capacitors, and other basic components. They also need to meet specific standard structural patterns.

[0003] In the existing standard architecture, the JEDEC specification also makes explicit requirements for the fly-by (T-topology) architecture of the CA (data, command, address lines) signal lines. This often results in complex routing, significantly impacting the performance of the corresponding memory products. JEDEC provides three stack-up styles, such as 6-layer, 8-layer, and 10-layer PCB stack-up styles, and strictly defines the size of the corresponding board outline.

[0004] However, the manufacturing cost of PCBs with 6 or more layers is usually quite high, which puts great pressure on the cost control of memory module manufacturers. Summary of the Invention

[0005] This application provides a memory, storage device, and electronic device to solve the problem that the circuit board of the memory in the prior art has too many layers, which greatly affects the performance of the memory and has a high manufacturing cost.

[0006] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a memory, wherein the memory includes: a memory module, the memory module includes a circuit board, a memory chip, and auxiliary circuits; one side of the circuit board is provided with electrical connection pins for establishing an electrical connection with the memory substrate; the memory chip and auxiliary circuits are attached to the other side of the circuit board, and the cross-sectional dimension of the circuit board is smaller than the cross-sectional dimension of the memory substrate.

[0007] The auxiliary circuit also includes a conversion chip and data command address lines. The memory chip is connected to the conversion chip through the data command address lines. The conversion chip is used to perform setting protocol conversion on the memory chip to realize the data storage capacity of at least two memory chips.

[0008] The auxiliary circuit also includes a termination circuit, which is attached to the other side of the circuit board and spaced apart from the conversion chip. It is connected to the conversion chip via data command address lines.

[0009] The auxiliary circuit also includes a termination circuit, which is embedded inside the conversion chip.

[0010] The memory chips consist of at least two stacked layers connected to each other via silicon wafer channels.

[0011] The memory module includes at least two rows of memory chips stacked on top of each other, and each row includes at least two memory chips interconnected by data, command, and address lines. The at least two rows of memory chips are interconnected by silicon wafer channels.

[0012] In this configuration, a thermally conductive material layer is attached to one side of at least two rows of stacked memory chips.

[0013] The memory module has a rectangular shape on one side, with one side measuring 40mm and the other side measuring no more than 25mm.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a storage device, wherein the storage device includes a memory as described in any of the preceding claims; the storage device also includes a memory backplane, on which the memory is mounted.

[0015] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide an electronic device, wherein the electronic device includes a processor, a connector and a card slot; the card slot is used to accommodate a storage device and to make the storage device contact the contact terminals of the connector, and to couple to the processor through the connector; wherein the storage device is the storage device as described in any of the above claims.

[0016] The beneficial effects of this application are as follows: Unlike the prior art, the memory in this application includes a memory module, and the memory module further includes a circuit board, memory chips, and auxiliary circuits; wherein, one side of the circuit board is provided with electrical connection pins for establishing an electrical connection with the memory substrate; while the memory chips and auxiliary circuits are attached to the other side of the circuit board, and the cross-sectional size of the circuit board is smaller than the cross-sectional size of the memory substrate, thereby reducing the trace length of the corresponding data command address lines that realize the electrical connection of the memory chips, thus greatly improving the overall performance of the memory; and by manufacturing the memory modules in the memory independently, the architecture of the separated memory substrate is simpler, the number of layers is fewer, and the manufacturing cost is lower. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0018] Figure 1 This is a schematic diagram of the structure of an embodiment of a memory in the prior art;

[0019] Figure 2 This is a schematic diagram of the structure of the memory in the first embodiment of this application;

[0020] Figure 3 This is a front view of the second embodiment of the memory in this application;

[0021] Figure 4 yes Figure 3 Top view of the memory;

[0022] Figure 5 This is a schematic diagram of the structure of an embodiment of the storage device of this application;

[0023] Figure 6 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] Currently, such as Figure 1 As shown, Figure 1 This is a schematic diagram of a prior art memory embodiment. Since a storage bandwidth of 64 bits is typically required in a prior art memory 10, the memory 10 will include eight 8-bit or four 16-bit DRAM (Dynamic Random Access Memory) chips 12 mounted in parallel on one side of a circuit board 11, and a termination circuit 13 mounted on one side of the circuit board 11. The circuit board 11 is used to implement preset line connections for the memory 10, and the eight memory chips 12 and the termination circuit 13 are interconnected through CA traces 14 with a defined fly-by architecture.

[0026] Obviously, circuit boards 11 with this structure usually need to be 6 / 8 / 10 layers. Due to the large number of memory chips 12, the area they occupy will also be too large, and the corresponding CA traces 14 will also be relatively long. The total length of CA traces 14 will greatly affect the overall performance of memory 10. In addition, the manufacturing cost of PCBs with more than 6 layers is usually also high, which will put great pressure on the quality and cost control of memory module manufacturers.

[0027] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of the first embodiment of the memory of this application. In this embodiment, the memory includes a memory module 20.

[0028] Specifically, the memory provided in this application is built into a personal computer, server, or laptop computer to store corresponding processed data. Of course, in other embodiments, the memory can also be used in any other reasonable electronic device that needs data storage, such as a drone or intelligent robot, and this embodiment does not limit this.

[0029] Specifically, the memory module 20 further includes a circuit board 21, a memory chip 22, and an auxiliary circuit 23. Electrical connection pins are also provided on one side of the circuit board 21 for establishing an electrical connection with the memory base plate 1.

[0030] Specifically, the memory base plate 1 refers to the external circuit board of the memory. After establishing an electrical connection between the circuit board 21 and the memory base plate 1, the memory base plate 1 enables the memory to connect to external devices and be inserted into the slots of corresponding electronic devices. The number of core board sub-layers included in the memory base plate 1 can be four. These core board sub-layers specifically refer to copper-clad laminates or other material layers that can be used to manufacture the circuit board 21. That is, by simplifying the functional integration of the memory base plate 1, the number of core board sub-layers included in the memory base plate 1 can also be reduced. Furthermore, the memory base plate 1 can always remain the same and be determined as a standard part, corresponding to the circuit characteristics and corresponding stack-up structure of different memory modules 20, thereby enabling mass production. It only needs to be specifically manufactured for different memory modules 20 and attached to the memory base plate 1. By producing the memory base plate 1 independently of the memory, the manufacturing cost of the memory can be effectively reduced, and the fewer layers of the memory base plate 1 further reduce the manufacturing cost of the corresponding storage device.

[0031] Optionally, the external dimensions of the memory base plate 1 are the same as any reasonable memory product that meets the existing JEDEC specifications, such as a standard unbuffered dual-channel memory module (UDIMM) or a standard small dual in-line memory module (SODIMM), so as to meet the connection requirements of any existing memory form. That is, the structural shape of the memory base plate 1 can match the slot of any existing electronic device with built-in memory.

[0032] Furthermore, the memory chip 22 and the auxiliary circuit 23 are mounted on the other side of the circuit board 21, and the cross-sectional dimension of the circuit board 21 is smaller than that of the memory base plate 1. This reduces the trace length of the corresponding command address lines that enable the electrical connection of the memory chip, thereby greatly improving the overall performance of the memory.

[0033] In one embodiment, the memory module 20 further includes an encapsulating colloid (not shown), which is located on the same side of the circuit board 21 where the memory chip 22 and the auxiliary circuit 23 are mounted, and covers the memory chip 22 and the auxiliary circuit 23 to protect them. In other embodiments, the circuit board 21, the memory chip 22, and the auxiliary circuit 23 may also be in the form of a PCBA (Printed Circuit Board Assembly) or an architecture with a shielding cover; this application does not limit this to any particular form.

[0034] It is understandable that by separating the memory baseboard 1, the memory module 20 can meet the signal integrity and storage function requirements of the memory, while the memory baseboard 1 can realize the function of connecting to external devices and plugging into the slots of corresponding electronic devices. This can effectively simplify the functional integration of the memory baseboard 1 and reduce the number of layers in the memory baseboard 1. Furthermore, the memory baseboard 1 and the memory module 20 can be manufactured separately, making the architecture of the memory baseboard 1 simpler, with fewer layers, and lower manufacturing costs. Since the cross-sectional size of the circuit board 21 is smaller than that of the memory baseboard 1, the trace length of the corresponding data command address lines 232 that realize the electrical connection of the memory chip 22 can also be reduced, thereby greatly improving the overall performance of the memory.

[0035] Furthermore, the auxiliary circuit 23 also includes a conversion chip 231 and a data command address line 232. The memory chip 22 is specifically connected to the conversion chip 231 through the data command address line 232. The conversion chip 231 can perform setting protocol conversion on the memory chip 22 to realize the data storage capacity of at least two memory chips 22.

[0036] It is understood that the memory chip 22 and / or the conversion chip 231 connected to the memory chip 22 via the data command address line 232 can be further connected to the memory base plate 1 via the set inner layer circuit in the circuit board 21. In this way, the memory base plate 1 can be electrically connected and / or communicated with external devices, such as the processor of an electronic device with built-in memory, and can be plugged into the corresponding slot of the electronic device through the peripheral structure of the memory base plate 1.

[0037] Furthermore, the memory chip 22 and the conversion chip 231 are disposed on the other side of the circuit board 21 at intervals, and the memory chip 22 is connected to the conversion chip 231 through the data command address line 232. The conversion chip 231 can perform a setting protocol conversion on the memory chip 22 so that it has the data storage capacity of at least two memory chips 22. That is, the conversion chip 231 can perform a setting protocol conversion on the memory chip 22, which is equivalent to at least two memory chips 22, thereby effectively reducing the number of memory chips 22 that need to be integrated in the memory module 20.

[0038] Optionally, there are two memory chips 22, which are mounted parallel to each other on the other side of the circuit board 21. They are connected to each other through data command address lines 232 and then further connected to the conversion chip 231 to cooperate with the conversion chip 231 to achieve a 64-bit storage bandwidth.

[0039] To be clear, for ease of explanation, let's take memory chip 22 as LPDDR4 (4th generation synchronous dynamic random access memory) and conversion chip 231 as LPDDR4 to DDR4 (Low Power Double Data Rate 4) as an example. Then we can see that the storage bandwidth of one of these DDR4 chips is usually 4bit, 8bit or 16bit, while the storage bandwidth of one LPDDR4 chip is 16bit, 32bit or 64bit.

[0040] In other words, when the storage bandwidth of LPDDR4 is 16 bits, each LPDDR4 is equivalent to four 4-bit DDR4s, or two 8-bit DDR4s, or one 16-bit DDR4. Therefore, four DDR4s are needed in the memory to work together with the LPDDR4 to achieve a storage bandwidth of 16 bits * 4, or 64 bits, through the protocol conversion set in the LPDDR4. When the storage bandwidth of LPDDR4 is 32 bits, two DDR4s with any storage bandwidth are needed in the memory to work together with the LPDDR4 to achieve a storage bandwidth of 64 bits.

[0041] Similarly, when the bandwidth of LPDDR4 is 64 bits, only one LPDDR4 chip with any storage bandwidth is needed in the memory to work together with the LPDDR4 conversion chip.

[0042] Understandably, the storage bandwidth of the DDR4 can be any one of 4 bits, 8 bits, and 16 bits. In other embodiments, the memory chip 22 can also be any other reasonable DRAM (Dynamic Random Access Memory) storage chip such as DDR2, DDR3, or DDR5, and the conversion chip 231 can also be any other reasonable DRAM storage chip; this application does not limit this.

[0043] Therefore, by using the conversion chip 231 to perform protocol conversion on the memory chip 22 connected to it, so that it has the data storage capacity of at least two memory chips 22, the number of memory chips 22 that need to be integrated in the memory module 20 can be effectively reduced. This reduces the area occupied by the memory chips 22 on the circuit board 21 of the memory module 20, thereby effectively reducing the cross-sectional size of the memory module 20. The corresponding data command address lines 232 are also greatly simplified and their length is reduced, thus greatly improving the overall performance of the memory.

[0044] In some specific embodiments, the number of memory chips 22 integrated in the memory is at least two, and the at least two memory chips 22 are stacked on top of each other and connected to each other through silicon wafer channels. This can further reduce the area occupied by the at least two memory chips 22 on the other side of the circuit board 21. That is, by stacking at least two memory chips 22 that are spaced parallel to each other on the other side of the circuit board 21, the thickness of the memory module 20 is increased in space, which can further reduce the cross-sectional size of the memory module 20. This greatly simplifies and reduces the length of the corresponding data command address lines 232, thereby greatly improving the overall performance of the memory.

[0045] Furthermore, the memory module 20 may include at least two memory chips 22 stacked in at least two columns, and each column may contain one or more memory chips 22. When there are multiple memory chips 22 in each column, the multiple memory chips 22 are connected to each other through data command address lines 232, so as to reduce the area occupied by at least two memory chips 22 on the other side of the circuit board 21.

[0046] The auxiliary circuit 23 also includes a termination circuit 233, which is attached to the other side of the circuit board 21 and spaced apart from the conversion chip 231. It is connected to the conversion chip 231 through the data command address line 232.

[0047] In another embodiment, the auxiliary circuit 23 further includes a termination circuit 233, which is specifically embedded inside the conversion chip 231.

[0048] Furthermore, the termination circuit 233 specifically includes a combination of one or more circuit sub-units from any reasonable functional devices such as termination resistors, decoupling capacitors, and serial presence detection circuits that are electrically connected to each other, so as to enable the memory to achieve anti-signal reflection or any other reasonable electrical function.

[0049] The size of the side of the circuit board 21 that is attached to the memory base plate 1 is smaller than the cross-sectional size of the memory base plate 1. That is, the memory module 20 only occupies a part of the area on the memory base plate 1, which can effectively simplify the circuit architecture of the corresponding data command address line 232 and reduce the length of the data command address line 232, thereby greatly improving the overall performance of the memory.

[0050] In one embodiment, the memory further includes a power conversion circuit 30, which is mounted on the memory substrate 1 and spaced apart from the circuit board 21. The power conversion circuit 30 is connected to the memory chip 22, the conversion chip 231, and the termination circuit 233 via data command address lines 232, respectively, to convert externally received power signals into appropriate voltage or current values ​​and send them to the memory chip 22, the conversion chip 231, and the termination circuit 233 accordingly. In other embodiments, the power conversion circuit 30 may be integrated inside the conversion chip 231, depending on the actual design requirements of the memory; this application does not impose any limitations on this.

[0051] Optionally, one side of the memory module 20 is rectangular, with one side of the rectangle having a dimension of 40mm and the other side having a dimension of no more than 25mm. In other embodiments, the dimension of one side of the rectangle can also be any other reasonable length such as 50mm or 60mm, and this application does not limit this.

[0052] Optionally, one side of the rectangle has a dimension of 40mm, while the other side has a dimension of not less than 10mm and not more than 25mm.

[0053] Therefore, compared to the existing standard UDIMM size of 133.35*31.25mm, the size of this memory module 20 has been greatly reduced, which in turn can shorten the corresponding CA traces, that is, the length of the data command address line 232 can reach more than 50mm, thereby greatly improving the overall performance of the memory.

[0054] Please see Figure 3 and Figure 4 ,in, Figure 3 This is a front view of the second embodiment of the memory in this application. Figure 3 yes Figure 2 Top view of the memory.

[0055] In this embodiment, the memory module 40 includes at least two rows of memory chips 42 stacked on top of each other, and each row contains at least two memory chips 42. Each pair of adjacent rows of memory chips 42 are interconnected through silicon wafer channels, and at least two memory chips 42 in each row are interconnected through data command address lines 432.

[0056] The circuit board 41 and the memory base plate 2 are the same as the circuit board 21 and the memory base plate 1, respectively. The difference between the auxiliary circuit 43 and the auxiliary circuit 23 is that the auxiliary circuit 43 does not include the conversion chip 231. Please refer to [link to details]. Figure 1 The related textual content will not be elaborated here.

[0057] Understandably, by stacking multiple memory chips 42 in the thickness direction of the memory module 40, the area occupied by multiple memory chips 42 on the circuit board 41 of the memory module 40 can be reduced, thereby effectively reducing the cross-sectional size of the memory module 40. The cross-sectional size of the circuit board 41 is smaller than that of the memory base plate 2, meaning that the memory module 40 only occupies a portion of the area on the memory base plate 2. This simplifies the circuit architecture of the corresponding data command address lines 432 and reduces their length, thus greatly improving the overall performance of the memory.

[0058] Understandably, for ease of explanation, taking the DDR4 (4th generation synchronous dynamic random access memory) memory chip 42 as an example, it can be seen that the storage bandwidth of one of these DDR4 chips is usually 4 bits, 8 bits or 16 bits.

[0059] In other words, to enable the corresponding memory to have a 64-bit memory bandwidth, when the memory bandwidth of DDR4 is 4 bits and the number of columns in which the memory stacks the DDR4 is 4, then the number of DDR4 packages in each column is 4, so that they can be stacked to achieve 4 bits * 4 * 4, which is 64 bits of memory bandwidth; while when the number of columns in which the memory stacks the DDR4 is 2, then the number of DDR4 packages in each column should be 8, to correspond to 4 bits * 2 * 8 = 64 bits of memory bandwidth.

[0060] Similarly, when the DDR4 chip bandwidth is 8 bits and the memory stacks the DDR4 in 4 columns, then the number of DDR4 chips packaged in each column is 2, corresponding to a memory bandwidth of 8 bits * 4 * 2 = 64 bits.

[0061] Similarly, when the DDR4 memory bandwidth is 16 bits, the corresponding number of DDR4 columns in the stack and the number of DDR4 cells in each column can be obtained. Other architectural combinations not listed are also possible when the DDR4 memory bandwidth is 4 bits or 8 bits, and will not be elaborated here. In other embodiments, the memory chip 42 can also be any other reasonable DRAM (Dynamic Random Access Memory) memory chip such as DDR2, DDR3, or DDR5; this application does not limit this.

[0062] The auxiliary circuit 43 also includes a termination circuit 431 and a data command address line 432. The termination circuit 431 is attached to the other side of the circuit board 41 and is spaced apart from at least two rows of memory chips 42. The data command address line 432 is connected to one of the memory chips 42 in the at least two rows of memory chips 42.

[0063] Furthermore, the termination circuit 431 specifically includes a combination of one or more circuit sub-units from any reasonable functional devices such as termination resistors, decoupling capacitors, and serial presence detection circuits that are electrically connected to each other, so as to enable the memory to achieve anti-signal reflection or any other reasonable electrical function.

[0064] In order to ensure the heat dissipation performance of the at least two rows of memory chips 42 stacked in the final product memory, a thermally conductive material layer (not shown) is attached to the other side of the at least two rows of memory chips 42 opposite to the memory base plate 31, so as to effectively improve the appearance and heat dissipation performance of the memory.

[0065] In one embodiment, the memory further includes a power conversion circuit 50, which is mounted on a circuit board 41 and spaced apart from the memory chip 42. The power conversion circuit 50 can be connected to the memory chip 42 and the termination circuit 431 via data command address lines 432 or inner layer circuits in the circuit board 41, respectively, to convert externally received power signals into appropriate voltage or current values ​​and send them to the memory chip 42 and the termination circuit 431 accordingly.

[0066] Optionally, the thermally conductive material layer is specifically one of any reasonable thermally conductive materials, such as graphene coating or thermally conductive metal sheet.

[0067] Optionally, one side of the memory module 40 is rectangular, with one side of the rectangle having a dimension of 40mm and the other side having a dimension of no more than 25mm. In other embodiments, the dimension of one side of the rectangle can also be any other reasonable length such as 50mm or 60mm, and this application does not limit this.

[0068] Optionally, one side of the rectangle has a dimension of 40mm, while the other side has a dimension of not less than 10mm and not more than 25mm.

[0069] Therefore, compared to the existing standard UDIMM size of 133.35*31.25mm, the size of this memory module 40 has been greatly reduced, which in turn can shorten the corresponding CA traces, that is, the length of the data command address line 324 can reach more than 50mm, thereby greatly improving the overall performance of the memory.

[0070] Please see Figure 5 , Figure 5 This is a schematic diagram of a storage device according to an embodiment of the present application. The storage device 60 includes a memory 61 and a memory substrate 62, and the memory 61 is mounted on the memory substrate 62.

[0071] The memory 61 is a memory as described in any of the preceding claims, and the memory substrate 62 is a memory substrate 1 or 2 as described in any of the preceding claims.

[0072] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. The electronic device 70 includes a processor 71, a connector 72, and a card slot 73.

[0073] The card slot 73 is used to accommodate the storage device and to make contact between the memory and the contact terminals of the connector 72, and to couple to the processor 71 through the connector 72.

[0074] Specifically, the storage device may be the storage device 60 described in the previous embodiment, and will not be repeated here.

[0075] Optionally, the electronic device 70 is any reasonable intelligent electronic device such as a personal computer, server, or laptop computer. Specifically, the electronic device 70 is inserted into the aforementioned memory in an embedded manner to achieve the corresponding storage function.

[0076] Unlike existing technologies, the memory in this application includes a memory module, which further includes a circuit board, memory chips, and auxiliary circuitry. One side of the circuit board has electrical connection pins for establishing an electrical connection with the memory substrate. The memory chips and auxiliary circuitry are mounted on the other side of the circuit board. The cross-sectional dimensions of the circuit board are smaller than those of the memory substrate, thereby reducing the trace length of the corresponding data command address lines for establishing the electrical connection with the memory chips, thus significantly improving the overall performance of the memory. Furthermore, by manufacturing the memory modules independently, the architecture of the separated memory substrate is simpler, with fewer layers, resulting in lower manufacturing costs.

[0077] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A memory, comprising: The memory comprises: The memory module comprises a circuit board, a memory chip and an auxiliary circuit; one side of the circuit board is provided with electrically connected pins for establishing electrical connection with a memory backplane; the memory chip and the auxiliary circuit are attached to the other side of the circuit board, and the cross-sectional dimension of the circuit board is smaller than that of the memory backplane; The auxiliary circuit comprises a conversion chip and a data command address line, and the memory chip is connected to the conversion chip through the data command address line; the conversion chip is used for setting protocol conversion of the memory chip to realize data storage capacity of at least two memory chips; the memory chip and / or the conversion chip are connected to the memory backplane through a set of inner layer lines in the circuit board.

2. The memory according to claim 1, wherein The auxiliary circuit further comprises a termination circuit, which is attached to the other side of the circuit board and is spaced apart from the conversion chip and connected to the conversion chip through the data command address line.

3. The memory according to claim 1, wherein The auxiliary circuit further comprises a termination circuit, which is embedded in the conversion chip.

4. The memory according to claim 1, wherein The number of the memory chips is at least two, and the at least two memory chips are arranged in a stack and connected to each other through a silicon channel.

5. The memory according to claim 1, wherein The memory module comprises at least two columns of memory chips arranged in a stack, and each column comprises at least two memory chips connected to each other through a data command address line, and the at least two columns of memory chips are connected to each other through a silicon channel.

6. The memory according to claim 5, wherein The other side of the at least two columns of memory chips arranged in a stack is attached with a layer of heat-conducting material.

7. The memory according to any one of claims 1-6, wherein One side of the memory module is rectangular, and one side of the rectangle has a dimension of 40 mm, and the other side has a dimension not greater than 25 mm.

8. A storage device, comprising the memory according to any one of claims 1-7. The storage device further comprises a memory backplane, and the memory is attached to the memory backplane. The electronic device comprises a processor, a connector and a card slot; 9. An electronic device, comprising: The card slot is used for accommodating the storage device, and makes the storage device contact with the contact terminals of the connector and be coupled to the processor through the connector; The storage device is the storage device according to claim 8. ​

Images