Quantum circuit compiling method and system, terminal and computer readable storage medium

Abstract

The invention discloses a quantum circuit compiling method and system, a terminal and a computer readable storage medium. The quantum circuit compiling method comprises the steps of obtaining target unitary transformation and hardware constraints; converting a unitary transformation space parameter corresponding to the target unitary transformation into a Riemannian manifold; calculating a geodesic path using a Lagrange action amount based on the Riemannian manifold and the hardware constraint; synthesizing a gate sequence of the geodesic line path; a compiling circuit with authenticated minimum depth and maximum fidelity is output based on the synthesized gate sequence. The compilation circuit obtained by the invention has circuit optimality mathematical guarantee.

Description

Technical Field

[0001] This application relates to the field of quantum computing technology, specifically to a quantum circuit compilation method and system, a terminal, and a computer-readable storage medium. Background Technology

[0002] Quantum circuit compilation is a crucial process for converting high-level quantum algorithms or logic gate sequences into low-level hardware instructions that can be executed on a specific quantum processing unit (QPU). The compilation quality directly determines the execution efficiency, reliability, and scalability of the quantum algorithm. An ideal quantum compiler should generate executable gate sequences with minimal circuit depth and maximum fidelity while satisfying hardware physical constraints.

[0003] Currently, most mainstream quantum compilers employ a heuristic search approach. The inventors have discovered that the aforementioned heuristic search-based quantum compiler schemes are prone to generating circuits with unnecessary gate overhead and error propagation, thus creating an urgent need for a compiler scheme that can provide mathematical guarantees of circuit optimality. Summary of the Invention

[0004] In view of this, this application provides a quantum circuit compilation method and system, terminal, and computer-readable storage medium, so that the resulting compiled circuit has a mathematical guarantee of circuit optimality.

[0005] This application provides a quantum circuit compilation method, which includes the following steps: Obtain the target unitary transformation and hardware constraints; Convert the unitary transform space parameters corresponding to the target unitary transform into a Riemannian manifold; The geodesic path is calculated using the Lagrange action based on the Riemannian manifold and the hardware constraints. Synthesize the gate sequence of the geodesic path; Compiler circuits with certified minimum depth and maximum fidelity based on synthesized gate sequence outputs.

[0006] Optionally, the step of calculating the geodesic path using Lagrange action based on the Riemannian manifold and the hardware constraints includes: analyzing the target circuit and determining the hardware constraints of the target circuit; constructing a manifold based on the hardware constraints and the Riemannian manifold; and calculating the geodesic path based on the result of the manifold construction.

[0007] Optionally, analyzing the target circuit and determining its hardware constraints includes: decomposing the target circuit to extract multiple circuit features; calculating theoretical lower bounds based on each circuit feature to obtain a structured target description; establishing a physical quantum bit connection graph based on the structured target description; listing available native gates based on the physical quantum bit connection graph; and performing constraint quantization on the available native gates to obtain the hardware constraints.

[0008] Optionally, the manifold construction based on the hardware constraints and the Riemannian manifold includes: extracting generators from the available native gates; and constructing a constrained manifold based on the generators and the hardware constraints.

[0009] Optionally, calculating the geodesic path based on the results of the popular construction includes: setting boundary conditions based on the results of the popular construction; setting initial values ​​using linear interpolation; and executing a geodesic solving algorithm based on the initial values ​​to obtain the geodesic path.

[0010] Optionally, the geodesic solution algorithm includes: determining the Lagrange action; performing variational derivation on the Lagrange action to obtain the Euler-Lagrange equation; performing iterative solution based on the Euler-Lagrange equation; and determining the geodesic path when the solution result satisfies the convergence condition.

[0011] Optionally, the Lagrange action includes terms for gate fidelity, decoherence effect, and hardware-specific error rate.

[0012] This application also provides a quantum circuit compilation system, including: The acquisition module is used to acquire the target unitary transformation and hardware constraints; The conversion module is used to convert the unitary transform space parameters corresponding to the target unitary transform into a Riemannian manifold; The calculation module is used to calculate the geodesic path using Lagrange action based on the Riemannian manifold and the hardware constraints; A synthesis module is used to synthesize the gate sequence of the geodesic path; Output module for outputting compiled circuits with certified minimum depth and maximum fidelity based on synthesized gate sequences.

[0013] This application also provides a terminal, including: a memory and a processor, wherein the memory stores a quantum circuit compiler, and when the quantum circuit compiler is executed by the processor, it implements the steps of any of the above quantum circuit compilation methods.

[0014] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the above quantum circuit compilation methods.

[0015] The quantum circuit compilation method, system, terminal, and computer-readable storage medium described in this application acquire the target unitary transform and hardware constraints, convert the unitary transform space parameters corresponding to the target unitary transform into a Riemannian manifold, thereby mapping the compilation problem to a path optimization problem on the Riemannian manifold. Then, based on the Riemannian manifold and the hardware constraints, the geodesic path is calculated using the Lagrange action, and the gate sequence of the geodesic path is synthesized, thereby outputting a compiled circuit with certified minimum depth and maximum fidelity, so that the obtained compiled circuit has a mathematical guarantee of circuit optimality. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic flowchart of a quantum circuit compilation method according to an embodiment of this application; Figure 2 This is a schematic diagram of a Lagrange-optimized quantum compiler system architecture according to an embodiment of this application; Figure 3 This is a schematic diagram of a unitary manifold optimization structure according to an embodiment of this application; Figure 4 This is a schematic diagram of the computation process for minimizing the scope of an embodiment of this application; Figure 5 This is a schematic diagram of an adaptive compilation framework according to an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a quantum circuit compilation system according to an embodiment of this application; Figure 7 This is a schematic diagram of a terminal structure according to an embodiment of this application. Detailed Implementation

[0018] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0019] The first aspect of this application provides a quantum circuit compilation method, which can be executed by a terminal that needs to compile quantum circuits.

[0020] Specifically, refer to Figure 1As shown, the quantum circuit compilation method includes the following steps S110 to S150.

[0021] S110, obtain the target unitary transformation and hardware constraints.

[0022] Optionally, the target unitary transform may include the unitary transform corresponding to the target circuit, and the hardware constraints may include the constraints corresponding to the target circuit. Optionally, step S110 above may parse the target circuit and / or the quantum circuit description corresponding to the target circuit, converting it into an accurate unitary matrix representation to obtain the target unitary transform. Optionally, step S110 above may extract information such as the topology connection graph, native gate set, gate duration, and / or error rate parameters from the hardware configuration file of the target circuit to obtain the hardware constraints.

[0023] S120, the unitary transformation space parameters corresponding to the target unitary transformation are converted into a Riemannian manifold, so as to map the compilation problem into a path optimization problem on the Riemannian manifold.

[0024] Step S120 above can determine the unitary manifold based on the unitary transform space parameters. The unitary manifold is a differentiable manifold, which is a continuous parameterized space of the compiler circuit. Each compiler circuit corresponds to a discrete point on the manifold, and the entire manifold contains all possible hardware implementation schemes. Specifically, it contains the set of native hardware gates. The tangent space basis vectors of the manifold are defined, and the hardware connectivity constraints are constructed through the quotient space. Encoding into manifold geometry, target circuit It can correspond to a target point on the manifold.

[0025] Optionally, the above steps can employ a Lagrange-optimized quantum compiler system architecture. (See reference) Figure 2 As shown, the Lagrange optimization core 104 includes unitary manifold parameterization 105, geodesic path solver 106, and circuit depth verification unit 107. The unitary manifold parameterization 105 can construct differentiable manifolds representing all possible unitary transformations; the geodesic path solver 106 can use variational principles to calculate the minimum action path between computational states; and the circuit depth verification unit 107 can verify that the compiled circuit reaches the theoretical minimum depth limit.

[0026] Optionally, Figure 3 The optimal structure of the unitary manifold is shown, such as Figure 3 As shown, the unitary manifold optimization structure includes Riemannian geometric representation 301, variational path optimization 302, and depth-optimal guarantee 303.

[0027] S130, the geodesic path is calculated using Lagrange action based on the Riemannian manifold and the hardware constraints. The geodesic path calculation can employ variational principles to find the minimum action trajectory through the unitary transformed manifold.

[0028] Specifically, the calculation process for the above geodesic path can be found by referring to... Figure 4 As shown, Figure 4 The compilation process for minimizing the action is explained, which may include processes such as target circuit analysis 201, hardware constraint definition 202, manifold construction 203, and geodesic calculation 204.

[0029] Specifically, the Lagrange action may include terms for gate fidelity, decoherence effect, and hardware-specific error rate.

[0030] S140, synthesize the gate sequence of the geodesic path. For example, step S140 can discretize the geodesic path to obtain the hardware native gate sequence corresponding to the target circuit.

[0031] S150 is a compiler circuit based on the output of a synthesized gate sequence that has certified minimum depth and maximum fidelity, so that the compiler circuit has mathematical guarantees of circuit optimality.

[0032] The above steps can be based on Figure 5 The hardware adaptive compilation framework shown is as follows: Figure 5 As shown, the hardware adaptive compilation framework includes cross-platform compilation 401, adaptive deep optimization 402, and performance guarantee 403.

[0033] The aforementioned quantum circuit compilation method, by acquiring the target unitary transform and hardware constraints, converts the unitary transform space parameters corresponding to the target unitary transform into a Riemannian manifold, thus mapping the compilation problem to a path optimization problem on the Riemannian manifold. Then, based on the Riemannian manifold and the hardware constraints, it uses the Lagrangian action to calculate the geodesic path, synthesizes the gate sequence of the geodesic path, and outputs a compiled circuit with certified minimum depth and maximum fidelity, so that the obtained compiled circuit has a mathematical guarantee of circuit optimality.

[0034] In some embodiments, the step of calculating the geodesic path using Lagrange action based on the Riemannian manifold and the hardware constraints includes: analyzing the target circuit and determining the hardware constraints of the target circuit; constructing a manifold based on the hardware constraints and the Riemannian manifold; and calculating the geodesic path based on the result of the manifold construction.

[0035] In some examples, analyzing the target circuit and determining its hardware constraints includes: decomposing the target circuit to extract multiple circuit features; calculating theoretical lower bounds based on each of the circuit features to obtain a structured target description; establishing a physical qubit connection graph based on the structured target description; listing available native gates based on the physical qubit connection graph; and constraining the available native gates to obtain hardware constraints.

[0036] Optionally, the above-described decomposition of the target circuit to extract multiple circuit features includes: decomposing the target circuit into basic unitary operations to obtain a unitary matrix. Extract the circuit width from it. (Number of qubits), logic depth Circuit characteristics such as special structure identification. Theoretical lower bound. It can be: Structured target descriptions include .

[0037] Optionally, the process of determining hardware constraints includes: (1) Topological mapping: establishing a physical quantum bit connection graph. (2) List the available native gates. (3) Constraint quantization: Determining the constraints on parallelism. Determine the time for re-correlation: Perform measurement configuration to output the configuration file corresponding to the hardware constraints. .

[0038] In some examples, the manifold construction based on the hardware constraints and the Riemannian manifold includes: extracting generators from the available native gates; and constructing a constrained manifold based on the generators and the hardware constraints.

[0039] Alternatively, this example can be generated from available native gates. Extracting native gate generators Next, define the parameter space. Then, construct the corresponding manifold with constraints. .

[0040] Alternatively, this example can also define a Riemann metric based on gate fidelity, and the formula for determining the Riemann metric includes: ,in Represents the Riemannian metric. Indicates the average gate fidelity. express One of the variables, express Another variable in the process.

[0041] Optionally, this example can also test and verify the above features. The testing and verification process includes: (1) Completeness test: verifying the unitary matrix corresponding to any target circuit. (2) Reachability test: Confirm the existence of continuous paths in the relevant identity transformations. (3) Accuracy verification: Calculate the approximation error. To verify the corresponding accuracy.

[0042] In some examples, calculating the geodesic path based on the results of popular constructions includes: setting boundary conditions based on the results of popular constructions; setting initial values ​​(i.e., initial paths) using linear interpolation; executing a geodesic solving algorithm based on the initial values ​​to obtain an optimal path; and determining the geodesic path based on the optimal path.

[0043] Optionally, the process of setting initial values ​​using linear interpolation includes: , This represents the initial value (i.e., the initial path). Represents a time variable. This indicates an estimated value.

[0044] In some examples, the geodesic solution algorithm includes: determining the Lagrange action; performing variational derivation on the Lagrange action to obtain the Euler-Lagrange equation; performing iterative solution based on the Euler-Lagrange equation; and determining the geodesic path when the solution result satisfies the convergence condition.

[0045] Alternatively, this example can first define the initial action as a functional and then extract the Lagrange action.

[0046] Taking variation with respect to the Lagrange action or the initial action This yields the Euler-Lagrange equations: Alternatively, Christofel notation can be used to simplify the Euler-Lagrange equations described above.

[0047] Alternatively, this example can use a symplectic integrator to iteratively solve the Euler-Lagrange equations, for example, using the Störmer-Verlet scheme.

[0048] In some examples, the feasibility of the optimal geodesic path can be verified and certified to generate a corresponding certification report.

[0049] Optionally, verifying practical feasibility includes: extracting the path depth; determining the minimum step size; and calculating the theoretical minimum depth based on the path depth and the minimum step size.

[0050] Minimum step size The calculation formulas include: ,in Indicates the shortest gate time. Indicates the maximum gate speed. This indicates taking the maximum value.

[0051] Theoretical minimum depth The calculation formulas include: .

[0052] Alternatively, this example can also analyze the target circuit using methods such as gate sequence discretization and deep computation. Gate sequence discretization includes dividing continuous paths... Discretized The depth calculation can take into account the actual depth after parallelization, and the actual depth is determined based on the maximum number of gates in the corresponding layer.

[0053] Optionally, the authentication criteria include simultaneously satisfying authentication conditions such as depth optimality, fidelity requirements, and feasibility constraints. Depth optimality includes: ,in This indicates the second preset tolerance. Indicates the theoretical minimum depth. This represents the actual minimum depth. Fidelity requirements include: , This indicates the second preset tolerance. This indicates fidelity. All hardware constraints are met.

[0054] Optionally, the certification may include a certification result of passing or failing, and may also include optimization ratios, fidelity data, and / or improvement suggestions. The optimization ratio is one such example. include: Improvement suggestions may include: if the test fails, indicating the type of constraint violated.

[0055] The above quantum circuit compilation method, through tight coupling of its various steps, transforms the abstract quantum circuit compilation problem into a concrete geometric optimization problem, ultimately outputting an executable quantum circuit with theoretical optimality guarantees. This method has significant value both theoretically and practically. Specifically, it uses the Lagrange optimization principle to compile a system and method for quantum circuits that guarantee minimum depth and maximum fidelity. Quantum compilation is formulated as an action minimization problem on a unitary manifold, where circuit synthesis follows geodesic paths between computational states. This produces compiled circuits with mathematically proven optimal gate sequences, significantly reducing circuit depth and error accumulation compared to traditional compilation methods.

[0056] A second aspect of this application provides a quantum circuit compilation system, which can be installed at the terminal where quantum circuit compilation is required. (Reference) Figure 6 As shown, the above-mentioned quantum circuit compilation system includes: Module 110 is used to acquire the target unitary transformation and hardware constraints; The conversion module 120 is used to convert the unitary transform space parameters corresponding to the target unitary transform into a Riemannian manifold; Calculation module 130 is used to calculate geodesic paths using Lagrange actions based on the Riemannian manifold and the hardware constraints; Synthesis module 140 is used to synthesize the gate sequence of the geodesic path; Output module 150 is used to output a compiler circuit with certified minimum depth and maximum fidelity based on the synthesized gate sequence.

[0057] Specific limitations regarding the quantum circuit compilation system can be found in the limitations of the quantum circuit compilation method described above, and will not be repeated here. Each module in the aforementioned quantum circuit compilation system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independent of the computation modules in the relevant computer device, or stored in software in the memory of the computer device, so that the computation modules can call and execute the operations corresponding to each of the above units.

[0058] This application also provides a terminal, for reference. Figure 7 As shown, the terminal may include: a memory and a processor, wherein the memory stores a quantum circuit compiler, and when the quantum circuit compiler is executed by the processor, it implements the steps of the quantum circuit compilation method as described in any of the above embodiments.

[0059] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the quantum circuit compilation method as described in any of the above embodiments.

[0060] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0061] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0062] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0063] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A quantum circuit compilation method, characterized in that, The quantum circuit compilation method includes: Obtain the target unitary transformation and hardware constraints; Convert the unitary transform space parameters corresponding to the target unitary transform into a Riemannian manifold; The geodesic path is calculated using the Lagrange action based on the Riemannian manifold and the hardware constraints. Synthesize the gate sequence of the geodesic path; Compiler circuits with certified minimum depth and maximum fidelity based on synthesized gate sequence outputs.

2. The quantum circuit compilation method according to claim 1, characterized in that, The calculation of geodesic paths using Lagrange actions based on the Riemannian manifold and the hardware constraints includes: Analyze the target circuit and determine its hardware constraints; Population construction is performed based on the hardware constraints and the Riemannian manifold; The geodesic path is calculated based on the results of popular construction.

3. The quantum circuit compilation method according to claim 2, characterized in that, The analysis of the target circuit, and the determination of the hardware constraints of the target circuit, include: The target circuit is decomposed to extract multiple circuit features; The theoretical lower bound is calculated based on the characteristics of each circuit to obtain a structured target description; A physical quantum bit connection diagram is established based on the structured target description; List the available native gates based on the physical qubit connection diagram; The available native gates are constrained and quantized to obtain the hardware constraints.

4. The quantum circuit compilation method according to claim 3, characterized in that, The process of constructing manifolds based on the hardware constraints and the Riemannian manifold includes: Extract generators from the available native gates; Constrained manifold construction is performed based on the generator and the hardware constraints.

5. The quantum circuit compilation method according to claim 4, characterized in that, The calculation of the geodesic path based on the results of popular construction includes: Set boundary conditions based on the results of popular constructions; Use linear interpolation to set the initial values; Based on the initial values, a geodesic solution algorithm is executed to obtain the geodesic path.

6. The quantum circuit compilation method according to claim 5, characterized in that, The geodesic solution algorithm includes: Determine the Lagrange action; Variational derivation of the Lagrange action yields the Euler-Lagrange equation; The geodesic path is determined by iteratively solving the Euler-Lagrange equations and when the solution meets the convergence condition.

7. The quantum circuit compilation method according to claim 1, characterized in that, The Lagrange action includes terms for gate fidelity, decoherence effect, and hardware-specific error rate.

8. A quantum circuit compilation system, characterized in that, include: The acquisition module is used to acquire the target unitary transformation and hardware constraints; The conversion module is used to convert the unitary transform space parameters corresponding to the target unitary transform into a Riemannian manifold; The calculation module is used to calculate the geodesic path using Lagrange action based on the Riemannian manifold and the hardware constraints; A synthesis module is used to synthesize the gate sequence of the geodesic path; Output module for outputting compiled circuits with certified minimum depth and maximum fidelity based on synthesized gate sequences.

9. A terminal, characterized in that, The terminal includes a memory and a processor, wherein the memory stores a quantum circuit compiler, and when the quantum circuit compiler is executed by the processor, it implements the steps of the quantum circuit compilation method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the quantum circuit compilation method as described in any one of claims 1 to 7.

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