A memory chip substrate layout structure and a wiring method thereof

Abstract

The application discloses a kind of memory chip substrate layout structure and its wiring method, it is related to semiconductor packaging technical field;Including board material, the substrate adopts two-layer board material, and one side of board material is fixedly connected with top layer and bot layer, and core block area is fixedly connected inside top layer and bot layer, LPDDR chip area is fixedly connected above the board material, main control chip area and NAND Flash chip area are fixedly connected above LPDDR chip area, a large number of signal line areas and a small amount of power supply one and power supply two are fixedly connected inside top layer, and its layout wiring method includes deleting redundant layer, retaining top layer and bot layer, moving NAND Flash chip area and LPDDR chip area, placing main control chip area above LPDDR chip area, so that main control chip area and NAND Flash chip area are in the same horizontal plane multiple steps;With chip is reduced to two-layer board from four-layer board, the complexity of chip substrate is reduced, process flow is simplified, production cost is saved, production loss is reduced, so that the advantages that ultra-thin product can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a storage chip substrate layout structure and a wiring method thereof. BACKGROUND

[0002] Electronic devices are widely used in daily life, from computers to chargers, mobile phones to hybrid electric vehicles, and even satellites. These electronic devices are filled with a large number of various chips, and the proportion of storage chips in these chips is as high as more than 30%.

[0003] At present, in the field of mobile electronic devices, the storage scheme mainly adopts eMCP (embedded Multichip Packaging) / ePoP (embedded Package on Package) chips or separate design chip combinations, including eMMC (embedded Multimedia Card) chips and LPDDR (Low Power Double Data Rate SDRAM) chips. Among them, eMCP and ePoP have high integration and can be used as ultra-thin products, and are widely used in various wearable devices and mobile communication devices.

[0004] The existing substrate design scheme of eMCP / ePoP chip is generally a 4-layer board, and its stack design and signal and power planning are as follows:

[0005] TOP Signal high-speed signal line signal line

[0006] M2 GND ground

[0007] M3 Power power supply

[0008] BOT Signal signal line

[0009] Among them, the Top layer runs the main and high-speed signal line, the Bot layer runs the secondary signal line, the second layer is a complete ground plane layer, and the third layer is composed of different power plane blocks. Under the current situation that the cost of various electronic devices and chips is more and more sensitive, this over-design of the remaining space causes high cost, and the space is redundant, which is not conducive to improving the market competitiveness of the product.

[0010] At the same time, with the trend of miniaturization, lightness and high density of electronic devices, there are relatively strict requirements on the overall thickness of the chip. The existing layout and wiring scheme has a large number of substrate layers and low utilization, resulting in a large overall thickness of the chip, which cannot meet the needs of light and thin or even ultra-thin products.

[0011] In view of the above phenomenon and problems, the application provides a chip substrate layout design method, which can effectively reduce the cost to a large extent, greatly reduce the thickness of the chip, and realize the invention of an ultra-thin product. SUMMARY

[0012] The application aims to solve the problems in the prior art and provides a memory chip substrate layout structure and a wiring method thereof.

[0013] To achieve the above-mentioned purpose, the application adopts the following technical solutions:

[0014] A memory chip substrate layout structure comprises a plate material, the substrate adopts two layers of plate materials, one side of the plate material is fixedly connected with a top layer and a bot layer, and the inside of the top layer and the bot layer is fixedly connected with a core block area.

[0015] Preferably, the plate material is fixedly connected with an LPDDR chip area above, and the LPDDR chip area is fixedly connected with a master control chip area and a NAND Flash chip area above.

[0016] Further, the inside of the top layer is fixedly connected with a large number of signal line areas and a small number of power supply one and power supply two.

[0017] Further, the inside of the bot layer is fixedly connected with a small number of signal line areas and a large number of power supply one and power supply two.

[0018] As a preferred scheme of the application, the master control chip area and the NAND Flash chip area are fixedly connected with gold wires on one side.

[0019] A memory chip substrate layout wiring method comprises the following steps:

[0020] S1: deleting redundant layers and retaining the top layer and the bot layer;

[0021] S2: moving the NAND Flash chip area and the LPDDR chip area, placing the master control chip area above the LPDDR chip area, and making the master control chip area and the NAND Flash chip area be in the same horizontal plane;

[0022] S3: connecting part of the pads of the master control chip area and the corresponding network pads of the NAND Flash chip area through gold wires;

[0023] S4: wiring the power supply network through the top layer and the bot layer;

[0024] S5: wiring the remaining space area of the top layer and the bot layer and filling the network;

[0025] S6: Check the connection of all signals and power ground network, complete the substrate design.

[0026] As a further scheme of the present application: the overall thickness of the chip is 0.8mm.

[0027] The present application has the following advantages:

[0028] 1. A memory chip substrate layout structure and its wiring method, which has the advantages of reducing the complexity of the chip substrate, simplifying the process flow, saving the production cost, reducing the production loss, and enabling the realization of ultra-thin products by reducing the chip from four layers to two layers.

[0029] 2. A memory chip substrate layout structure and its wiring method, which saves the wiring space of the signal lines on the substrate by directly connecting the master chip area to the NAND Flash chip area through gold wires.

[0030] 3. A memory chip substrate layout structure and its wiring method, which improves the efficiency and yield of substrate design and manufacturing, simplifies the process flow, reduces the chip thickness, improves the market competitiveness of the product, and takes into account the signal integrity and power integrity of the chip.

[0031] 4. A memory chip substrate layout structure and its wiring method, which increases the density of layout and wiring by fully utilizing the substrate space, and ensures the realization of high-speed reading and writing functions.

[0032] 5. A memory chip substrate layout structure and its wiring method, which reduces the substrate layer number, reduces the chip substrate development time by 30-50%, and reduces the cost by 30-50%. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a cross-sectional structure schematic diagram of the memory chip substrate layout structure and its wiring method proposed by the present application;

[0034] Figure 2 is a layout and wiring structure schematic diagram of the memory chip substrate layout structure and its wiring method proposed by the present application;

[0035] Figure 3 is a gold wire side view structure schematic diagram of the memory chip substrate layout structure and its wiring method proposed by the present application.

[0036] In the figure: 1, board material; 2, top layer; 3, bot layer; 4, core block area; 5, master chip area; 6, power supply one; 7, NAND Flash chip area; 8, LPDDR chip area; 9, signal line area; 10, power supply two; 11, gold wire. DETAILED DESCRIPTION

[0037] The technical solutions of the patent will be further described in detail in combination with the specific embodiments.

[0038] The embodiments of the patent are described in detail below, and examples of the embodiments are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the patent, and cannot be understood as a limitation of the patent.

[0039] In the description of the patent, it should be understood that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the patent and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the patent.

[0040] In the description of the patent, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "setting" should be understood broadly, for example, it can be fixedly connected, set, or detachably connected, set, or integrally connected, set. For those skilled in the art, the specific meanings of the above terms in the patent can be understood according to the specific circumstances.

[0041] Embodiment 1:

[0042] A storage chip substrate layout structure comprises a board material 1, the substrate adopts two layers of board materials 1, one side of the board material 1 is fixedly connected with a top layer 2 and a bot layer 3, the inside of the top layer 2 and the bot layer 3 both contain copper, the inside of the top layer 2 and the bot layer 3 are fixedly connected with a core block area 4, the second and third layers of the original four-layer board are laid in the form of the core block area 4 to the top layer 2 and the bot layer 3, and the wiring layout planning of each stack and signal power ground is as follows:

[0043] TOP Signal / GND / Power signal line / power / ground;

[0044] BOT Signal / GND / Power signal line / power / ground;

[0045] The board material 1 is fixedly connected with an LPDDR chip area 8 above, and a master control chip area 5 and a NAND Flash chip area 7 are fixedly connected above the LPDDR chip area 8;

[0046] The top layer 2 is internally fixedly connected with a large number of signal line areas 9 and a small number of power supply one 6 and power supply two 10, and the remaining part is paved with a ground block for isolation shielding;

[0047] The bot layer 3 is internally fixedly connected with a small number of signal line areas 9 and a large number of power supply one 6 and power supply two 10, so that the power supply network is completely connected, and the remaining part is completely paved with a ground plane;

[0048] The structure can be used not only for eMCP and ePoP chips, but also for other four-layer substrates or three-layer substrate type storage chips such as eMMC, eSSD, etc., reduces from four-layer boards to two-layer boards, reduces the complexity and process flow of the chip substrate, saves costs and reduces losses, and reduces the thickness of the chip substrate from 150-200um of the four-layer board to 80-100um of the two-layer board;

[0049] The overall thickness of the chip product can be reduced from 1.2mm to 0.8mm, meeting the requirements of ultra-thin chip products.

[0050] Embodiment 2

[0051] A layout and wiring method of a storage chip substrate layout structure, comprising the following steps:

[0052] S1: deleting the redundant M2 layer ground layer and M3 layer power supply layer in the original four-layer board structure, and retaining the first layer top layer 2 and the last layer bot layer 3;

[0053] S2: referencing a new structure, changing the existing layout structure, moving the NAND Flash chip area 7 and the LPDDR chip area 8, and placing the master control chip area 5 above the LPDDR chip area 8, so that the master control chip area 5 and the NAND Flash chip area 7 are on the same horizontal plane;

[0054] S3: connecting part of the pads of the master control chip area 5 and the corresponding network pads of the NAND Flash chip area 7 through gold wires 11, the gold wires 11 being processed through a Bonding process, the pads being pins for chip output and input, being packaged in the chip, and directly connecting the master control chip area 5 and the NAND Flash chip area 7 through the gold wires 11, without connecting through the internal wiring of the substrate, directly saving the wiring space of the substrate and reducing the number of substrate layers;

[0055] S4: wiring the power supply network on the top layer 2 and the bot layer 3, while considering the power supply integrity problem;

[0056] S5: wiring the remaining space area of the top layer 2 and the bot layer 3, and paving the ground network;

[0057] S6: check the connection of all signals and power ground network, and take into account the signal and power integrity, complete the substrate design;

[0058] In the embodiment, the substrate space is fully utilized, the density of layout and wiring is increased, the substrate layer number is reduced, the chip substrate development time is reduced by 30-50%, and the cost is reduced by 30-50%;

[0059] Compared with the four-layer board, the two-layer board improves the efficiency and yield of substrate design and manufacturing, simplifies the process flow, reduces the chip thickness, improves the market competitiveness of the product, and takes into account the signal integrity and power integrity of the chip;

[0060] The mode of directly connecting the main control chip area 5 to the NAND Flash chip area 7 through the gold wire 11 saves the signal line wiring space on the substrate, and improves the electrical performance.

[0061] The above describes the preferred specific embodiment of the application, the protection scope of the application is not limited to this, any skilled person in the art combines the prior art or public common sense within the technical range disclosed by the application, any modification, equivalent replacement and improvement within the spirit and principle of the application, etc. should be covered within the protection scope of the application.

Claims

1. A layout routing method of a layout structure of a memory chip substrate, characterized by, It comprises the following steps: S1: delete the original 4-layer board structure in the M2 layer formation and M3 layer power layer, keep the first layer top layer (2) and the last layer bot layer (3); S2: move the NAND Flash chip area (7) and LPDDR chip area (8), place the master control chip area (5) above the LPDDR chip area (8), so that the master control chip area (5) and the NAND Flash chip area (7) are in the same horizontal plane; S3: connect part of the pad of the master control chip area (5) and the corresponding network pad of the NAND Flash chip area (7) through the gold wire (11); directly connect the master control chip area (5) and the NAND Flash chip area (7) through the gold wire (11); S4: wire the power network through the top layer (2) and the bot layer (3); S5: wire the remaining space area of the top layer (2) and the bot layer (3), and fill the ground network; S6: check the connection of all signal and power ground networks, and complete the substrate design.

2. The storage chip substrate layout structure prepared by the layout routing method of claim 1, wherein, The substrate adopts upper and lower two layers of board materials (1), one side of the board material (1) is fixedly connected with the top layer (2) and the bot layer (3), and the inside of the top layer (2) and the bot layer (3) is fixedly connected with the core block area (4).

3. The memory chip substrate layout structure according to claim 2, wherein The upper side of the board material (1) is fixedly connected with the LPDDR chip area (8), and the upper side of the LPDDR chip area (8) is fixedly connected with the master control chip area (5) and the NAND Flash chip area (7).

4. The memory chip substrate layout structure according to claim 3, wherein The inside of the top layer (2) is fixedly connected with a large number of signal line areas (9) and a small number of power supply one (6) and power supply two (10).

5. The memory chip substrate layout structure according to claim 3, wherein The inside of the bot layer (3) is fixedly connected with a small number of signal line areas (9) and a large number of power supply one (6) and power supply two (10).

6. The memory chip substrate layout structure according to claim 3, wherein The one side of the master control chip area (5) and the NAND Flash chip area (7) is fixedly connected with the gold wire (11).

Images