Solid state disk channel signal adjusting system and solid state disk

Abstract

The application provides a solid state disk channel signal adjusting system and a solid state disk, and the system further comprises a master control chip, a memory chip, a real-time monitoring module and a timing adjusting module, wherein: the real-time monitoring module is used for monitoring a read operation error rate corresponding to the flash memory chip in real time, and when the read operation error rate is greater than a preset threshold, working environment parameters of DQS signals and DQ signals are obtained and transmitted to the master control chip; the master control chip is used for obtaining timing adjusting signals of the DQS signals and the DQ signals corresponding to the flash memory chip according to the working environment parameters and transmitting the timing adjusting signals to the timing adjusting module; wherein, the timing adjusting signals are used for realizing alignment of the DQS signals and the DQ signals corresponding to the flash memory chip; and the timing adjusting module adjusts the timing of the DQS signals and the DQ signals corresponding to the flash memory chip according to the timing adjusting signals. The solid state disk channel signal adjusting system and the solid state disk provided by the application realize self-adaptive optimization adjustment of solid state disk channel signals, can adapt to complex and changeable working environments, and significantly improve the read performance and data transmission rate of the solid state disk.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive (SSD) technology, and more particularly to an SSD channel signal adjustment system and an SSD. Background Technology

[0002] With the rapid development of modern computer technology, solid-state drives (SSDs) have become the mainstream choice for storage devices. Compared to traditional hard disk drives (HDDs), SSDs offer higher read speeds, lower power consumption, and better shock resistance. However, with increasing storage density and data transfer rates, SSDs face numerous challenges in signal transmission and data retrieval. Current SSD signal optimization technologies mainly rely on fixed parameter settings and simple feedback control, making it difficult to adapt to complex and changing working environments. Summary of the Invention

[0003] This invention provides a solid-state drive (SSD) channel signal adjustment system and a SSD, which addresses the shortcomings of existing SSD signal optimization technologies that rely mainly on fixed parameter settings and simple feedback control, making it difficult to adapt to complex and changing working environments. The system enables adaptive optimization and adjustment of SSD channel signals, adapting to complex and changing working environments and improving the read performance and data transfer rate of the SSD.

[0004] This invention provides a solid-state drive (SSD) channel signal adjustment system. The system includes a main control chip and at least one flash memory chip. A channel for transmitting DQS and DQ signals exists between the main control chip and the flash memory chip. The system further includes a real-time monitoring module and a timing adjustment module. The real-time monitoring module monitors the read operation error rate corresponding to the flash memory chip in real time. When the read operation error rate exceeds a preset threshold, it acquires the operating environment parameters of the DQS and DQ signals and transmits these parameters to the main control chip. The main control chip obtains timing adjustment signals for the DQS and DQ signals corresponding to the flash memory chip based on the operating environment parameters and transmits these signals to the timing adjustment module. The timing adjustment signals are used to align the DQS and DQ signals corresponding to the flash memory chip. The timing adjustment module receives the timing adjustment signals and adjusts the timing of the DQS and DQ signals corresponding to the flash memory chip based on these signals.

[0005] According to the present invention, a solid-state drive channel signal adjustment system is provided, wherein the operating environment parameters include at least one of voltage, temperature and operating frequency.

[0006] According to the present invention, a solid-state drive channel signal adjustment system further includes a voltage adjustment module; the real-time monitoring module is further configured to acquire signal quality parameters of the DQS signal and the DQ signal when the read operation error rate corresponding to the flash memory chip is greater than the preset threshold, and transmit the signal quality parameters to the main control chip; the main control chip is further configured to obtain voltage adjustment signals of the DQS signal and the DQ signal corresponding to the flash memory chip according to the signal quality parameters, and transmit the voltage adjustment signals to the voltage adjustment module; the voltage adjustment module is configured to receive the voltage adjustment signals and adjust the voltages of the DQS signal and the DQ signal corresponding to the flash memory chip according to the voltage adjustment signals.

[0007] According to a solid-state drive channel signal adjustment system provided by the present invention, the signal quality parameter includes signal strength; when the main control chip obtains the voltage adjustment signals of the DQS signal and the DQ signal corresponding to the flash memory chip based on the signal quality parameter, it is specifically used to: in response to the signal strength of the DQS signal and the DQ signal corresponding to the flash memory chip being lower than a preset signal strength, generate a voltage adjustment signal for increasing the voltage of the DQS signal and the DQ signal.

[0008] According to a solid-state drive channel signal adjustment system provided by the present invention, the signal quality parameters include noise level; when the main control chip obtains the voltage adjustment signals of the DQS signal and the DQ signal corresponding to the flash memory chip based on the signal quality parameters, it is specifically used to: in response to the noise level of the DQS signal and the DQ signal corresponding to the flash memory chip being higher than a preset noise level, generate a voltage adjustment signal for increasing the voltage of the DQS signal and the DQ signal.

[0009] According to a solid-state drive channel signal adjustment system provided by the present invention, the main control chip is further configured to: initialize and set the parameters of the DQS signal and the DQ signal when the solid-state drive is powered on, and write data of a preset size to the flash memory chip.

[0010] According to the solid-state drive channel signal adjustment system provided by the present invention, the real-time monitoring module is further configured to: read the preset size of data written by the flash memory chip after the solid-state drive reaches a preset frequency, and calculate the read operation error rate.

[0011] According to a solid-state drive channel signal adjustment system provided by the present invention, the real-time monitoring module is further configured to: acquire the flash memory chip that first achieves a read operation error rate lower than a preset threshold after the solid-state drive is powered on, and transmit the information of the flash memory chip to the main control chip; the main control chip is further configured to configure the parameters of the DQS signal and the DQ signal of other flash memory chips according to the parameters of the DQS signal and the DQ signal of the flash memory chip.

[0012] According to the present invention, a solid-state drive channel signal adjustment system is provided, wherein the parameters of the DQS signal and the DQ signal include the DQ write clock and the delay of the DQS read direction.

[0013] The present invention also provides a solid-state drive, including any of the solid-state drive channel signal adjustment systems described above.

[0014] The solid-state drive (SSD) channel signal adjustment system and SSD provided by this invention, by setting up a real-time monitoring module and a timing adjustment module, enables the real-time monitoring of the read operation error rate corresponding to the flash memory chip. When the read operation error rate exceeds a preset threshold, the system acquires the operating environment parameters of the DQS and DQ signals and transmits these parameters to the main control chip. The main control chip obtains the timing adjustment signals of the DQS and DQ signals corresponding to the flash memory chip based on the operating environment parameters and transmits these signals to the timing adjustment module. The timing adjustment module receives the timing adjustment signals and adjusts the timing of the DQS and DQ signals corresponding to the flash memory chip according to the timing adjustment signals. This achieves adaptive optimization adjustment of the SSD channel signals, enabling it to adapt to complex and changing working environments and significantly improving the read performance and data transfer rate of the SSD. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is one of the structural schematic diagrams of the solid-state drive channel signal adjustment system provided by the present invention.

[0017] Figure 2 This is the second schematic diagram of the solid-state drive channel signal adjustment system provided by the present invention.

[0018] Figure 3 This is a schematic diagram of the processing flow of the solid-state drive channel signal adjustment system provided by the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0020] Figure 1 This is one of the structural schematic diagrams of the solid-state drive channel signal adjustment system provided by the present invention, such as... Figure 1 As shown, the system includes a main control chip 1 and at least one flash memory chip 2. A channel for transmitting DQS and DQ signals exists between the main control chip 1 and the flash memory chip 2. The system further includes a real-time monitoring module 3 and a timing adjustment module 4. Specifically: the real-time monitoring module 3 monitors the read operation error rate corresponding to the flash memory chip 2 in real time; when the read operation error rate exceeds a preset threshold, it acquires the operating environment parameters of the DQS and DQ signals and transmits these parameters to the main control chip 1; the main control chip 1 obtains timing adjustment signals for the DQS and DQ signals corresponding to the flash memory chip 2 based on the operating environment parameters and transmits these signals to the timing adjustment module 4; the timing adjustment signals are used to align the DQS and DQ signals corresponding to the flash memory chip 2; and the timing adjustment module 4 receives the timing adjustment signals and adjusts the timing of the DQS and DQ signals corresponding to the flash memory chip 2 according to these signals.

[0021] The controller chip 1 and at least one flash memory chip 2 can be the controller chip and flash memory chip in a solid-state drive (SSD). A channel for transmitting DQS and DQ signals exists between the controller chip 1 and the flash memory chip 2. In an SSD, DQS (Data Strobe) and DQ (Data) are two key signals. DQS is a synchronization signal used to help the receiver accurately align and receive data during data transmission. DQ is the data signal, carrying the actual data information to be transmitted. In an SSD, DQS and DQ signals are indispensable components in the data read and write process. The DQS signal, as a synchronization signal, ensures the alignment and accuracy of data during transmission; while the DQ signal carries the actual data information. Together, they achieve efficient and accurate data transmission in the SSD.

[0022] However, in actual signal transmission, various noises, interferences, and attenuations can affect signal transmission, leading to signal distortion, jitter, and timing deviations. These issues directly impact the read performance and data transfer rate of SSDs. Furthermore, SSDs exhibit different signal characteristics under different operating environments (such as temperature variations and voltage fluctuations). Therefore, it is necessary to optimize SSD channel signals to improve SSD read performance and data transfer rate.

[0023] The solid-state drive channel signal adjustment system provided by this invention, in addition to the main control chip 1 and at least one flash memory chip 2 ( Figure 1 Only one flash memory chip 2 is shown, and it also includes a real-time monitoring module 3 and a timing adjustment module 4. When the timing adjustment module 4 is working, it receives control commands from the main control chip 1 through a high-speed interface and adjusts the rising and falling edge timings of the DQS and DQ signals in real time to ensure signal synchronization.

[0024] The real-time monitoring module 3 is used to monitor the read operation error rate of the flash memory chip 2 during the operation of the solid-state drive. When the read operation error rate is greater than a preset threshold, it acquires the working environment parameters of the DQS and DQ signals and transmits the working environment parameters to the main control chip 1. The main control chip 1 is used to obtain the timing adjustment signals of the DQS and DQ signals corresponding to the flash memory chip 2 according to the working environment parameters and transmits the timing adjustment signals to the timing adjustment module 4. The timing adjustment signals are used to align the DQS and DQ signals corresponding to the flash memory chip. The timing adjustment module 4 is used to receive the timing adjustment signals and adjust the timing of the DQS and DQ signals corresponding to the flash memory chip 2 according to the timing adjustment signals. For example, by adjusting the rising and falling edges of the DQS and DQ signals, the timing of the DQS and DQ signals is aligned, ensuring signal synchronization and ensuring that the signals are sampled at appropriate times.

[0025] The solid-state drive (SSD) channel signal adjustment system provided by this invention includes a real-time monitoring module and a timing adjustment module. The real-time monitoring module monitors the read operation error rate corresponding to the flash memory chip in real time. When the read operation error rate exceeds a preset threshold, it acquires the operating environment parameters of the DQS and DQ signals and transmits these parameters to the main control chip. The main control chip obtains the timing adjustment signals of the DQS and DQ signals corresponding to the flash memory chip based on the operating environment parameters and transmits these signals to the timing adjustment module. The timing adjustment module receives the timing adjustment signals and adjusts the timing of the DQS and DQ signals corresponding to the flash memory chip according to these signals. This achieves adaptive optimization adjustment of the SSD channel signals, enabling it to adapt to complex and changing working environments and significantly improving the read performance and data transfer rate of the SSD.

[0026] According to the present invention, a solid-state drive channel signal adjustment system is provided, wherein the operating environment parameters include at least one of voltage, temperature and operating frequency.

[0027] The timing adjustment module 4 can dynamically adjust the timing of the DQS and DQ signals based on real-time monitored data (such as temperature, voltage, and operating frequency). Specifically, the timing adjustment module 4 ensures signal synchronization by adjusting the timing of the rising and falling edges of the signals. For example, in high-temperature environments, the signal propagation speed may slow down; the timing adjustment module 4 can ensure that the signal is sampled at the appropriate time by delaying the timing of the rising and falling edges.

[0028] The solid-state drive channel signal adjustment system provided by this invention improves the reliability of signal timing adjustment by adjusting the timing of DQS and DQ signals according to working environment parameters such as voltage, temperature and operating frequency.

[0029] Figure 2 This is the second schematic diagram of the solid-state drive channel signal adjustment system provided by the present invention, as shown below. Figure 2 As shown, the system further includes a voltage adjustment module 5; the real-time monitoring module 3 is further configured to acquire signal quality parameters of the DQS signal and the DQ signal when the read operation error rate corresponding to the flash memory chip 2 is greater than the preset threshold, and transmit the signal quality parameters to the main control chip 1; the main control chip 1 is further configured to obtain voltage adjustment signals of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the signal quality parameters, and transmit the voltage adjustment signals to the voltage adjustment module 5; the voltage adjustment module 5 is configured to receive the voltage adjustment signals and adjust the voltages of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the voltage adjustment signals.

[0030] The solid-state drive channel signal adjustment system provided by this invention adjusts not only the timing of the DQS and DQ signals, but also their voltages to improve signal quality. Therefore, the system also includes a voltage adjustment module 5. Under the control of the main control chip 1, the voltage adjustment module 5 dynamically adjusts the voltage amplitudes of the DQS and DQ signals. During operation, the voltage adjustment module 5 receives control commands from the main control chip 1 via a high-speed interface to dynamically adjust the voltage amplitudes of the DQS and DQ signals.

[0031] The real-time monitoring module 3 is also used to acquire the signal quality parameters of the DQS and DQ signals when the read operation error rate corresponding to the flash memory chip 2 exceeds a preset threshold, and transmit the signal quality parameters to the main control chip 1. The main control chip 1 is also used to obtain the voltage adjustment signals of the DQS and DQ signals corresponding to the flash memory chip 2 based on the signal quality parameters, and transmit the voltage adjustment signals to the voltage adjustment module 5. The voltage adjustment module 5 is used to receive the voltage adjustment signals and adjust the voltages of the DQS and DQ signals corresponding to the flash memory chip 2 according to the voltage adjustment signals. By adjusting the output voltage of the voltage source of the DQS and DQ signals, the DQS and DQ signals are ensured to be transmitted at the optimal voltage level.

[0032] The solid-state drive channel signal adjustment system provided by this invention, through a real-time monitoring module, is used to acquire signal quality parameters of the DQS and DQ signals when the read operation error rate corresponding to the flash memory chip exceeds a preset threshold, and transmit the signal quality parameters to the main control chip. The main control chip is also used to obtain voltage adjustment signals of the DQS and DQ signals corresponding to the flash memory chip based on the signal quality parameters, and transmit the voltage adjustment signals to the voltage adjustment module. The voltage adjustment module is used to receive the voltage adjustment signals and adjust the voltage of the DQS and DQ signals corresponding to the flash memory chip according to the voltage adjustment signals, thereby realizing dynamic adjustment of the voltage amplitude of the DQS and DQ signals and ensuring that the signals are transmitted at the optimal voltage level.

[0033] According to a solid-state drive channel signal adjustment system provided by the present invention, the signal quality parameter includes signal strength; when the main control chip 1 obtains the voltage adjustment signals of the DQS signal and the DQ signal corresponding to the flash memory chip 2 based on the signal quality parameter, it is specifically used to: in response to the signal strength of the DQS signal and the DQ signal corresponding to the flash memory chip 2 being lower than a preset signal strength, generate a voltage adjustment signal for increasing the voltage of the DQS signal and the DQ signal.

[0034] Signal quality parameters can include signal strength. When signal strength is low, signal transmission quality can be enhanced by increasing the voltage amplitude. Therefore, when the main control chip 1 obtains the voltage adjustment signals for the DQS and DQ signals corresponding to the flash memory chip 2 based on the signal quality parameters, if it learns that the signal strength of the DQS and DQ signals corresponding to the flash memory chip 2 is lower than a preset signal strength, it generates a voltage adjustment signal to increase the voltage of the DQS and DQ signals. The voltage adjustment module 5 increases the supply voltage of the DQS and DQ signals based on the voltage adjustment signal generated by the main control chip 1, thereby improving signal quality.

[0035] The solid-state drive channel signal adjustment system provided by the present invention, through signal quality parameters including signal strength, responds to the fact that the signal strength of the DQS signal and DQ signal corresponding to the flash memory chip is lower than the preset signal strength, and generates a voltage adjustment signal to increase the voltage of the DQS signal and DQ signal, thereby effectively improving the signal quality of the DQS signal and DQ signal.

[0036] According to a solid-state drive channel signal adjustment system provided by the present invention, the signal quality parameter includes a noise level; when the main control chip 1 obtains the voltage adjustment signals of the DQS signal and the DQ signal corresponding to the flash memory chip 2 based on the signal quality parameter, it is specifically used to: in response to the noise level of the DQS signal and the DQ signal corresponding to the flash memory chip 2 being higher than a preset noise level, generate a voltage adjustment signal for increasing the voltage of the DQS signal and the DQ signal.

[0037] Signal quality parameters can also include noise levels. When signal noise is high, the signal's anti-interference capability can be enhanced by increasing the signal voltage amplitude. Therefore, when the main control chip 1 obtains the voltage adjustment signals for the DQS and DQ signals corresponding to the flash memory chip 2 based on the signal quality parameters, if it learns that the noise levels of the DQS and DQ signals corresponding to the flash memory chip 2 are higher than a preset noise level, it generates voltage adjustment signals to increase the voltages of the DQS and DQ signals. The voltage adjustment module 5 increases the supply voltage of the DQS and DQ signals based on the voltage adjustment signals generated by the main control chip 1, thereby improving signal quality.

[0038] The solid-state drive channel signal adjustment system provided by the present invention, through signal quality parameters including noise level, responds to the noise level of the DQS signal and DQ signal corresponding to the flash memory chip being higher than a preset noise level, and generates a voltage adjustment signal to increase the voltage of the DQS signal and DQ signal, thereby effectively improving the signal quality of the DQS signal and DQ signal.

[0039] According to the solid-state drive channel signal adjustment system provided by the present invention, the main control chip 1 is further configured to: initialize the parameters of the DQS signal and the DQ signal when the solid-state drive is powered on, and write data of a preset size to the flash memory chip 2.

[0040] During the initial power-on phase, the solid-state drive (SSD) operates at a low frequency, gradually transitioning to a pre-set frequency. Initialization is performed during this low-frequency phase, including setting the parameters of the DQS and DQ signals to their default values. After configuration, the real-time monitoring module 3, timing adjustment module 4, and voltage adjustment module 5 enter the ready phase. During this low-frequency phase, a preset size of data (e.g., a page) is written to each NAND flash memory chip controlled by each channel of the SSD. The parameters of the DQS and DQ signals include the DQ write clock and the DQS read direction delay.

[0041] The solid-state drive channel signal adjustment system provided by this invention initializes the parameters of the DQS and DQ signals when the solid-state drive is powered on, and writes a preset amount of data to the flash memory chip 2, thus providing the initial working conditions for the solid-state drive and providing a basis for subsequent calculation of read operation errors by writing the preset amount of data.

[0042] According to the solid-state drive channel signal adjustment system provided by the present invention, the real-time monitoring module 3 is further configured to: read the preset size of data written by the flash memory chip 2 after the solid-state drive reaches a preset frequency, and calculate the read operation error rate.

[0043] After the solid-state drive (SSD) is powered on and starts up, it gradually reaches the preset frequency and can then operate normally. Once the SSD reaches the preset frequency, the real-time monitoring module 3 reads the preset size of data written to each flash memory chip 2, compares the read results with the pre-written data, and calculates the read operation error rate.

[0044] The solid-state drive channel signal adjustment system provided by this invention reads a preset size of data written by the flash memory chip after the solid-state drive reaches a preset frequency, and calculates the read operation error rate, thus providing a basis for optimizing the parameters set during initialization.

[0045] According to the solid-state drive channel signal adjustment system provided by the present invention, the real-time monitoring module 3 is further configured to: acquire the flash memory chip 2 that achieves a read operation error rate lower than a preset threshold for the first time after the solid-state drive is powered on, and transmit the information of the flash memory chip 2 to the main control chip 1; the main control chip 1 is further configured to configure the parameters of the DQS signal and the DQ signal of other flash memory chips 2 according to the parameters of the DQS signal and the DQ signal of the flash memory chip 2.

[0046] During the operation of the solid-state drive (including the initialization phase), the real-time monitoring module 3 monitors the read operation error rate corresponding to the flash memory chip 2 in real time. When the read operation error rate exceeds a preset threshold, it acquires the operating environment parameters and signal quality parameters of the DQS and DQ signals and transmits them to the main control chip 1. The main control chip 1 obtains the timing adjustment signals of the DQS and DQ signals corresponding to the flash memory chip 2 based on the operating environment parameters and transmits them to the timing adjustment module 4. The timing adjustment module 4 receives the timing adjustment signals and adjusts the timing of the DQS and DQ signals corresponding to the flash memory chip 2 according to the timing adjustment signals. The main control chip 1 also obtains the voltage adjustment signals of the DQS and DQ signals corresponding to the flash memory chip 2 based on the signal quality parameters and transmits them to the voltage adjustment module 5. The voltage adjustment module 5 receives the voltage adjustment signals and adjusts the voltage of the DQS and DQ signals corresponding to the flash memory chip 2 according to the voltage adjustment signals.

[0047] During the aforementioned adjustment process, the voltage and timing of the DQS and DQ signals corresponding to each flash memory chip 2 are adjusted respectively. The parameters of the DQS and DQ signals also change during this adjustment. Since the default values ​​of the DQS and DQ signal parameters set during power-on initialization usually differ significantly from the parameters required for actual operation, it is necessary to adjust the initialization parameters after power-on to ensure that the DQS and DQ signals of each flash memory chip 2 operate under appropriate parameters.

[0048] Since the voltage and timing of the DQS and DQ signals corresponding to each flash memory chip 2 are adjusted separately, the real-time monitoring module 3 detects the flash memory chip 2 that achieves a read operation error rate lower than the preset threshold for the first time after the solid-state drive is powered on, and transmits the information of the flash memory chip 2 to the main control chip 1. At this time, the parameters of the DQS and DQ signals of the flash memory chip 2 are considered to be at a reasonable value. Using the parameters of the DQS and DQ signals of the flash memory chip 2, the parameters of the DQS and DQ signals of other flash memory chips 2 are configured, thereby optimizing the initialization parameters of each DQS and DQ signal in one step, so that each DQS and DQ signal operates under reasonable parameter settings. This achieves the optimal configuration of the original DQS and DQ signals of each channel of the SSD.

[0049] During SSD operation, read operations may encounter errors due to factors such as voltage and temperature fluctuations. When the SSD's real-time monitoring module 3 detects a read error (read operation error rate exceeding a preset threshold), it sends the monitoring results to the main controller chip 1. The main controller chip 1 then controls the timing adjustment module 4 to adjust the timing of the DQS and DQ signals, and controls the voltage adjustment module 5 to adjust the voltage amplitude of the DQS and DQ signals, achieving dynamic adjustment of the DQS and DQ signals. Subsequently, during operation, the DQS and DQ signals corresponding to each flash memory chip 2 can be optimized under the control of the timing adjustment module 4 and the voltage adjustment module 5, respectively. These steps ensure that the SSD maintains optimal performance under various operating conditions, improving the system's adaptability.

[0050] The solid-state drive channel signal adjustment system provided by this invention obtains the flash memory chip that achieves a read operation error rate lower than a preset threshold for the first time after the solid-state drive is powered on, and transmits the information of the flash memory chip to the main control chip. The main control chip is also used to configure the parameters of the DQS and DQ signals of other flash memory chips according to the parameters of the flash memory chip's DQS and DQ signals, thereby quickly optimizing the initialization parameters of the DQS and DQ signals.

[0051] In addition, the present invention also provides a solid-state drive (SSD) including the SSD channel signal adjustment system of any of the above embodiments. That is, the SSD is a type of SSD capable of optimizing both the DQS and DQ signals.

[0052] Figure 3 This is a schematic diagram of the processing flow of the solid-state drive channel signal adjustment system provided by the present invention. Figure 3 As shown, the process includes:

[0053] Solid-state drive power-on initialization;

[0054] The real-time monitoring module is activated, and the voltage adjustment module and timing adjustment module are ready.

[0055] Import data into NAND flash memory chips;

[0056] After the solid-state drive's operating frequency is detected to have increased to the set frequency, the pre-written data is read.

[0057] The real-time monitoring module obtains the read operation error rate;

[0058] If the read operation error rate is greater than the preset threshold, the operating environment parameters and signal quality parameters of the DQS and DQ signals are acquired and transmitted to the main control chip. The main control chip generates timing adjustment signals based on the operating environment parameters to control the timing adjustment module to adjust the timing of the DQS and DQ signals, and generates voltage adjustment signals based on the signal quality parameters to control the voltage adjustment module to adjust the voltage of the DQS and DQ signals.

[0059] After the solid-state drive is powered on, the flash memory chip that achieves a read operation error rate lower than a preset threshold for the first time will transmit the information of the flash memory chip to the main control chip. The main control chip is also used to configure the parameters of the DQS and DQ signals of other flash memory chips according to the parameters of the DQS and DQ signals of the flash memory chip, thereby optimizing the initialization parameters of the DQS and DQ signals.

[0060] During the operation of the solid-state drive, the real-time monitoring module monitors the read operation error rate in real time. If the read operation error rate exceeds a preset threshold, it acquires the operating environment parameters and signal quality parameters of the DQS and DQ signals and transmits them to the main control chip. The main control chip then generates timing adjustment signals based on the operating environment parameters to control the timing adjustment module to adjust the timing of the DQS and DQ signals, and generates voltage adjustment signals based on the signal quality parameters to control the voltage adjustment module to adjust the voltage of the DQS and DQ signals, thereby achieving dynamic optimization of the DQS and DQ signals.

[0061] The solid-state drive channel signal adjustment system provided by this invention has the following characteristics:

[0062] (1) Improve signal quality and stability

[0063] By monitoring operational data in real time and adaptively and dynamically adjusting voltage and timing parameters, signal noise and distortion are reduced, improving signal clarity and stability. Synchronization of DQS and DQ signals and accuracy of data sampling are ensured, reducing timing deviations.

[0064] (2) Enhance the system's adaptive capability

[0065] It can automatically adjust voltage and timing parameters based on real-time monitoring data to ensure that the SSD maintains optimal performance under various operating conditions.

[0066] (3) Improve SSD read performance

[0067] By optimizing signal quality, improving data transfer rate and reliability, the read performance of SSDs is significantly enhanced.

[0068] (4) Improve the reliability and lifespan of SSDs

[0069] By reducing signal noise and distortion, the data error rate is lowered, improving SSD reliability. Dynamically adjusting and optimizing signal parameters reduces failures caused by signal quality issues, extending the SSD's lifespan.

[0070] (5) Adaptable to various working conditions

[0071] Dynamically adjust voltage and timing parameters to adapt to different operating conditions (such as temperature changes and voltage fluctuations), ensuring stable operation of the SSD in various environments. Improve the SSD's adaptability to complex application scenarios and meet the needs of different users.

[0072] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0073] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A solid-state drive channel signal adjustment system, the system comprising a main control chip, at least one flash memory chip, a real-time monitoring module, a timing adjustment module, and a voltage adjustment module, wherein a channel for transmitting DQS signals and DQ signals exists between the main control chip and the flash memory chip, characterized in that: The main control chip is used to initialize the parameters of the DQS signal and the DQ signal when the solid-state drive is powered on, and to write data of a preset size to the flash memory chip; The real-time monitoring module is used to read the preset size of data written by the flash memory chip after the solid-state drive reaches a preset frequency, calculate the read operation error rate, identify the flash memory chip that achieves the first read operation error rate below a preset threshold after the solid-state drive is powered on, and transmit the information of the flash memory chip to the main control chip; during the operation of the solid-state drive, it monitors the read operation error rate corresponding to the flash memory chip in real time, and when the read operation error rate is greater than the preset threshold, it synchronously acquires the working environment parameters and signal quality parameters of the DQS signal and the DQ signal, and transmits the working environment parameters and signal quality parameters to the main control chip, wherein the working environment parameters include at least one of voltage, temperature and operating frequency; The main control chip is further configured to configure the parameters of the DQS and DQ signals of other flash memory chips according to the parameters of the DQS and DQ signals of the flash memory chip; obtain timing adjustment signals for the DQS and DQ signals corresponding to the flash memory chip according to the operating environment parameters, and transmit the timing adjustment signals to the timing adjustment module; obtain voltage adjustment signals for the DQS and DQ signals corresponding to the flash memory chip according to the signal quality parameters, and transmit the voltage adjustment signals to the voltage adjustment module; wherein, the timing adjustment signals are used to align the DQS and DQ signals corresponding to the flash memory chip; The timing adjustment module is used to receive the timing adjustment signal and adjust the timing of the DQS signal and the DQ signal corresponding to the flash memory chip according to the rising and falling edges of the timing adjustment signal. The voltage adjustment module is used to adjust the voltage of the DQS signal and the DQ signal corresponding to the flash memory chip according to the voltage adjustment signal.

2. The solid-state drive channel signal adjustment system according to claim 1, characterized in that, The voltage adjustment module is used to receive the voltage adjustment signal.

3. The solid-state drive channel signal adjustment system according to claim 2, characterized in that, The signal quality parameters include signal strength; when the main control chip obtains the voltage adjustment signals of the DQS signal and the DQ signal corresponding to the flash memory chip based on the signal quality parameters, it is specifically used for: In response to the signal strength of the DQS signal and the DQ signal corresponding to the flash memory chip being lower than the preset signal strength, a voltage adjustment signal is generated to increase the voltage of the DQS signal and the DQ signal.

4. The solid-state drive channel signal adjustment system according to claim 2, characterized in that, The signal quality parameters include noise levels; when the main control chip obtains the voltage adjustment signals for the DQS signal and the DQ signal corresponding to the flash memory chip based on the signal quality parameters, it is specifically used for: In response to the noise levels of the DQS signal and the DQ signal corresponding to the flash memory chip being higher than a preset noise level, a voltage adjustment signal is generated to increase the voltage of the DQS signal and the DQ signal.

5. The solid-state drive channel signal adjustment system according to claim 1, characterized in that, The parameters of the DQS signal and the DQ signal include the DQ write clock and the delay of the DQS read direction.

6. A solid-state drive, characterized in that, Includes the solid-state drive channel signal adjustment system as described in any one of claims 1 to 5.

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