Memory management communication interface for network-on-chip and DDR controller

Abstract

A memory management communication interface for a network-on-chip and a DDR controller. The memory management communication interface is connected to a host by means of the network-on-chip, and is connected to a DDR memory chip by means of the DDR controller. The memory management communication interface comprises: a request processing module, configured to receive a request packet from the host by means of the network-on-chip, and verify the integrity of the data format of the request packet; a response processing module, configured to send an ID unlocking request to the request processing module; and an output control module, configured to receive a read acknowledgment packet from the request processing module and a response packet from the response processing module, and further configured to handle a situation where the read acknowledgment packet and the response packet are received simultaneously. The memory management communication interface can ensure the security of data during the transmission of requests of multiple hosts over the network-on-chip, thereby improving the performance of a multi-chiplet Internet system.

Description

A memory management communication interface for on-chip network and DDR controller Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a memory management communication interface for on-chip networks and DDR controllers. Background Technology

[0002] In recent years, constrained by Moore's Law, the development cost of integrated circuit chips has increased dramatically. In certain fields, the emergence of chip-on-chip technology has greatly shortened the chip design and manufacturing cycle. This technology relies on on-chip networks to integrate different bare dies, and the on-chip network accesses a remote DDR controller through a communication interface to control DDR memory chips for read and write operations.

[0003] Currently, this type of communication interface has data security issues. When different hosts access DDR memory chips through the on-chip network, the data that has already been written is easily accessed and modified illegally. Therefore, it is necessary to propose a memory management communication interface for the on-chip network and the DDR controller to solve this problem. Summary of the Invention

[0004] The purpose of this invention is to provide a memory management communication interface for on-chip network and DDR controller, so as to ensure data security when transmitting multi-host requests on the on-chip network and improve the performance of multi-chip interconnect network system.

[0005] To address the aforementioned technical problems, this invention provides a memory management communication interface for an on-chip network and a DDR controller. This memory management communication interface connects to the host via the on-chip network and to the DDR memory chips via the DDR controller. The memory management communication interface includes:

[0006] The request processing module is used to receive request packets from the host via the on-chip network and verify the integrity of the request packet data format; it is also used for memory management of DDR memory chips, including dividing DDR memory chips into memory blocks, verifying the legality of host requests for memory block occupancy, sharing, release, read, and write requests, and outputting memory management information to the response processing module; it is also used to perform protocol conversion or data concatenation of authorized read and write request packets to obtain data packets of AW, W, and AR channel types in the form of AXI bus signals, and send them to the DDR controller, which controls the DDR memory chips to complete read and write operations; it is also used to generate read confirmation packets after read request authorization and output them to the output control module; and it is also used to receive ID unlock requests from the response processing module.

[0007] The response processing module is used to send an ID unlock request to the request processing module; it is also used to receive memory management information from the request processing module, package the memory management response information into a response packet, and output it to the output control module; it is also used to package the data of the B and R channels in the form of AXI bus signals read from the DDR controller into a read response packet and output it to the output control module.

[0008] The output control module is used to receive read acknowledgment packets from the request processing module and response packets from the response processing module; it is also used to handle the situation where read acknowledgment packets and response packets are received simultaneously; when they are received simultaneously, the response packets are arbitrated according to a pre-defined priority, and the response packets with higher priority are fed back to the on-chip network first, while the response packets with lower priority wait for the next priority arbitration.

[0009] Preferably, the memory management communication interface receives request packets from the host via the on-chip network, verifies the integrity and validity of the request packet data, and converts valid request packets into request data packets of AW, W, and AR channel types in the form of AXI bus signals. The DDR controller then controls the DDR memory chips to perform read and write operations. After the read and write operations are completed, the DDR controller returns response data packets of B and R channel types in the form of AXI bus signals to the memory management communication interface. The memory management communication interface packages the response data packets into response packets and outputs them to the host via the on-chip network.

[0010] Preferably, the specific connection circuit of the memory management communication interface is as follows:

[0011] The data input port of the request processing module is connected to the data output port of the on-chip network. The data output port of the request processing module is connected to the data input ports of the DDR controller, the response processing module, and the output control module. The data input port of the response processing module is connected to the data output ports of the DDR controller and the request processing module. The data output port of the response processing module is connected to the data output port of the output control module. The data input port of the output control module is connected to the data output ports of the request processing module and the response processing module. The data output port of the output control module is connected to the data input port of the on-chip network.

[0012] Preferably, the request processing module includes:

[0013] The verification unit performs data format integrity verification on request packets from the on-chip network. After verification, it returns the verification result to the request processing protocol conversion and memory management control state machine. When the verification is successful, the complete request packet is output to the memory management unit. When the verification fails, the request packet is discarded.

[0014] The memory management unit verifies the validity of request packets. When the verification is valid, it divides the DDR storage chips into memory blocks of different sizes and performs operations such as occupying, releasing, sharing, reading, and writing on the divided memory blocks. When the verification is invalid, it rejects the invalid request packets and outputs the corresponding memory management response information to the response processing module.

[0015] Request processing protocol conversion and memory management control state machine;

[0016] The read / write request protocol conversion unit, for read and write operations, requests the processing protocol conversion and memory management control state machine outputs read and write control information to the read / write request protocol conversion unit, the protocol conversion obtains AW and AR channel type data packets in the form of AXI bus signals, and outputs them to the DDR controller;

[0017] For write operations, the request processing protocol conversion and memory management control state machine outputs the write data to the write data concatenation unit and concatenates the data into a W-channel type data packet in the form of an AXI bus signal, which is then output to the DDR controller. For read operations, the request processing protocol conversion and memory management control state machine generates a read confirmation packet based on the valid read request information and outputs it to the output control module.

[0018] When processing a request packet, the ID lock unit queries the locked ID number and sends an ID locking request based on the event ID of the request packet, according to the request processing protocol conversion and memory management control state machine.

[0019] Preferably, the response processing module includes:

[0020] Memory management response unit;

[0021] Packaged logical units;

[0022] Read data splicing unit;

[0023] The response processing protocol transition control state machine is used to receive memory management response information from the request processing module, control the memory management response unit to generate corresponding response packets and output them to the output control module; it is also used to receive data from the B and R channels in the form of AXI bus signals from the DDR controller. For the data on the B channel, which is write response information, a response packet is generated by the packing logic unit and output to the output control module. For the data on the R channel, which is read data, a data packet is assembled by the read data splicing unit and then a response packet is generated by the packing logic unit and output to the output control module; it is also used to send an ID unlock request to the request processing module.

[0024] Preferably, in the verification unit, the request packet includes multiple micro-pieces of a fixed format arranged in sequence, and the micro-pieces carry the operation event type, event ID, address and data information of the transmission; in the memory management unit, the event type, data length and write / read address in the request packet are verified for validity.

[0025] Preferably, the ID lock unit is responsible for restricting the transmission of data packets with the same TID, ensuring that read-related transactions or write-related transactions to be processed and those being processed in the interface have different TIDs; after receiving the request packet, the request processing module first checks the ID lock status of the corresponding TID. If the check result is that it is not locked, the subsequent processing process is performed; when the request packet processing module completes the AXI request, it locks the corresponding ID; when the response processing module completes the corresponding AXI response, it unlocks the ID.

[0026] Preferably, the ID lock unit further includes the following functions:

[0027] (1) The write ID lock status signal in the output signal will report the write ID status consistent with the current write ID check input signal, 0 indicates that it is not locked, and 1 indicates that it is locked;

[0028] (2) The read ID lock status signal in the output signal will report the read ID status consistent with the current check read ID input signal, 0 indicates that it is not locked, and 1 indicates that it is locked;

[0029] (3) When the write ID lock request is 1, the ID lock will lock the write ID that is consistent with the lock write ID signal, that is, write 1 to the corresponding write ID register in the ID lock unit;

[0030] (4) When the read ID lock request is 1, the ID lock will lock the read ID that is consistent with the lock read ID signal, that is, write 1 to the corresponding read ID register in the ID lock unit;

[0031] (5) When the write ID unlock request is 1, the ID lock will unlock the write ID that is consistent with the unlock write ID signal, that is, write 0 to the corresponding write ID register in the ID lock unit;

[0032] (6) When the read ID unlock request is 1, the ID lock will unlock the read ID that is consistent with the unlock read ID signal, that is, write 0 to the corresponding read ID register in the ID lock unit;

[0033] (7) When an ID unlock request and an ID lock request for the same TID are initiated at the same time, the corresponding ID will be locked.

[0034] Preferably, the request processing protocol conversion and memory management control state machine performs ID lock query on the ID lock unit according to the legitimate request of the memory management unit. If an operation with the same event ID is being executed, the request is put on hold and executed after the ID is unlocked. If no operation with the same event ID is being executed, the request is executed and the ID of the request is locked at the same time.

[0035] Preferably, the memory management response unit receives memory management response information from the response processing protocol transition control state machine, the memory management response information including illegal operation information and legal operation information;

[0036] The illegal operation information includes: performing allocation, release, sharing, and read / write operations without initialization; performing release, sharing, and read / write operations without allocating a memory block; insufficient space in the allocated memory block, resulting in out-of-bounds read / write operations; insufficient remaining space in the DDR memory chips, leading to failure to allocate a memory block.

[0037] Legitimate operation information includes: application success information; sharing success information; release success information.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] This invention proposes a memory management communication interface for on-chip networks and DDR controllers, used to connect the on-chip network and the DDR controller. It can receive request data packets of the on-chip network type, convert them into data packets of AW, W, and AR channel types, and the DDR controller controls the DDR memory chips to complete read and write operations, returning corresponding response data packets to the on-chip network. This memory management communication interface consists of a request processing module, a response processing module, and an output control module. While ensuring transmission in multi-chip interconnect networks, it allocates memory spaces of different sizes to the DDR memory chips, receives and manages memory access requests from multiple hosts, and improves the performance of multi-chip interconnect network systems. Attached Figure Description

[0040] Figure 1 is a schematic diagram of an application scenario of the memory management communication interface provided by the present invention.

[0041] Figure 2 is a schematic diagram of the memory management communication interface provided by the present invention.

[0042] Figure 3 is a schematic diagram of the request processing module provided by the present invention.

[0043] Figure 4 is a schematic diagram of the response processing module provided by the present invention. Detailed Implementation

[0044] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0045] As shown in Figure 1, this embodiment of the invention provides a memory management communication interface for an on-chip network and a DDR controller, enabling data transfer between the on-chip network and the DDR controller. This memory management communication interface connects to the host computer via the on-chip network and to the DDR memory chips via the DDR controller.

[0046] The memory management communication interface receives request packets from the host via the on-chip network, verifies the integrity and validity of the request packet data, and converts valid request packets into request data packets of AW, W, and AR channel types in the form of AXI bus signals. The DDR controller then controls the DDR memory chips to perform read and write operations. After the read and write operations are completed, the DDR controller returns response data packets of B and R channel types in the form of AXI bus signals to the memory management communication interface. The memory management communication interface packages the response data packets into a response packet and outputs it to the host via the on-chip network.

[0047] As shown in Figure 2, the memory management communication interface mainly consists of a request processing module, a response processing module, and an output control module.

[0048] The request processing module is used to receive request data packets from the host via the on-chip network and verify the integrity of the request packet data format; it is also used for memory management of DDR memory chips, including dividing the DDR memory chips into memory blocks, verifying the legality of host requests for occupancy, sharing, release, read, and write to DDR memory blocks, and outputting memory management information to the response processing module; it is also used to convert authorized read request packets and write request packets into AW, W, and AR channel type data packets in the form of AXI bus signals and send them to the DDR controller, which controls the DDR memory chips to complete read and write operations; it is also used to generate read confirmation packets after read request authorization and output them to the output control module; and it is also used to receive ID unlock requests from the response processing module.

[0049] The response processing module is used to send an ID unlock request to the request processing module; it is also used to receive memory management information from the request processing module, package the memory management response information into a response packet, and output it to the output control module; it is also used to package the data of the B and R channels in the form of AXI bus signals read from the DDR controller into a read response packet and output it to the output control module.

[0050] The output control module receives read acknowledgment packets from the request processing module and response packets from the response processing module. It also handles the situation where read acknowledgment packets and response packets are received simultaneously. When received simultaneously, the response packets are arbitrated according to a pre-defined priority. The response packet with higher priority is sent to the on-chip network first, while the response packet with lower priority waits for the next priority arbitration.

[0051] Specifically, as shown in Figure 3, the three modules in the memory management communication interface are described in detail below:

[0052] 1. Request processing module: The request processing module mainly consists of a verification unit, a memory management unit, a read / write request protocol conversion unit, a write data concatenation unit, an ID lock unit, and a request processing protocol conversion and memory management control state machine.

[0053] The verification unit performs data format integrity checks on request packets from the on-chip network. After verification, it returns the result to the request processing protocol conversion and memory management control state machine. If verification is successful, the complete request packet is output to the memory management unit; if verification fails, the request packet is discarded. The memory management unit performs validity checks on the request packets. If valid, it divides the DDR memory chips into memory blocks of different sizes and performs occupy, release, share, read, and write operations on these memory blocks. If invalid, the invalid request packet is rejected, and the corresponding memory management information is output to the response processing module. For read and write operations, the request processing protocol conversion and memory management control state machine transmits read and write control information. The data is output to the read / write request protocol conversion unit, where it is converted into AW and AR channel type data packets in the form of AXI bus signals, and then output to the DDR controller. For write operations, the request processing protocol conversion and memory management control state machine outputs the write data to the write data splicing unit, which splices the data into W channel type data packets in the form of AXI bus signals, and then outputs them to the DDR controller. For read operations, the request processing protocol conversion and memory management control state machine generates a read confirmation packet based on the valid read request information and outputs it to the output control module. When processing a request packet, the request processing protocol conversion and memory management control state machine queries the ID lock unit for the locked ID number and sends an ID lock request based on the event ID of the request packet.

[0054] The verification unit, memory management unit, read / write request protocol conversion unit, write data concatenation unit, ID lock unit, and request processing protocol conversion and memory management control state machine are described below:

[0055] In one embodiment, the verification unit includes multiple micro-pieces of a fixed format arranged in sequence in the request packet. The micro-pieces carry information such as the type of operation event, event ID, address, and data to be transmitted. The verification unit performs data format integrity verification on the request packet from the on-chip network. After the verification is completed, the verification result is returned to the request processing protocol conversion and memory management control state machine. When the verification is successful, the complete format request packet is output to the memory management unit. When the verification fails, the request packet is discarded.

[0056] In one embodiment, the memory management unit sends an initialization write request packet with address 0. The write data contains the capacity of the DDR storage chip. The memory management unit divides the capacity into memory blocks of different sizes by dividing the DDR storage chip into two levels according to a binary tree algorithm.

[0057] In another embodiment, the memory management unit verifies the validity of the event type, data length, and read / write address in the request packet. Validity means that the host can perform read, write, share, and release operations on the memory block of the requested DDR storage chip; the host sharing the memory block can perform read operations on it; and other hosts cannot perform any operations on the already occupied memory block. When the request is valid, the validity information for the memory management requests (allocation, release, and sharing) is output to the response processing module, and the read and write requests are output to the request processing protocol conversion and memory management control state machine. When the request is invalid, the invalid information for the memory management requests (allocation, release, and sharing) is output to the response processing module and rejected.

[0058] In one embodiment, for read and write operations, the request processing protocol conversion and memory management control state machine outputs read and write control information such as read and write event ID, read and write address, and read and write length to the read and write request protocol conversion unit. The protocol conversion yields data packets of AW and AR channel types in the form of AXI bus signals, which are then output to the DDR controller to control the DDR memory chips to perform read and write operations.

[0059] In one embodiment, the write data splicing unit, for write operations, since the data width of the W channel type in the form of the AXI bus signal on the DDR controller side is 256 bits, while the data packets from the on-chip network are transmitted in units of words (32 bits), i.e., the data width is 128 bits, therefore, when initiating a write operation to the DDR controller, the write data needs to be spliced ​​and aligned according to the low bits of the word alignment start address. That is, when initiating a write request to the AXI bus, the corresponding address of the write data must always be a multiple of 32. Eight 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 write data splicing modules respectively complete the write data splicing task for the low bits 0 / 4 / 8 / 12 / 16 / 20 / 24 / 28 corresponding to the word alignment address. The request processing protocol conversion and memory management control state machine outputs the write data to the write data splicing unit, which splices the data into a W channel type data packet in the form of an AXI bus signal, and outputs it to the DDR controller to control the DDR memory chip to perform write data operations.

[0060] In one embodiment, the ID locking unit is responsible for restricting the transmission of data packets with the same TID, ensuring that pending and ongoing read or write transactions within the interface have different TIDs. In a normal workflow, the request processing module, upon receiving a request packet, first checks the ID lock status of the corresponding TID. If the check result is that it is not locked, subsequent processing is performed. When the request packet processing module completes the AXI request, it locks the corresponding ID. The ID is unlocked only after the response processing module completes the corresponding AXI response. When processing a request packet, the request processing protocol conversion and memory management control state machine queries the ID locking unit for the locked ID number and sends an ID locking request based on the event ID of the request packet.

[0061] Specifically, the functions of the aforementioned ID lock unit are as follows:

[0062] (1) The write ID lock status signal in the output signal will report the write ID status consistent with the current write ID input signal. 0 indicates that it is not locked and 1 indicates that it is locked.

[0063] (2) The read ID lock status signal in the output signal will report the read ID status consistent with the current check read ID input signal. 0 indicates that it is not locked and 1 indicates that it is locked.

[0064] (3) When the write ID lock request is 1, the ID lock will lock the write ID that is consistent with the lock write ID signal, that is, write 1 to the corresponding write ID register in the module.

[0065] (4) When the read ID lock request is 1, the ID lock will lock the read ID that is consistent with the lock read ID signal, that is, write 1 to the corresponding read ID register in the module.

[0066] (5) When the write ID unlock request is 1, the ID lock will unlock the write ID that is consistent with the unlock write ID signal, that is, write 0 to the corresponding write ID register in the module.

[0067] (6) When the read ID unlock request is 1, the ID lock will unlock the read ID that is consistent with the unlock read ID signal, that is, write 0 to the corresponding read ID register in the module.

[0068] (7) When an ID unlock request and an ID lock request for the same TID are initiated at the same time, the corresponding ID will be locked.

[0069] In one embodiment, the request processing protocol conversion and memory management control state machine determines whether to discard the request packet based on the verification result of the verification unit. If the verification format is complete, the control verification unit outputs the request packet to the memory management unit; if the verification format is incomplete, the control verification unit discards the request packet.

[0070] In another embodiment, the request processing protocol conversion and memory management control state machine performs ID lock query on the ID lock unit according to the legitimate request of the memory management unit. If an operation with the same event ID is being executed, the request is put on hold and executed after the ID is unlocked. If no operation with the same event ID is being executed, the request is executed and the ID of the request is locked at the same time.

[0071] In another embodiment, the request processing protocol conversion and memory management control state machine extracts the read and write control information of the legitimate read and write requests and outputs it to the read and write request protocol conversion unit; it extracts the data of the write request and outputs it to the write data splicing unit; and it outputs a read confirmation packet to the output control module according to the read request information.

[0072] 2. Response processing module: In one embodiment, as shown in Figure 4, the response processing module mainly consists of a memory management response unit, a packing logic unit, a read data splicing unit, and a response processing protocol conversion control state machine.

[0073] The response processing protocol conversion control state machine receives memory management information from the request processing module and controls the memory management response unit to generate corresponding response packets and output them to the output control module. The response processing protocol conversion control state machine also receives data from the B and R channels in the form of AXI bus signals from the DDR controller. For B channel data, which is write response information, a response packet is generated by the packing logic unit and output to the output control module. For R channel data, which is read data, a data packet is assembled by the read data concatenation unit and then generated by the packing logic unit to generate a response packet and output to the output control module. Finally, the response processing protocol conversion control state machine sends an ID unlock request to the request processing module. The memory management response unit, packing logic unit, read data concatenation unit, and response processing protocol conversion control state machine are described below:

[0074] In one embodiment, the memory management response unit receives memory management response information from the response processing protocol transition control state machine. This information includes illegal operation information and legal operation information. Illegal operation information includes: (1) performing request, release, share, or read / write operations without initialization; (2) performing release, share, or read / write operations without requesting a memory block; (3) insufficient space in the requested memory block, resulting in out-of-bounds read / write operations; (4) insufficient remaining space in the DDR memory chip, leading to memory block request failure. Legal operation information includes: (1) successful request information; (2) successful share information; (3) successful release information.

[0075] In another embodiment, the memory management response unit combines the above information to generate a response packet and sends it to the output control module.

[0076] In one embodiment, the packaging logic unit packages data of type B in the form of AXI bus signals from the DDR controller, including write event ID and write response information of write transfer status, into a write response packet and outputs it to the output control module.

[0077] In another embodiment, the packing logic unit outputs the read data contained in the R channel type data in the form of the DDR controller AXI bus signal to the read data splicing unit. After splicing, the data is packaged with the read response information of the read event ID into a read response packet and output to the output control module.

[0078] In one embodiment, for read operations, the data concatenation unit handles the data bit width of the R channel type (AXI bus signal type) on the DDR controller side, which is 256 bits. Data packets from the on-chip network are transmitted in words (32 bits), meaning the data bit width is 128 bits. Furthermore, the request packet processing module always ensures that the address value is a multiple of 32 when initiating a read request via the AR channel type (AXI bus signal type). Therefore, for R channel type data (AXI bus signal type), the read data needs to be concatenated and aligned according to the low-order bits of the word-aligned start address to output the correct read response packet. Eight read data concatenation modules 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 respectively complete the read data concatenation task for the low-order bits 0 / 4 / 8 / 12 / 16 / 20 / 24 / 28 corresponding to the word-aligned address. That is, they select valid bits from the read data based on the length and address information of the corresponding data packet, concatenate and align them, and output the data portion to the packaging logic unit for encapsulation into a read response packet.

[0079] In one embodiment, the response processing protocol transition control state machine receives memory management information from the request processing module and generates memory management response information for the memory management response unit.

[0080] In another embodiment, the response processing protocol conversion control state machine receives B-channel type data in the form of AXI bus signals from the DDR controller, generates write response information, and outputs it to the packing logic unit; the response processing protocol conversion control state machine receives R-channel type data in the form of AXI bus signals from the DDR controller, generates read data, outputs it to the read data splicing unit, and generates read response information, which is then output to the packing logic unit.

[0081] In another embodiment, the response processing protocol transition control state machine, based on the completed output response information, sends an unlock request for the event ID of the request to the ID lock unit in the request processing module.

[0082] 3. Output Control Module: The output control unit is used to feed back the received read confirmation packets, memory management response packets, and response packets from DDR memory chips to the on-chip network. When read confirmation packets, memory management response packets, and response packets from DDR memory chips are received simultaneously, priority arbitration is performed on the response packets according to the pre-defined priority. The response packets with higher priority are fed back to the on-chip network first, and the response packets with lower priority wait for the next priority arbitration. The pre-defined priority is a fixed priority, that is, the read confirmation packets have the highest priority, followed by the response packets from DDR memory chips.

[0083] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A memory management communication interface oriented to a network on chip and a DDR controller, the memory management communication interface connecting a host through a network on chip and connecting a DDR storage particle through a DDR controller; characterized in that, The memory management communication interface comprises: The request processing module is configured to receive a request packet from the host through the network on chip, and check the integrity of the data format of the request packet; the request processing module is further configured to perform memory management on the DDR storage particles, including dividing the DDR storage particles into memory blocks, checking the legality of the occupation request, the sharing request, the release request, the read request and the write request of the host to the memory blocks of the DDR storage particles, and outputting memory management information to the response processing module; the request processing module is further configured to perform protocol conversion or data splicing on the authorized read request packet and the write request packet to obtain data packets in the form of AXI bus signals of AW, W and AR channel types, and send the data packets to the DDR controller, so that the DDR controller controls the DDR storage particles to complete the read / write operation; the request processing module is further configured to generate a read confirmation packet after the read request is authorized and output the read confirmation packet to the output control module; and the request processing module is further configured to receive the ID unlocking request from the response processing module. The response processing module is configured to send an ID unlocking request to the request processing module; the response processing module is further configured to receive the memory management information from the request processing module, pack the memory management response information into a response packet, and output the response packet to the output control module; and the response processing module is further configured to pack the data in the form of AXI bus signals of B and R channels read from the DDR controller into a read response packet, and output the read response packet to the output control module. The output control module is configured to receive the read confirmation packet from the request processing module and the response packet from the response processing module; the output control module is further configured to handle the case that the read confirmation packet and the response packet are received at the same time; when the read confirmation packet and the response packet are received at the same time, the output control module is configured to perform priority arbitration on the response packet according to a pre-defined priority, feed back the response packet with high priority to the network on chip first, and wait for the next priority arbitration for the response packet with low priority.

2. The memory management communication interface for a network-on-chip and DDR controller of claim 1, wherein, The memory management communication interface receives a request packet from the host through the network on chip, checks the integrity and legality of the data of the request packet, converts the request packet into a request data packet in the form of AXI bus signals of AW, W and AR channel types for a legal request packet, controls the DDR storage particles to perform read / write operation through the DDR controller, returns response data packets in the form of AXI bus signals of B and R channel types to the memory management communication interface through the DDR controller after the read / write operation is completed, packs the response data packets into response packets, and outputs the response packets to the host through the network on chip.

3. The memory management communication interface for a network-on-chip and DDR controller of claim 1, wherein, The specific connection circuit of the memory management communication interface comprises: The data input port of the request processing module is connected to the data output port of the network on chip, the data output port of the request processing module is connected to the data input ports of the DDR controller, the response processing module and the output control module, the data input port of the response processing module is connected to the data output ports of the DDR controller and the request processing module, the data output port of the response processing module is connected to the data output port of the output control module, the data input port of the output control module is connected to the data output ports of the request processing module and the response processing module, and the data output port of the output control module is connected to the data input port of the network on chip.

4. The memory management communication interface for a network-on-chip and DDR controller of claim 1, wherein, The request processing module comprises: The check unit checks the data format integrity of the request packet from the network on chip, returns the check result to the request processing protocol conversion and memory management control state machine after the check, outputs the request packet in complete format to the memory management unit when the check is successful, and discards the request packet when the check fails; The memory management unit checks the legality of the request packet, divides the DDR storage particles into different size memory blocks when the check is legal, and performs occupation, release, sharing, reading and writing operations on the divided memory blocks, and rejects the illegal request packet when the check is not legal, and outputs the corresponding memory management response information to the response processing module; The request processing protocol conversion and memory management control state machine; The read-write request protocol conversion unit outputs the read-write control information to the read-write request protocol conversion unit for read and write operations, and the protocol conversion obtains the AXI bus signal form of the AW and AR channel type data packet and outputs it to the DDR controller; The write data splicing unit outputs the write data to the write data splicing unit for write operation, splices the data into the AXI bus signal form of the W channel type data packet, and outputs it to the DDR controller; for read operation, the request processing protocol conversion and memory management control state machine generates a read confirmation packet according to the legal read request information and outputs it to the output control module; The ID lock unit, for processing request packets, the request processing protocol conversion and memory management control state machine queries the ID lock unit according to the event ID of the request packet to lock the ID number and send the ID lock request.

5. The interface of claim 1, wherein, The response processing module includes: The memory management response unit; The packing logic unit; The read data splicing unit; The response processing protocol conversion control state machine is used to receive the memory management response information from the request processing module, control the memory management response unit to generate the corresponding response packet and output it to the output control module, receive the AXI bus signal form of the B and R channel data from the DDR controller, the data of the B channel is write response information, the response packet is generated through the packing logic unit and output to the output control module, the data of the R channel is read data, which is spliced into a data packet through the read data splicing unit, and then the response packet is generated through the packing logic unit and output to the output control module, and the ID unlock request is sent to the request processing module.

6. A network-on-chip and DDR controller oriented memory management communication interface as defined in claim 4, wherein, In the check unit, the request packet includes a plurality of microchips in fixed format arranged in sequence, and the microchip carries the transmission operation event type, event ID, address and data information; In the memory management unit, the legality of the event type, data length and read-write address in the request packet is checked.

7. A memory management communication interface for a network-on-chip and DDR controller as defined in claim 4, wherein, The ID lock unit is responsible for limiting the transmission of data packets of the same TID, ensuring that the read-related transactions or write-related transactions to be processed and being processed in the interface have different TIDs; the request processing module first checks the ID lock state of the corresponding TID after receiving the request packet, and if the check result is not locked, the subsequent processing process is performed. When the request packet processing module finishes the AXI request, the corresponding ID is locked. When the response processing module finishes the corresponding AXI response, the ID is unlocked.

8. The memory management communication interface for a network-on-chip and DDR controller of claim 4, wherein, The ID lock unit further comprises the following functions: (1) The write ID lock state signal in the output signal reports the write ID state consistent with the current check write ID input signal, 0 indicating no locking and 1 indicating locking; (2) The read ID lock state signal in the output signal reports the read ID state consistent with the current check read ID input signal, 0 indicating no locking and 1 indicating locking; (3) When the write ID locking request is 1, the ID lock locks the write ID consistent with the locking write ID signal, that is, writes 1 into the corresponding write ID register in the ID lock unit; (4) When the read ID locking request is 1, the ID lock locks the read ID consistent with the locking read ID signal, that is, writes 1 into the corresponding read ID register in the ID lock unit; (5) When the write ID unlocking request is 1, the ID lock unlocks the write ID consistent with the unlocking write ID signal, that is, writes 0 into the corresponding write ID register in the ID lock unit; (6) When the read ID unlocking request is 1, the ID lock unlocks the read ID consistent with the unlocking read ID signal, that is, writes 0 into the corresponding read ID register in the ID lock unit; (7) When the ID unlocking request and the ID locking request of the same TID are initiated at the same time, the corresponding ID is locked.

9. The memory management communication interface for a network-on-chip and DDR controller of claim 4, wherein, The request processing protocol conversion and memory management control state machine queries the ID lock unit according to the legal request of the memory management unit. If the same event ID operation is being executed, the request is shelved and executed after the ID is unlocked; If no same event ID operation is being executed, the request is executed and the ID of the request is locked.

10. The memory management communication interface for a network-on-chip and DDR controller of claim 5, wherein, The memory management response unit receives the memory management response information from the response processing protocol conversion control state machine, and the memory management response information comprises illegal operation information and legal operation information; The illegal operation information comprises: uninitialization for application, release, sharing and read-write operation; unapplication of memory blocks for release, sharing and read-write operation; insufficient space of the applied memory blocks, read-write operation out of bounds; insufficient space of the remaining DDR storage particles, failure of application of memory blocks; The legal operation information comprises: application success information; sharing success information; release success information.

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