Memory operation method and memory chip

Abstract

The application provides a memory operation method and a memory chip. The method comprises the following steps: obtaining an operation depth; wherein the operation depth is determined in wafer testing and stored in a storage unit; the operation depth represents a threshold voltage change level of the storage unit after operation; when the operation is performed, the operation depth is used for depth checking until the operation depth is reached. The application can accurately test the operation depth of the memory chip, and then guide the actual operation by using the operation depth, so as to achieve the purpose of accurately controlling the operation effect, and the problem that the threshold voltage of the storage unit becomes complex and uncontrollable can be avoided.

Description

Technical Field

[0001] This invention relates to the field of memory chip technology, and more specifically, to a memory operation method and a memory chip. Background Technology

[0002] Charge-trapping memory, also known as charge-trap memory, is an advanced storage technology. These memory chips utilize traps within the semiconductor material to capture and retain electrical charges (electrons or holes). When an erase or program operation is performed, the trap state of the memory cells changes. Newly injected charges may initially escape rapidly, but over time, the escape rate decreases exponentially. Eventually, the charge escape rate slows to a stable state, ensuring data stability.

[0003] However, it is precisely because of the uncertainty of charge escape that existing operating methods for memory chips such as charge-trapping flash memory, such as erase or program operations, are difficult to accurately control the depth of operation. This may cause the threshold voltage of the memory cell to fail to reach the expected level, and this uncontrollability may affect the performance of the memory chip. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a memory operation method and a memory chip that can pre-determine the depth information required for the memory chip to perform a specific operation, and can call upon this depth information during data operation to precisely control the operation depth, thereby avoiding the threshold voltage of the memory cell becoming complex and uncontrollable. To achieve the above objective, the technical solution adopted by this invention is as follows:

[0005] In a first aspect, the present invention provides a memory operation method applied to a memory chip, the memory chip including a plurality of memory cells, the method comprising: obtaining an operation depth; wherein the operation depth is determined in wafer testing and stored in the memory cells; the operation depth characterizes the threshold voltage change level of the memory cells after an operation is performed; when an operation is performed, a depth check is performed using the operation depth until the operation depth is reached.

[0006] In an optional implementation, when performing an operation, the operation depth is used for depth verification until the operation depth is reached. This includes: after obtaining the operation instruction, executing the operation indicated by the operation instruction multiple times on the storage unit to be operated on, and confirming after each operation whether the operation depth required by the operation has been reached; if not, then executing the next operation; otherwise, ending the operation.

[0007] In an optional implementation, obtaining the operation depth includes: performing a continuous operation process, and after completion, confirming whether a set reference depth value has been reached; if not, adjusting the reference depth value and repeating the continuous operation process; otherwise, stopping the test, and writing the current reference depth value as the operation depth corresponding to the operation process into the memory chip.

[0008] In an optional implementation, obtaining the operating depth further includes obtaining the operating depth of each individual die.

[0009] In an optional implementation, obtaining the operation depth further includes: if the operation process is an erasure process, then during the erasure process, the storage units are first adjusted to a unified logical state before the erasure operation is performed.

[0010] In an optional implementation, obtaining the operation depth further includes: if the operation process is a programming process, then during the programming process, the residual data in the storage unit is cleared first, and then the programming operation is performed.

[0011] In an optional implementation, obtaining the operation depth further includes: checking whether each operation position has been correctly operated after the operation process is completed.

[0012] In an optional implementation, when performing an operation, the operation depth is used for depth verification until the operation depth is reached. The method further includes: if the operation is an erase operation, the storage unit to be operated is pre-programmed after receiving the erase command.

[0013] In an optional implementation, when performing an operation, a depth check is performed using the operation depth until the operation depth is reached. The method further includes: after each operation is completed, a consistency check is performed on the data in the storage unit to be operated.

[0014] In a second aspect, the present invention provides a memory chip comprising a plurality of memory cells, the memory chip being used to perform a memory operation method as described in any of the foregoing embodiments.

[0015] The memory operation method and memory chip provided by this invention first obtain the operation depth, which is determined during wafer testing and stored in the memory cell. When performing an operation, the operation depth is used for depth verification until the operation depth is reached. This invention can pre-determine the depth information that the memory chip needs to reach when performing a specific operation, and can call this depth information during data operation to precisely control the operation depth, avoiding the threshold voltage of the memory cell from becoming complex and uncontrollable, thereby optimizing the overall performance of the memory chip.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic flowchart illustrating a memory operation method provided in an embodiment of the present invention;

[0019] Figure 2 A schematic flowchart of step S101 provided in an embodiment of the present invention;

[0020] Figure 3 This invention provides a schematic diagram illustrating the test erasure process and test programming process in wafer testing, for the purposes of embodiments of the present invention;

[0021] Figure 4 A schematic flowchart of step S102 provided in an embodiment of the present invention;

[0022] Figure 5 This is a schematic diagram illustrating the process of erasing and programming data provided in the embodiments of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0025] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0026] Considering that when performing one-time erase or programming operations, the threshold voltage of the memory cell may become unpredictable and uncontrollable due to the instability of charge escape, which in turn affects the performance of the entire memory chip.

[0027] To address this issue, this invention first proposes a wafer testing process. This process pre-determines the required change in the threshold voltage of each memory cell after completing a certain operation (e.g., erase or program operation) in the early stages of the memory chip's lifespan. This change, such as the erase depth or program depth, reflects the degree to which the threshold voltage of the memory cell decreases or increases after the erase or program operation. Furthermore, based on this pre-determined depth information, this invention also provides a memory operation method. In practical applications of memory chips, when a user performs a certain operation on the memory chip, the corresponding depth information can be used to precisely control the operation process, ensuring that the threshold voltage change of the memory cell remains within the expected range, thereby optimizing the performance of the memory chip.

[0028] This invention provides a memory operation method, the execution subject of which can be a memory chip, which can be, but is not limited to, charge-trapping flash memory. See also... Figure 1 , Figure 1 A schematic flowchart of a memory operation method provided in an embodiment of the present invention includes the following steps:

[0029] S101: Obtain the operation depth;

[0030] The operation depth is determined during wafer testing and stored in the memory cell; the operation depth characterizes the threshold voltage change level of the memory cell after the operation is performed.

[0031] S102: When performing an operation, use the operation depth to perform a depth check until the operation depth is reached.

[0032] The memory operation method provided in this invention first obtains the operation depth during wafer testing. When performing an operation, the operation depth is used for depth verification until the operation depth is reached. This invention can pre-determine the depth information that the memory chip needs to reach during operation and can call this depth information during data operation to precisely control the operation depth, avoiding the threshold voltage of the memory cell from becoming complex and uncontrollable, thereby optimizing the overall performance of the memory chip.

[0033] The steps S101 to S102 provided in the embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0034] In one embodiment of the present invention, the required change in the threshold voltage of each memory cell after a certain operation (e.g., erase or program operation) can be predetermined in the early stages of the memory chip development process. This could be the erase depth or programming depth. Furthermore, based on this predetermined depth information, the user can be guided to perform a specific operation on the memory chip, achieving precise operation and ensuring that the threshold voltage change of the memory cell remains within the expected range, thereby optimizing the performance of the memory chip.

[0035] Therefore, please see Figure 2 , Figure 2 This is a schematic flowchart illustrating step S101 provided in an embodiment of the present invention. In step S101, the wafer testing process provided in this embodiment of the present invention includes the following steps:

[0036] S101-1: Perform a continuous operation process, and after completion, confirm whether the set reference depth value has been reached;

[0037] The defined "continuous operation process" refers to the memory chip completing a predetermined type of data operation in one go, without interruption or pause. The defined "reference depth value" is a pre-configured initial depth value for the memory chip, which can be flexibly set by testers based on practical experience and is not limited here. As the operation process is repeated, this initial depth value will be continuously adjusted.

[0038] S101-2: If not, adjust the reference depth value and repeat the same operation process continuously; otherwise, stop the test, take the current reference depth value as the operation depth corresponding to the operation process, and write it into the memory chip.

[0039] In the wafer testing process provided in this embodiment of the invention, the entire testing process is precisely controlled by the memory chip. Through this implementation, data is read and verified immediately after each operation by the memory chip, significantly reducing waiting time. This ensures that the data during the testing process is not deviated due to transmission, guaranteeing the accuracy of the test results. Furthermore, once the memory chip determines the required depth information, it automatically stores this information internally. In subsequent user operations, this depth information can be quickly read to control the depth of the operation, thereby precisely managing the threshold voltage of the memory cells. This not only improves testing efficiency but also ensures the accuracy of the test results.

[0040] In one embodiment of the present invention, to ensure the smooth execution of the testing process, testers can complete a series of preparatory work in advance, including setting depth reference values, configuring a suitable testing environment, ensuring the memory chip is in optimal testing condition, and sending test commands to instruct the memory chip to initiate the entire process. For the memory chip, testing can be completed through a built-in self-test process, including performing specific operations, collecting necessary test data, verifying test results, and writing critical depth information into the chip.

[0041] In one embodiment of the present invention, the operating depth of each die can be obtained through the above-described wafer testing process, and their respective operating depths can be written into the chip, so that when users perform specific operations in actual applications, they only need to operate according to the preset depth.

[0042] In optional implementations, regarding the method of adjusting the reference depth value, the memory chip can flexibly design adjustment rules based on the difference between the actual measured operating depth and the reference depth value. For example, as an example, if the actual depth is lower than the reference value, an increment can be set, and the memory chip increases this increment each time it adjusts until the adjusted reference depth value is reached. Of course, exponential adjustment, adaptive adjustment, etc., can also be performed, and this embodiment of the invention does not limit the scope of the invention.

[0043] In one embodiment of the present invention, the operation process involved may be, but is not limited to, an erasing process, a programming process, etc. For example, if the operation process required for the memory chip is an erasing operation, then the test obtains the erasing depth that the memory chip needs to achieve when performing the erasing operation. Similarly, if it is a programming process, then the test obtains the programming depth that needs to be achieved when performing the programming operation. Specific erasing and programming processes can be found in the prior art, and will not be described in detail here.

[0044] In one embodiment of the present invention, when the operation referred to is an erase process, the memory chip can preprocess the memory cells to ensure that they are in a unified logical state. For example, as an example, the memory chip can write all zeros to the memory cells before performing the erase operation. This ensures that the erase process performed by the memory chip can be carried out on a consistent basis, improving the reliability of the erase operation.

[0045] Similarly, in one embodiment of the present invention, when the operation process is a programming process, the memory chip can first clear the residual data in the memory cell to be programmed before performing the programming process. For example, as an example, the memory chip can perform an erase operation on the memory cell to be programmed to ensure that all data bits are completely cleared before performing a one-time programming operation, thereby avoiding any potential data interference and ensuring the success rate of the programming operation.

[0046] In one embodiment of the present invention, the memory chip may also check whether each operation position has been operated correctly after the operation process is completed. This not only improves the accuracy and reliability of the entire operation process, but also helps to detect and correct possible errors in a timely manner.

[0047] Of course, it is understandable that if the operation in question involves other types of operations, then preprocessing steps that help the operation can be adaptively performed on the storage unit to optimize the state of the storage unit and make it more suitable for the specific operation to be performed, thereby improving the accuracy of the operation.

[0048] To facilitate a comprehensive understanding of the above embodiments, the following example, using an erase operation and a programming operation as examples, clearly illustrates the wafer testing process provided by the embodiments of the present invention. Please refer to... Figure 3 , Figure 3 This is a schematic diagram illustrating the test erasure process and test programming process in wafer testing, provided as an embodiment of the present invention.

[0049] exist Figure 3 In the illustrated process, when a memory chip performs an erase operation, it first needs to set an initial erase reference depth value. Subsequently, the memory chip repeats the erase process, with each execution following these steps: First, the memory chip writes all zeros into the memory cell; next, the memory chip performs a one-time erase on the memory cell; then, the memory chip checks whether the set erase reference depth value has been reached. If not, the memory chip adjusts the erase reference depth value and returns to the step of writing all zeros, iterating in this loop. Once the memory chip reaches the adjusted erase reference depth value after completing an erase operation, the test stops, and the memory chip writes the current erase reference depth value internally. The programming process is similar and will not be described in detail here.

[0050] pass Figure 3 It is clear that as the erasing and programming process progresses, the memory chip will continuously perform depth verification until it reaches the preset reference depth value. After the test passes, the obtained reference depth value will be stored inside the chip for later retrieval and calibration in subsequent operations.

[0051] Based on the operational depth obtained during wafer testing, during the execution of step S102, this embodiment of the invention provides the following... Figure 4 The implementation method shown, Figure 4 A schematic flowchart of step S102 provided in the embodiments of the present invention may include the following process:

[0052] S102-1: After obtaining the operation instruction, execute the operation indicated by the operation instruction multiple times on the memory unit to be operated, and confirm whether the required operation depth has been reached after each operation;

[0053] In this embodiment of the invention, executing the operation in multiple steps can be understood as the memory chip, after receiving an operation instruction, dividing the entire operation process into multiple executions, gradually completing them within a limited operation time. Each time the memory chip completes an operation, it needs to perform an operation depth verification. This is fundamentally different from the one-time operation used in wafer testing, where the memory chip completes the entire operation at once before performing operation depth verification.

[0054] It is understandable that after receiving an operation instruction, the memory chip can first read the operation depth corresponding to the operation that is pre-stored inside the chip, so as to quickly perform depth verification later.

[0055] S102-2: If not, proceed to the next operation; otherwise, end the operation.

[0056] During steps S102-1 to S102-2, after the memory chip receives the operation instruction, the entire operation is divided into multiple executions. After each operation, the memory chip checks whether the required operation depth has been reached. If it has, the memory chip stops the operation; otherwise, the memory chip continues to execute the next operation. This achieves precise control of the operation depth and avoids the problem of the memory cell threshold voltage becoming complex and uncontrollable.

[0057] In one embodiment of the present invention, the operations performed by the memory chip may include, but are not limited to, erasing operations, programming operations, etc.

[0058] In one embodiment of the present invention, when the memory chip receives an operation instruction, it can first read the operation depth corresponding to the operation indicated by the operation instruction from the memory cell, and then only need to perform the operation according to the operation depth, which achieves the effect of optimizing the operation result.

[0059] In one embodiment of the present invention, if the memory chip receives an erase command, after receiving the erase command, the memory chip first pre-programs the memory cells to be operated on. Pre-programming is performed by using a weak programming operation to program the state of the memory cells to be operated on to a weakly programmed state, so that the initial states of these memory cells are more similar. The specific pre-programming process can be found in the prior art and will not be described in detail here.

[0060] In one embodiment of the present invention, after each operation, the memory chip can also perform a consistency check on the data in the memory cell to be operated on. For example, taking an erase operation as an example, the memory chip can check whether the erase effect meets the expected result. The expected result here can mean that there are no areas that have not been erased or have not been erased completely.

[0061] To facilitate a comprehensive understanding of the above embodiments, the following examples of erasing and programming operations clearly illustrate the data processing process provided by the embodiments of the present invention. Please refer to... Figure 5 , Figure 5 This is a schematic diagram illustrating the process of erasing and programming data provided in the embodiments of the present invention.

[0062] exist Figure 5 In this process, after receiving an erase command, the memory chip reads the erase depth pre-stored inside the chip. Next, the memory chip pre-programs the memory cell to be erased. Then, the memory chip performs an erase operation on the memory cell, verifying whether the read erase depth has been reached. If so, the erase operation ends; otherwise, it returns to the step of performing the erase operation on the memory cell to be erased. Similarly, after receiving a programming command, the memory chip reads the programming depth pre-stored inside the chip, then performs a programming operation on the memory cell to be programmed, verifying whether the read programming depth has been reached. If so, the memory chip ends the programming operation; otherwise, it returns to the step of performing the programming operation on the memory cell to be erased.

[0063] from Figure 5 It can be clearly seen that the memory chip performs erase or program operations on the memory cell multiple times, and verifies the result of each erase or program operation. This achieves the purpose of controlling the erase depth or program depth and avoids the risk of uncontrollable threshold voltage of the memory cell after erase or program.

[0064] In summary, the embodiments of the present invention have the following significant advantages: First, in the early stages of the memory chip development process, the embodiments of the present invention can accurately determine the depth information required by the memory chip to perform a specific operation during wafer testing, and write this information into the chip for subsequent operation calls. Second, when performing a specific operation in the memory cell of the memory chip, the embodiments of the present invention adopt a staged execution strategy, checking whether the pre-stored depth information has been reached after each operation. If it has been reached, the operation can be terminated; if not, the next operation continues until the set depth information is met. This method can effectively control the operation depth, ensuring that the threshold of the memory cell is maintained at the expected level, thereby optimizing the overall performance of the memory chip.

[0065] This invention also provides a memory chip. It should be noted that this invention provides a memory chip that shares the same concept as the memory operation method performed by the memory chip in the above embodiments. The specific implementation process is detailed in the method embodiments and will not be repeated here. This invention first obtains the operation depth; wherein the operation depth is determined during wafer testing and stored in the memory cell; the operation depth characterizes the threshold voltage change level of the memory cell after the operation is performed; when the operation is performed, the operation depth is used for depth verification until the operation depth is reached. This effectively controls the operation depth, ensuring that the threshold voltage of the memory cell remains at the expected level, thereby optimizing the overall performance of the memory chip.

[0066] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0067] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0068] If the functionality is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention.

[0069] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A memory operation method, characterized in that, Applied to a memory chip, the memory chip comprising multiple memory cells, the method includes: Obtaining the operating depth includes: performing a continuous operation process, and after completion, confirming whether a set reference depth value has been reached; if not, adjusting the reference depth value and repeating the continuous operation process; otherwise, stopping the test, and writing the current reference depth value as the operating depth corresponding to the operation process into the memory chip; wherein, the operating depth is determined during wafer testing and stored in the memory cell; the operating depth characterizes the threshold voltage change level of the memory cell after the operation is performed; When an operation is performed, a depth check is performed using the operation depth until the operation depth is reached.

2. The memory operation method according to claim 1, characterized in that, During operation, a depth check is performed using the operation depth until the operation depth is reached, including: After receiving the operation instruction, the operation indicated by the operation instruction is executed multiple times on the storage unit to be operated. After each operation, it is confirmed whether the operation depth required by the operation has been reached. If not, perform the operation again; otherwise, end the operation.

3. The memory operation method according to claim 1, characterized in that, Obtaining operational depth also includes: Obtain the operating depth for each bare die.

4. The memory operation method according to claim 1, characterized in that, Obtaining operational depth also includes: If the operation is an erasure process, the storage units are first adjusted to a unified logical state before the erasure operation is performed.

5. The memory operation method according to claim 1, characterized in that, Obtaining operational depth also includes: If the operation process is a programming process, then during the programming process, the residual data in the storage unit is cleared first, and then the programming operation is performed.

6. The memory operation method according to claim 1, characterized in that, Obtaining operational depth also includes: After the operation process is completed, check whether each operation position has been operated correctly.

7. The memory operation method according to claim 1, characterized in that, When performing an operation, a depth check is performed using the operation depth until the operation depth is reached. The process also includes: If the operation is an erase operation, the memory unit to be operated on is pre-programmed after receiving the erase command.

8. The memory operation method according to claim 1, characterized in that, When performing an operation, a depth check is performed using the operation depth until the operation depth is reached. The process also includes: After each operation is completed, a consistency check is performed on the data in the storage unit to be operated on.

9. A memory chip, characterized in that, The memory chip includes a plurality of memory cells, and the memory chip is used to perform the memory operation method as described in any one of claims 1-8.

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