A memory chip data error correction method and system

Abstract

The application relates to the technical field of data error correction of storage chips, and discloses a data error correction method and system for a storage chip, wherein the method is characterized in that data processing priority information associated with data in the storage chip is acquired, and differential correction processing is performed on data errors according to the priority information, so that the problems that the traditional error correction method in the prior art is insufficient in the face of complex and changeable error modes and a large amount of system resources is consumed by frequent error processing are effectively solved.

Description

Technical Field

[0001] This invention relates to the field of data error correction technology for memory chips, and more specifically, to a method and system for correcting data errors in memory chips. Background Technology

[0002] Memory chips play a crucial role in various electronic devices, responsible for storing important programs and data. However, in practical applications, especially in harsh operating environments, memory chips may encounter various data errors. These errors can be caused by factors such as temperature variations, electromagnetic interference, chip aging and wear, or unstable power supply. Traditional error correction techniques, such as common error-correcting codes (ECC), can handle some simple, randomly occurring errors, but their capabilities are often insufficient when faced with complex and varied error patterns. When errors become frequent, exhibit specific patterns, or occur with critical data, traditional error correction methods may not only fail to effectively repair them but may also consume significant system resources due to frequent error handling, potentially impacting the normal operation and lifespan of the device.

[0003] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0004] This invention provides a method and system for correcting data errors in memory chips, aiming to solve the problem that traditional error correction codes are unable to effectively identify and correct intermittent, pattern-dependent data errors caused by memory chip aging and unstable power supply in long-term operation environments with unstable power supply, thereby affecting the data integrity, system stability and energy efficiency of the device.

[0005] The technical solution of this application is as follows: In a first aspect, this application discloses a method for correcting data errors in a memory chip, comprising: Obtain data processing priority information associated with data in the memory chip; Based on data processing priority information, differentiated correction processing is performed on data errors in the memory chip. This differentiated correction processing includes: When the data processing priority information indicates that the data has the first processing priority, the first correction process is performed. The first correction process is to decode the data using an encoding method that corrects multiple bit errors. If decoding fails, the data is read multiple times by adjusting the reading parameters. When the data processing priority information indicates that the data has the second processing priority, the second correction process is executed. The second correction process is to perform an integrity check on the data. If the integrity check finds an error, the data repair is abandoned.

[0006] This technical solution enables differentiated correction of data errors in memory chips based on different data processing priorities, thereby ensuring the reliability of critical data while optimizing resource utilization and improving the overall system's energy efficiency and stability.

[0007] Furthermore, based on the above, when decoding fails, the data is read multiple times by adjusting the reading parameters, including: Obtain the indication information for data decoding failure; In response to a data decoding failure indication, a dual-threshold alternating read sequence is initiated. The dual-threshold alternating read sequence includes: Within a preset time window, the reading voltage is lower than the preset standard reading voltage and higher than the preset standard reading voltage; By comparing the differences at the same bit position in the two data reads, bit difference information is obtained; Based on the bit difference information, determine whether the data error is a transient logic jitter mode; If so, then stop reading and adjusting the parameters; Obtain the correct version of the data from the backup area; Write the correct version of the data to the healthy area of ​​the storage chip.

[0008] This technical solution enables multiple attempts to resolve decoding failures by adjusting reading parameters and combining alternating reading sequences with dual thresholds and bit difference information to determine instantaneous logic jitter patterns. This allows for more accurate identification and repair of complex data errors, thereby improving the success rate of data recovery.

[0009] Furthermore, in some preferred embodiments, when the data processing priority information indicates that the data has a first processing priority, a first correction process is performed, including: Obtain the indication information for data decoding failure; Assess the instantaneous power supply capability of the current device; When the instantaneous power supply capacity is lower than the preset threshold, data error correction processing is paused. During the pause, low-power operation is performed; When the instantaneous power supply capacity recovers to above the preset threshold, the data error correction process is restarted. A phased error correction strategy is adopted to perform error correction on the data. The phased error correction strategy includes: The data is decoded using an encoding method capable of correcting multiple bit errors; When decoding fails, the data is read multiple times by adjusting the reading parameters, and an interval is set between the reading attempts. Record the delay in data error correction processing; Send a warning message.

[0010] This technical solution enables dynamic adjustment of the error correction strategy based on the instantaneous power supply capacity. When power supply is insufficient, error correction is paused and a low-power mode is entered, effectively avoiding error correction failure and system instability caused by insufficient power supply. At the same time, through phased error correction and delayed recording, error correction efficiency and system response are further optimized.

[0011] Preferably, when the instantaneous power supply capacity is lower than a preset threshold, the data error correction process is paused, including: Obtain the pause instruction information for data error correction processing; Identify whether there are time-sensitive data segments in the data blocks that have been suspended from error correction; When time-sensitive data segments exist, obtain the correct version of the time-sensitive data segments; When the correct version of a time-sensitive data segment cannot be obtained, perform an integrity check on the time-sensitive data segment. Based on the integrity check results, process the time-sensitive data segments; Send instruction information.

[0012] This technical solution enables the priority identification and processing of time-sensitive data segments during error correction, ensuring the timeliness and integrity of critical data and preventing the loss or invalidation of important data due to the pause in error correction.

[0013] Based on the above, when the instantaneous power supply capacity is lower than a preset threshold, the data error correction process is paused, including: Obtain indication information that the instantaneous power supply capability is continuously lower than a preset threshold; The microcontroller is periodically woken up in response to indications. Upon wake-up, assess the current power supply's instantaneous power delivery capability; When the instantaneous power supply capacity is still lower than the preset threshold, perform a minimum strength error correction attempt on the first priority data block that has been suspended. Record the error correction pause duration for the first priority data block; When the error correction pause duration exceeds the preset maximum allowable pause duration, a high-intensity error correction attempt will be forcibly executed. Send an emergency alert.

[0014] This technical solution addresses situations where the instantaneous power supply capacity is consistently insufficient by introducing periodic wake-up and minimum strength error correction attempts. When the pause duration is too long, high strength error correction is forcibly executed. This ensures low power consumption while preventing data from being in an erroneous state for extended periods, thus improving the timeliness and reliability of data recovery.

[0015] As a technical improvement, when the error correction pause duration exceeds the preset maximum allowable pause duration, a high-intensity error correction attempt is forcibly executed, including: Obtain the voltage ripple amplitude information of the power supply; Based on the voltage ripple amplitude information, adjust the execution timing of high-intensity error correction attempts so that high-power operations avoid the peak moments of power supply ripple; Activate the instantaneous energy buffer unit to provide additional instantaneous power supply during error correction operations; Monitor the instantaneous power supply capability; When a downward trend in power supply capacity is detected, reduce the intensity of error correction operations or suspend non-critical error correction subtasks.

[0016] This technical solution can effectively address the challenges posed by power instability by acquiring voltage ripple amplitude information, adjusting execution timing, and activating an instantaneous energy buffer unit, ensuring the success rate of high-intensity error correction attempts. At the same time, it further optimizes power consumption management through dynamic monitoring and adjustment.

[0017] As a further improvement, when the instantaneous power supply capacity is lower than a preset threshold, data error correction processing is paused, including: Obtain the pause instruction information for data error correction processing; Monitor the triggering of external emergency commands or critical events; When an external emergency command or critical event is detected, assess the response priority of the external emergency command or critical event; The pause strategy for data error correction processing is dynamically adjusted based on response priority. This dynamic adjustment includes: When the response priority indicates that an immediate response is required, the instantaneous energy buffer unit is activated, and the response operation for the emergency command or critical event is performed with limited power consumption. When the response priority indicator allows for a delayed response, the data error correction process remains paused, and the delay information for emergency instructions or critical events is recorded. During emergency command or critical event response operations, continuously monitor the instantaneous power supply capacity; When a decreasing trend in the instantaneous power supply capacity is detected, the intensity of emergency command or critical event response operations will be further reduced.

[0018] This technical solution enables the dynamic adjustment of the data error correction processing pause strategy based on the priority of external emergency commands or critical events, ensuring that the system can still respond to high-priority events in a timely manner even in a low-power state. At the same time, it balances emergency response and energy consumption management through instantaneous energy buffering and power consumption limiting.

[0019] Based on the above, when the response priority indication requires an immediate response, the instantaneous energy buffer unit is activated, and emergency command or critical event response operations are performed with limited power consumption, including: Before activating the instantaneous energy buffer unit, a health status assessment of the instantaneous energy buffer unit is performed. The health status assessment includes: A preset test discharge pulse is applied to the instantaneous energy buffer unit; Monitor the voltage drop rate of the instantaneous energy buffer unit under the action of a test discharge pulse; The instantaneous energy release efficiency of the instantaneous energy buffer unit is determined based on the voltage drop rate. When the instantaneous energy release efficiency is lower than the preset standard, the instantaneous energy buffer unit undergoes a pre-charge activation process, which includes: The instantaneous energy buffer unit is subjected to multiple charge-discharge cycles using a controlled current; After the pre-charge activation process is completed, the instantaneous energy release efficiency of the instantaneous energy buffer unit is evaluated again; When the instantaneous energy release efficiency is still lower than the preset standard, a fault alarm is triggered in the transmission buffer unit. Once the instantaneous energy release efficiency meets the preset standard, the instantaneous energy buffer unit is activated, and emergency commands or critical event response operations are executed with limited power consumption.

[0020] This technical solution enables the health status assessment and pre-charge activation of the instantaneous energy buffer unit before its activation, ensuring that the buffer unit can provide reliable instantaneous power supply in emergency situations, thereby improving the reliability and stability of the system in response to sudden events.

[0021] As a functional enhancement, after the pre-charge activation process is completed, the instantaneous energy release efficiency of the instantaneous energy buffer unit is re-evaluated, including: Retrieve emergency instructions received by the system; When an emergency command is received, the current evaluation process of the instantaneous energy release efficiency of the instantaneous energy buffer unit is interrupted; According to the preset emergency response strategy, the instantaneous energy buffer unit is activated; Record the current evaluation status of the buffer unit and the response time of emergency commands; After the emergency command response is completed, the evaluation of the instantaneous energy release efficiency of the instantaneous energy buffer unit continues in low-power mode.

[0022] This technical solution enables priority response to emergency commands when they arrive, interrupting the evaluation process of the buffer unit, and resuming evaluation after the emergency response is completed. This ensures the system's ability to respond quickly to emergency events while also taking into account the health status management of the buffer unit.

[0023] Secondly, this application also discloses a memory chip data error correction system, comprising: The input terminal is used to obtain data processing priority information associated with the data in the memory chip. The processing unit is used to perform differentiated correction processing on data errors in the memory chip based on data processing priority information. The differentiated correction processing includes: When the data processing priority information indicates that the data has the first processing priority, the first correction process is performed. The first correction process is to decode the data using an encoding method that corrects multiple bit errors. If decoding fails, the data is read multiple times by adjusting the reading parameters. When the data processing priority information indicates that the data has the second processing priority, the second correction process is executed. The second correction process is to perform an integrity check on the data. If the integrity check finds an error, the data repair is abandoned.

[0024] This technical solution enables differentiated correction of data errors in memory chips based on different data processing priorities, thereby ensuring the reliability of critical data while optimizing resource utilization and improving the overall system's energy efficiency and stability. Beneficial effects

[0025] The memory chip data error correction method and system disclosed in this application effectively solve the problems of insufficient capability of traditional error correction methods in the face of complex and ever-changing error modes, and the consumption of a large amount of system resources by frequent error processing, by obtaining data processing priority information associated with data in the memory chip and performing differentiated correction processing on data errors according to the priority information.

[0026] Specifically, when data is identified as having the highest processing priority, the system employs an encoding method that corrects multiple bit errors for decoding. If decoding fails, multiple read attempts are made by adjusting the reading parameters. This significantly improves the ability to repair complex, intermittent errors, avoiding data loss or system instability caused by the inability to correct errors, as is common with traditional methods. When data is identified as having the second highest processing priority, the system only performs an integrity check and abandons repair attempts upon finding errors. This strategy avoids time-consuming and potentially ineffective repair attempts on non-critical data, effectively saving system resources and power consumption, making it particularly suitable for low-power IoT devices. Through this differentiated processing mechanism, this application can optimize the overall system's energy efficiency and stability while ensuring the reliability of critical data. It overcomes the shortcomings of existing technologies in handling complex data errors caused by aging storage chips and unstable power supplies, achieving efficient identification and correction of data errors without significantly increasing hardware resources and power consumption, thereby extending device lifespan and improving data integrity. Attached Figure Description

[0027] Figure 1 This is a flowchart illustrating a data error correction method for a memory chip provided in an embodiment of the present invention; Figure 2 This is a flowchart of a method for adjusting reading parameters to attempt to read data multiple times, provided by an embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of a memory chip data error correction system provided in an embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Reference Figure 1 , Figure 1 This is a flowchart illustrating a data error correction method for a memory chip provided in an embodiment of the present invention, including: S11, Obtain data processing priority information associated with data in the memory chip; S12, based on data processing priority information, perform differentiated correction processing on data errors in the memory chip. The differentiated correction processing includes: When the data processing priority information indicates that the data has the first processing priority, the first correction process is performed. The first correction process is to decode the data using an encoding method that corrects multiple bit errors. If decoding fails, the data is read multiple times by adjusting the reading parameters. When the data processing priority information indicates that the data has the second processing priority, the second correction process is executed. The second correction process is to perform an integrity check on the data. If the integrity check finds an error, the data repair is abandoned.

[0030] This application aims to provide a data error correction method for memory chips to address complex data errors that occur during long-term operation and under unstable power supply environments. This method introduces data processing priority information to perform differentiated correction processing on data of varying importance, thereby optimizing system resource consumption while ensuring the reliability of critical data.

[0031] Specifically, the "data processing priority information" mentioned in this application refers to an identifier associated with data in the memory chip, used to indicate the importance or timeliness of the data. For example, critical data such as system firmware and calibration parameters can be assigned "first processing priority," while log files and non-critical sensor data can be assigned "second processing priority." This priority information can be pre-stored in a specific area of ​​the memory chip or dynamically generated by the system controller based on the data type and application scenario.

[0032] "First priority processing" typically refers to data with extremely high requirements for integrity and availability, such as system startup code, critical configuration parameters, or financial transaction data. Errors in this type of data can lead to system crashes, functional failures, or significant losses, thus requiring the highest level of error correction protection.

[0033] "Secondary processing priority" typically refers to data with relatively low requirements for data integrity, or data that can tolerate a certain degree of data loss, such as historical logs, non-critical sensor readings, or cached data. For this type of data, excessive resources may not be cost-effective for repair, and may even affect the overall system performance due to delays in the repair process.

[0034] "Encoding methods for correcting multiple bit errors" refers to advanced error-correcting codes, such as BCH codes and LDPC codes. Compared to traditional single-bit error-correcting codes (such as Hamming codes), they have stronger error-correcting capabilities and can correct errors in multiple bits of a data block simultaneously. This encoding method is used when data is written to the memory chip and is used for decoding to detect and correct errors when data is read.

[0035] "Adjusting read parameters" refers to attempting to reread data under different physical conditions by changing parameters such as read voltage, read timing, and reference voltage when reading data from a memory chip. This is because the threshold voltage distribution of memory cells may change due to aging or interference. By adjusting the read parameters, data that could not be correctly identified due to threshold voltage shifts can sometimes be successfully read.

[0036] "Integrity checking" refers to verifying whether data has been corrupted during transmission or storage using methods such as checksums and cyclic redundancy checks (CRC). This type of check typically requires less computation than decoding error-correcting codes, but it can only detect errors and cannot correct them.

[0037] The memory chip data error correction method of this application first obtains data processing priority information associated with the data in the memory chip. This priority information can be marked by the system when data is written, for example, by adding a priority field to the metadata of the data block, or by implicitly determining its priority based on the data storage area. For example, the area storing system firmware is set to the first processing priority by default, while the area storing user logs is set to the second processing priority.

[0038] Based on the acquired data processing priority information, the system performs differentiated correction processing for data errors in the memory chip. Specifically, when the data processing priority information indicates that the data has the highest processing priority, the system performs the first correction process. The first correction process begins by decoding the data using an encoding method that corrects multiple bit errors. For example, when reading a data block from the memory chip, if the data block is marked as having the highest processing priority, the memory controller will use a preset error-correcting code (such as an LDPC code) capable of correcting multiple bit errors to decode the read data. If decoding is successful, the data is considered correct; if decoding fails, meaning the error-correcting code cannot correct all detected errors, the system will not immediately abandon the attempt but will instead attempt to read the data multiple times by adjusting the read parameters. For example, the controller may attempt to reread the data at a threshold slightly higher or lower than the standard read voltage, or change the read timing to successfully acquire the data under different read conditions. This multiple-attempt approach aims to overcome edge errors caused by memory cell aging, charge leakage, or transient noise, thereby improving the success rate of critical data recovery.

[0039] When data processing priority information indicates that data has a second processing priority, the system performs a second correction process. This second correction process involves performing an integrity check on the data. For example, for a data block marked as having a second processing priority, the system performs a quick integrity check after reading it, such as calculating its CRC checksum and comparing it with a stored checksum. If the integrity check finds an error, i.e., a checksum mismatch, the system immediately abandons the attempt to repair the data. This is because data with a second processing priority is not important enough to support a complex, high-power error correction attempt. Abandoning the repair saves system resources, avoids unnecessary latency and power consumption, and thus maintains low-power operation of the device.

[0040] Through the aforementioned differentiated correction processes, this application effectively balances data reliability and system resource consumption. For critical data, even in the event of complex errors, the system will strive to repair it using multi-bit error correction and adjustment of reading parameters to ensure its integrity. For non-critical data, a strategy of rapid inspection and timely abandonment is adopted to avoid wasting resources on unnecessary data repair.

[0041] The memory chip data error correction method of this application effectively solves the problem that traditional error correction codes are insufficient when facing complex multi-bit errors by introducing data processing priority information and performing differentiated correction processing on data errors in the memory chip according to the information.

[0042] In summary, this application, by introducing data processing priorities and performing differentiated correction processes accordingly, not only improves the efficiency and success rate of data error correction in memory chips but also achieves refined management of resource consumption. This method demonstrates significant technological progress and innovation in ensuring the reliability of critical data, improving system stability, and optimizing energy efficiency.

[0043] Traditional data error correction methods for existing memory chips typically involve adjusting read parameters to attempt multiple reads when data decoding fails. However, this general approach may not be efficient in handling all types of errors, especially those caused by transient logic jitter. Simple parameter adjustments are often ineffective in such cases, potentially leading to excessively long recovery times or even failure to recover data, thus impacting the performance and reliability of the storage system.

[0044] In this regard, refer to Figure 2 , Figure 2 This is a flowchart of a method for adjusting reading parameters to attempt multiple reads of data according to an embodiment of the present invention. S12 includes: S121, Obtain the indication information of data decoding failure; S122, in response to the indication information of data decoding failure, a dual-threshold alternating read sequence is initiated, the dual-threshold alternating read sequence comprising: S123, within a preset time window, read the voltage at a level lower than the preset standard and a level higher than the preset standard; S124, compare the differences between the two data read results at the same bit position to obtain bit difference information; S125, Based on the bit difference information, determine whether the data error is a momentary logic jitter mode; S126, if so, then stop reading the parameter adjustment; S127, Obtain the correct version of the data from the backup area; S128, Write the correct version of the data into the healthy area of ​​the storage chip.

[0045] Specifically, a data decoding failure indication refers to a signal or state generated when the decoder cannot successfully recover the original data after decoding it using an encoding method that corrects multiple bit errors. This indication is typically issued by the decoding module to notify the system that the current data block contains errors that cannot be corrected by conventional error correction codes. In response to the data decoding failure indication, the system initiates a dual-threshold alternating read sequence. The dual-threshold alternating read sequence is an advanced read strategy designed to detect potential transient or edge errors by reading data at different voltage thresholds.

[0046] Specifically, within a preset time window, the memory chip controller first performs a data read at a voltage lower than the preset standard read voltage, and then performs another data read at a voltage higher than the preset standard read voltage. This alternating read method amplifies bit differences caused by voltage fluctuations or cell state instability. After completing two data reads at different voltage thresholds, the system compares the differences between the two data reads at the same bit position to obtain bit difference information.

[0047] For example, if a bit is read as "0" below the standard voltage but as "1" above the standard voltage, it indicates that the bit may be unstable or in a critical state. Based on this bit difference information, the system determines whether the data error is a transient logic jitter pattern. A transient logic jitter pattern refers to data exhibiting an unstable logical state in the storage unit, potentially jumping randomly between "0" and "1" within a short period. This type of error is usually difficult to capture through a single read attempt or simple parameter adjustments. If the bit difference information exhibits randomness, inconsistency, or a specific pattern, it can be inferred to be a transient logic jitter pattern.

[0048] If the error is identified as a transient logic jitter pattern, adjustments to the read parameters are stopped. This is because simply adjusting read parameters (such as voltage and timing) is often ineffective for transient logic jitter errors and may even waste system resources and time. In this case, the system retrieves the correct version of the data from the backup area. The backup area is a reserved area in the memory chip used to store copies of important data in case of unrecoverable errors in the primary data area. Retrieving the correct version is the ultimate means of ensuring data integrity.

[0049] Finally, the correct version of the data is written to the healthy area of ​​the memory chip. The healthy area refers to a verified, high-performing memory cell area within the memory chip that is free of significant defects. By writing the correct data to the healthy area, damaged data blocks can be effectively replaced, thereby restoring data availability and reliability.

[0050] This application's solution effectively addresses the inefficiency or unrecoverable nature of traditional methods when facing complex errors such as transient logic jitter by introducing intelligent judgment and targeted processing of error patterns after data decoding failure. Through this technical solution, the application significantly improves the correction capability and efficiency of memory chips when facing complex data errors, especially transient logic jitter errors. Compared to the basic approach of simply adjusting read parameters and making multiple attempts, this application introduces an intelligent error pattern recognition mechanism, avoiding ineffective parameter adjustments for unsuitable error types, thus saving valuable system resources and time. Specifically, the introduction of a dual-threshold alternating read sequence enables the system to more sensitively capture transient and edge-type errors that are difficult to detect using traditional single read methods, improving the accuracy of error diagnosis. Once a transient logic jitter pattern is identified, parameter adjustments are immediately stopped and the correct data is retrieved from the backup area. This decision-making mechanism greatly shortens data recovery time and ensures a high success rate for data recovery, effectively avoiding further data corruption or system performance degradation that may result from repeated attempts. Therefore, the solution proposed in this application optimizes the error correction process and improves the overall robustness of the storage system while ensuring data integrity and reliability.

[0051] In some preferred embodiments, a specific example is illustrated below. Suppose that when a data block in a memory chip is read and undergoes error correction decoding, the decoder reports a decoding failure. The system first receives an indication of this data decoding failure. In response to this indication, the memory controller initiates a dual-threshold alternating read sequence. For example, the preset standard read voltage is 1.5V. Within a preset time window, the controller first reads the data block at 1.4V (below the standard), obtaining the first read result. Subsequently, it reads the data block again at 1.6V (above the standard), obtaining the second read result. Next, the system compares the differences between these two read results at each bit position. Suppose that at a certain bit position, the first read result is "0", while the second read result is "1". This inconsistency is recorded as bit difference information. If multiple bit positions exhibit similar random or irregular differences, the system determines the current data error to be a transient logic jitter mode based on a preset algorithm and thresholds. Once a transient logic jitter mode is determined, the system immediately stops any further attempts to adjust read parameters, as this type of error is known to be difficult to resolve through parameter adjustments. At this point, the system will then search for and retrieve the correct version of the data block from the reserved backup area of ​​the storage chip. For example, the correct version of the data block may have been synchronously copied to the backup area when the system performed data writing. After retrieving the correct version, the system will write the correct version of the data to a health-checked, defect-free storage area within the storage chip to replace the original damaged data block. In this way, even if the original data block is affected by momentary logical jitter, the data can be quickly and reliably recovered, thereby ensuring data integrity and stable system operation.

[0052] In some embodiments described above in this application, when the data processing priority information indicates that the data has a first processing priority, a first correction process is performed. This process includes decoding the data using an encoding method that corrects multiple bit errors, and attempting to read the data multiple times by adjusting the reading parameters if decoding fails. However, in its implementation, these intensive error correction operations may place a significant burden on the device's instantaneous power supply capability, especially when the power supply is unstable or limited, which may lead to inefficient error correction or even failure, affecting data reliability.

[0053] In this regard, this application further proposes that when the data processing priority information indicates that the data has a first processing priority, the steps for performing the first correction processing include: Obtain the indication information for data decoding failure; Assess the instantaneous power supply capability of the current device; When the instantaneous power supply capacity of the power source is lower than a preset threshold, the data error correction process is suspended. During the pause, low-power operation is performed; When the instantaneous power supply capability of the power supply recovers to above the preset threshold, the data error correction process is restarted. A phased error correction strategy is employed to perform error correction processing on the data. The phased error correction strategy includes: The data is decoded using an encoding method capable of correcting multiple bit errors; If the decoding fails, the data is read multiple times by adjusting the reading parameters, and an interval is set between the reading attempts. Record the delay in the data error correction process; Send a warning message.

[0054] Specifically, the data decoding failure indication message refers to a signal or state generated when the system fails to successfully recover the original data during its attempt to decode it. Meanwhile, assessing the instantaneous power supply capability of the current device can be understood as monitoring parameters such as power supply voltage, current, and power consumption to determine in real time the device's ability to provide sufficient power to support high-power operation within a short period.

[0055] In practical applications, this can be achieved through a built-in power management unit or dedicated sensors. When the instantaneous power supply capacity falls below a preset threshold, pausing data error correction processing means that when the evaluation results indicate that the power supply capacity is insufficient to safely and efficiently perform error correction, the system will temporarily halt the current error correction task. The preset threshold can be dynamically or statically set based on factors such as device hardware specifications, battery status, and system load. During the pause, low-power operation means that to save energy and wait for power recovery, the device will enter a lower-power operating mode, such as shutting down some non-critical modules or reducing the clock frequency. When the instantaneous power supply capacity recovers to above the preset threshold, restarting data error correction processing means that once the power supply returns to a safe level, the paused error correction task will continue.

[0056] Furthermore, a phased error correction strategy is employed to process the data. This is a more refined error correction method designed to balance error correction effectiveness and resource consumption. Specifically, this strategy includes: First, decoding the data using an encoding method capable of correcting multiple bit errors. This is the first phase, utilizing powerful error correction codes (such as LDPC, BCH, etc.) to attempt to correct multiple bit errors at once. When decoding fails, multiple read attempts are made by adjusting the read parameters, with an interval set between these attempts. This is the second phase. When decoding fails in the first phase, a new read attempt is not immediately made; instead, an interval is set. Adjusting the read parameters may include changing the read voltage, timing, reference level, etc. Setting an interval helps with power recovery and avoids continuous high-power operation. Additionally, recording the delay in the data error correction processing refers to recording the extra time incurred due to power issues causing pauses or phased execution of the error correction process, for subsequent analysis or system optimization. Sending warning messages means issuing alerts to the system or user when delays occur in the error correction process or when power supply is insufficient, so that timely measures can be taken.

[0057] This application's solution effectively addresses the inefficiency or failure issues that may arise from unstable power supply during high-intensity data error correction processing by introducing the assessment and management of the device's instantaneous power supply capability. Through this technical solution, the robustness and reliability of memory chip data error correction are significantly improved, especially in operating environments with unstable or limited power supply. By real-time assessment of the instantaneous power supply capability and dynamic adjustment of the error correction strategy, blindly executing high-power error correction operations when power is insufficient is avoided, effectively preventing error correction failures or system instability caused by power supply issues. The phased error correction strategy and the interval setting between read attempts further optimize power management, reduce instantaneous current surges, and extend the effective operating time of the device under low or unstable power conditions. Furthermore, the introduction of delay recording and early warning mechanisms enables the system to better monitor and manage the data error correction process, promptly detect and respond to potential power or data risks, thereby optimizing the overall energy efficiency and user experience of the device while ensuring data integrity.

[0058] In some preferred embodiments, a specific example is given below. Suppose a mobile storage device has data in its storage chip that has become corrupted for some reason, and this data is marked as having the highest processing priority. When the system attempts to decode this data, decoding fails. At this point, the device's built-in power management unit immediately assesses the device's instantaneous power supply capability. If it detects that the battery power is low or the system load is too high, causing the instantaneous power supply capability to fall below a preset threshold (e.g., below the minimum voltage required to support high-strength ECC decoding), the system immediately suspends the current data error correction processing and puts the device into a low-power mode, such as turning off the screen backlight or reducing the CPU frequency. During the suspension, the power management unit continuously monitors the power status. Once the instantaneous power supply capability recovers above the preset threshold (e.g., the user plugs in a charger or the system load decreases), the data error correction processing restarts. After restarting, the system first attempts to decode the data using an encoding method that corrects multiple bit errors. If the error fails again, the system will enter the second stage of phased error correction, attempting to read the data by adjusting read parameters (e.g., fine-tuning the read voltage). However, a short interval (e.g., 100 milliseconds) will be set between each attempt to allow the power supply a brief recovery time. Simultaneously, the system will record the total latency from decoding failure to successful error correction and will send a warning message to the operating system if the latency exceeds a certain threshold, alerting the user to potential power or storage health issues.

[0059] In some embodiments of this application, when the device's instantaneous power supply capacity is lower than a preset threshold, data error correction processing is paused, and low-power operation is performed during the pause. However, in practical applications, if the data block whose error correction is paused contains data segments with high timeliness requirements, such as real-time control commands, critical sensor data, or system status information, simply pausing all error correction processing may result in these time-sensitive data segments not being processed in a timely manner, thereby affecting the system's real-time performance, response speed, or data consistency. If the above problems are not addressed, the system may not be able to effectively guarantee the continuity of critical services and the reliability of data when power is limited. To address this, this application further proposes a method for special processing of time-sensitive data segments when data error correction processing is paused, to ensure the availability and integrity of critical data, and to maintain a certain level of system responsiveness even when the instantaneous power supply capacity is insufficient.

[0060] In response, this application further proposes the following steps for pausing data error correction processing when the instantaneous power supply capacity is lower than a preset threshold: Obtain the pause indication information for the data error correction process; Identify whether there are time-sensitive data segments in the data blocks that have been suspended from error correction; When the time-sensitive data segment exists, obtain the correct version of the time-sensitive data segment; When the correct version of the time-sensitive data segment cannot be obtained, an integrity check is performed on the time-sensitive data segment. Based on the integrity check results, the time-sensitive data segments are processed; Send instruction information.

[0061] Specifically, obtaining the pause indication information for the data error correction process means that when the system assesses that the instantaneous power supply capacity is lower than a preset threshold, it will generate and receive a signal or status flag that clearly indicates that the current data error correction process has entered a paused state. This indication information can be issued by the power management unit, the main controller, or a dedicated error correction module.

[0062] The identification of time-sensitive data segments within data blocks whose error correction has been paused can be understood as the system scanning the content of a data block or querying its metadata when error correction is paused to determine if it contains data pre-marked as time-sensitive. Time-sensitive data segments typically refer to data that needs to be processed or responded to within a specific time window, such as task scheduling information in a real-time operating system, critical sensor readings, or control commands that need to be executed immediately. The identification process can be accomplished by examining the header information of the data block, the associated metadata tags, or its storage location.

[0063] In practical applications, when the time-sensitive data segment exists, the correct version of the time-sensitive data segment is obtained. This can be achieved, for example, by obtaining a latest and correct copy of the data segment from a redundant area of ​​the storage chip, a backup memory, or by communicating with an external controller. The aim is to restore or confirm the accuracy of critical data as much as possible without performing full error correction.

[0064] Furthermore, when the correct version of the time-sensitive data segment cannot be obtained, an integrity check is performed on the time-sensitive data segment. Specifically, this refers to performing a fast, low-power verification on the data segment, such as calculating a checksum, performing a cyclic redundancy check, or a simple parity check. The purpose is to at least determine the degree of data corruption or its usability when complete data repair is not possible, thus avoiding system failure caused by using erroneous data.

[0065] Therefore, processing the time-sensitive data segments based on the integrity check results can be understood as taking different countermeasures based on the output of the integrity check. For example, if the check results indicate that the data is complete and usable, the system can continue to use the data; if the data has minor errors but is still acceptable, it can be marked and limited use can be allowed; if the data is severely corrupted and unusable, it can be marked as invalid, and the upper-layer application can be notified to take alternative measures or rollback operations.

[0066] Finally, sending instruction information means notifying relevant system modules, applications, or logging systems of the processing results mentioned above, such as the availability status of time-sensitive data segments, whether the correct version has been obtained, integrity check results, or processing measures taken. The purpose is to enable the system to adjust its behavior based on the latest status and to provide a basis for subsequent fault diagnosis or recovery.

[0067] This application's solution addresses the potential delays or loss of critical data processing in basic solutions by prioritizing the identification and processing of time-sensitive data segments instead of simply halting all operations when data correction is paused due to insufficient instantaneous power supply. Through this technical solution, the application effectively avoids the problem of time-sensitive data segments being unable to be processed in a timely manner when data correction processing is paused due to a power supply instantaneous capacity falling below a preset threshold. This solution significantly improves the system's data reliability and real-time response capabilities in power-constrained environments through intelligent identification, prioritizing the acquisition of the correct version, or performing integrity checks. Compared to the basic solution that merely suspends all error correction processing, the additional technical features of this application ensure that critical time-sensitive data is properly processed even in low-power operation modes, thereby maintaining the system's core functions and business continuity, reducing the risk of data loss or system crashes due to power fluctuations, and greatly enhancing the robustness of the memory chip data error correction method.

[0068] In some preferred embodiments, a specific example is given below. Suppose that in an in-vehicle infotainment system, the memory chip stores navigation map data, user preference settings, and real-time traffic information. The real-time traffic information is marked as a time-sensitive data segment because it needs to be updated promptly to provide accurate navigation guidance. When the vehicle starts or during certain high-load operations, the power supply may temporarily decrease, causing the system to suspend routine error correction processing of all data in the memory chip.

[0069] At this point, the system receives a pause instruction for data error correction processing. Subsequently, the system identifies the data block whose error correction was paused and discovers that it contains a time-sensitive segment of real-time traffic information. The system first attempts to retrieve the latest correct version of this real-time traffic information from the vehicle communication module or a reserved backup area. If successful, the system directly updates the data segment in the storage chip to ensure the navigation system uses the latest traffic conditions.

[0070] However, if the system cannot obtain the correct version of real-time traffic information due to unstable network connectivity or corrupted backup data, it will immediately perform an integrity check on the data segment, such as by calculating its CRC checksum. If the integrity check indicates that the data is complete, the system will allow the navigation system to continue using the data, even if it is not the latest version, and may display a "Traffic information may not be up-to-date" message on the user interface. If the integrity check finds that the data is corrupted, the system will mark the data segment as invalid and may instruct the navigation system to temporarily disable the real-time traffic function or use a default, non-real-time traffic model to avoid providing incorrect information. Finally, the system will send an instruction to the onboard control unit, informing it of the processing result and current status of the real-time traffic information, so that the control unit can adjust the navigation strategy or issue a warning to the driver as needed. In this way, even if power constraints cause error correction to pause, the onboard system can prioritize the availability and reliability of critical real-time traffic information.

[0071] In some embodiments of this application, when the instantaneous power supply capability of the device is lower than a preset threshold, the data error correction process is suspended, and low-power operation is performed during the suspension period. However, in its implementation, if the instantaneous power supply capability remains low, simply suspending the error correction process may cause the suspended data blocks to remain in an unrepaired state for a long time, thereby increasing the risk of data error accumulation, and may even lead to permanent data damage or loss. This risk is unacceptable, especially for high-priority data.

[0072] To address this, this application further proposes an optimization scheme for more refined management of the paused data error correction processing when the instantaneous power supply capacity is consistently below a preset threshold, in order to balance the requirements of power consumption limitations and data integrity assurance. The aforementioned pause of data error correction processing when the instantaneous power supply capacity is below the preset threshold includes: Obtain indication information that the instantaneous power supply capability is continuously lower than a preset threshold; In response to the indicated information, the microcontroller is periodically woken up; Upon wake-up, assess the current power supply's instantaneous power delivery capability; When the instantaneous power supply capability of the power supply is still lower than the preset threshold, a minimum strength error correction attempt is performed on the first processing priority data block that has been suspended. Record the error correction pause duration of the first processing priority data block; When the error correction pause duration exceeds the preset maximum allowable pause duration, a high-intensity error correction attempt is forcibly executed. Send an emergency alert.

[0073] Specifically, acquiring the indication information that the instantaneous power supply capability is continuously lower than a preset threshold means that the system continuously monitors the power supply status. When it detects that the instantaneous power supply capability is lower than the preset threshold for a period of time or at multiple consecutive sampling points, it generates and acquires the corresponding indication information. This indication information can be issued by the power management unit or a dedicated monitoring circuit, and its purpose is to identify and confirm that the system is in a state of continuous low power consumption or insufficient power supply. Responding to the indication information, periodically waking up the microcontroller means that when the system receives the indication information that the instantaneous power supply capability is continuously lower than the preset threshold, the microcontroller (e.g., the main control chip or a dedicated power management controller) is periodically woken up from a low-power sleep state. The frequency of this periodic wake-up can be configured according to the system's data integrity requirements and power budget, with the aim of allowing the system to perform necessary checks and processing on the current state while maintaining overall low-power operation. After waking up, evaluating the current instantaneous power supply capability means that the microcontroller immediately re-evaluates the current instantaneous power supply capability after each wake-up. This can be achieved by reading real-time voltage, current, or power data from the power management unit, with the aim of obtaining the latest power supply status in order to make subsequent processing decisions.

[0074] Specifically, when the instantaneous power supply capacity is still below the preset threshold, performing a minimum-strength error correction attempt on the suspended first-priority data blocks means that if the microcontroller assessment finds that the instantaneous power supply capacity is still insufficient to support complete data error correction processing, but to avoid potential risks caused by prolonged data inactivity, the system will selectively perform a low-power error correction attempt on those suspended first-priority data blocks. This minimum-strength error correction attempt may include, but is not limited to: performing only partial decoding steps, using a low-complexity error correction algorithm, or only verifying the key metadata of the data block. Its purpose is to maintain basic data integrity as much as possible and prevent error accumulation under limited power conditions. In practical applications, recording the error correction pause duration of the first-priority data blocks means that the system will continuously track and record the total duration since the pause of each suspended first-priority data block. This record can be stored in non-volatile memory, and its purpose is to provide a time basis for subsequent decisions to determine whether stronger measures are needed.

[0075] Furthermore, when the error correction pause duration exceeds the preset maximum allowable pause duration, a high-intensity error correction attempt is forcibly executed. This means that once the error correction pause duration of a first-priority data block exceeds the system's preset maximum allowable pause duration, the system will forcibly initiate a high-intensity error correction attempt, even if the instantaneous power supply capacity is still below a preset threshold. This high-intensity error correction attempt typically refers to a complete error correction process, including decoding using an encoding method capable of correcting multiple bit errors and performing multiple read attempts by adjusting read parameters when decoding fails. Its purpose is to prevent data from being permanently damaged or lost due to prolonged inactivity, ensuring the timely recovery of critical data. Simultaneously, sending an emergency alarm means that while forcibly executing the high-intensity error correction attempt, the system will send an emergency alarm message to external entities (e.g., the host system, user interface, or remote monitoring center). This alarm message indicates that the current data error correction processing of the memory chip faces serious challenges, requiring external intervention or attention. Its purpose is to promptly notify relevant parties so that further countermeasures can be taken to avoid potential system failures.

[0076] This application's solution effectively addresses the data integrity risks and processing delays caused by prolonged pauses in data error correction processing under power constraints in basic solutions by introducing a monitoring and response mechanism for persistently low instantaneous power supply capabilities. Through this technical solution, the application significantly improves the data reliability and system robustness of memory chips under conditions of persistently insufficient instantaneous power supply. Specifically, periodically waking up the microcontroller and assessing the instantaneous power supply capability allows the system to continuously monitor environmental changes in low-power mode, avoiding the risks associated with blind pauses. Performing minimum-intensity error correction attempts provides basic protection for paused data within a limited power budget, effectively reducing the risk of error accumulation. More importantly, by introducing the recording of error correction pause duration and the setting of the maximum allowable pause duration, this application achieves dynamic management of data error correction processing. This ensures that even under prolonged power constraints, high-priority data can receive mandatory high-intensity error correction when necessary, thereby maximizing data integrity and promptly notifying system administrators through an emergency alarm mechanism, preventing potential catastrophic data loss. This is significantly superior to solutions that only perform simple pauses.

[0077] In some preferred embodiments, a specific example is given below. Suppose a memory chip in an embedded system is performing data error correction processing. At this time, due to external load fluctuations or insufficient battery power, the system power supply's instantaneous power delivery capacity continuously falls below a preset threshold. According to the basic scheme, the data error correction processing will be paused, and the system will enter low-power operation. However, if this low-power state persists for an extended period, such as several hours, errors in the paused data blocks may further deteriorate.

[0078] The proposed solution is an optimization of this approach. When the system detects an indication that the instantaneous power supply capability is consistently below a preset threshold, the microcontroller in the system periodically wakes up from sleep mode, for example, every 10 minutes. After each wake-up, the microcontroller reassesses the current instantaneous power supply capability. If the instantaneous power supply capability is still below the preset threshold, the system selects to perform minimum-strength error correction attempts on the first-priority data blocks that have been paused. For example, the system may only perform CRC checks on the data blocks, or use a computationally less complex error correction code for partial decoding to check the basic integrity of the data with extremely low power consumption. Simultaneously, the system continuously records the error correction pause duration for each paused first-priority data block.

[0079] Assume the system's preset maximum allowable pause time is 2 hours. If the error correction pause time for a first-priority data block reaches 2 hours, the system will forcibly initiate a high-intensity error correction attempt even if the instantaneous power supply has not yet recovered. This means the system will temporarily increase power consumption, use an encoding method capable of correcting multiple bit errors to decode the data block, and attempt multiple reads by adjusting read parameters if decoding fails. While forcibly executing the high-intensity error correction attempt, the system will immediately send an emergency alarm message to the host system, such as via interrupt or network message notification, indicating that the data error correction processing of the memory chip has reached an emergency state and requires immediate attention. In this way, this application ensures that the integrity of high-priority data is promptly and strongly guaranteed even in harsh environments with prolonged power constraints, avoiding permanent data corruption that may result from long delays.

[0080] In some embodiments described above, when the pause duration of data error correction processing exceeds the preset maximum allowable pause duration, a high-intensity error correction attempt is forcibly executed. However, this forced high-intensity error correction attempt, especially when the instantaneous power supply capability may still be unstable or in a marginal state, may cause a sharp increase in the system's instantaneous power demand. If not effectively managed, this high-power operation may cause a further drop in power supply voltage, leading to system instability, error correction operation failure, and even potential damage to the memory chip, thereby affecting the reliability of data recovery.

[0081] In response, this application further proposes the aforementioned method of forcibly executing high-intensity error correction attempts when the error correction pause duration exceeds the preset maximum allowable pause duration, including: Obtain the voltage ripple amplitude information of the power supply; Based on the voltage ripple amplitude information, the execution timing of the high-intensity error correction attempt is adjusted so that high-power operation avoids the peak moment of power ripple. Activate the instantaneous energy buffer unit to provide additional instantaneous power supply during error correction operations; Monitor the instantaneous power supply capability; When a downward trend in power supply capacity is detected, reduce the intensity of error correction operations or suspend non-critical error correction subtasks.

[0082] Specifically, acquiring power supply voltage ripple amplitude information refers to the system using a built-in power management unit or a dedicated voltage sensor to detect voltage fluctuations in the power supply in real time or periodically, and extracting characteristic parameters such as peak-to-peak value and frequency of the ripple. This information is used to assess the stability of the current power supply. Adjusting the execution timing of high-intensity error correction attempts based on the voltage ripple amplitude information, so that high-power operations avoid peak power supply ripple times, can be understood as the system predicting the low and high peaks of the power supply voltage based on the acquired voltage ripple information, and intelligently scheduling operations requiring large amounts of instantaneous current in high-intensity error correction attempts to execute when the power supply voltage is relatively stable or at a trough, thereby avoiding further burdening the power supply during peak ripple times. For example, this can be achieved by delaying the startup time of certain computationally intensive or memory-access-intensive subtasks.

[0083] In practical applications, activating a transient energy buffer unit provides additional transient power during error correction operations. Specifically, this involves activating a pre-charged energy storage device such as a capacitor bank or supercapacitor before performing a high-intensity error correction attempt. This buffer unit can quickly release stored energy when the system requires additional transient power, supplementing the main power supply and ensuring a stable power supply for error correction operations. Furthermore, monitoring the transient power supply capability refers to the system continuously monitoring the voltage, current, or power of the power supply in real time throughout the high-intensity error correction attempt. This can be achieved through a monitoring module integrated into the power management chip or independent sensors to promptly detect any abnormal changes in power supply capability. When a decreasing trend in power supply capability is detected, the intensity of the error correction operation is reduced or non-critical error correction subtasks are paused. The aim is to avoid system crashes or data corruption by dynamically adjusting the error correction strategy in the early stages of insufficient power supply capability. For example, the complexity of the error correction algorithm can be temporarily reduced, the number of parallel processing tasks can be decreased, or auxiliary error correction subtasks with low real-time requirements but high power consumption, such as logging and status updates, can be paused.

[0084] This application's solution effectively addresses the potential power instability issues encountered during forced high-intensity error correction attempts by introducing power supply voltage ripple sensing and a transient energy buffering mechanism. Through this technical solution, the application significantly improves the success rate and system stability of forced high-intensity data error correction under conditions of insufficient or unstable instantaneous power supply. By intelligently avoiding power supply ripple peaks and utilizing a transient energy buffer unit to provide supplementary power, the impact of high-power operation on the power supply is effectively mitigated. Simultaneously, the mechanism for dynamically adjusting error correction intensity or pausing non-critical tasks enables the system to respond promptly when power conditions deteriorate, avoiding error correction failures or system crashes due to insufficient power. This ensures reliable data recovery under extreme conditions and improves the overall reliability and data integrity of the memory chip.

[0085] In some preferred embodiments, a specific example is given below. Assume a storage controller, when performing a high-intensity error correction attempt, first obtains the voltage ripple amplitude information of the current power supply and detects periodic voltage fluctuations. Based on this information, the controller schedules the most power-consuming decoding and reconstruction stages of the high-intensity error correction algorithm to be executed at the rising edge after a voltage trough or at a relatively stable moment, avoiding the peak of the voltage ripple. Simultaneously, before initiating the high-intensity error correction attempt, the controller activates a supercapacitor integrated on the motherboard as a transient energy buffer unit, ensuring that even if the main power supply experiences a brief voltage drop during the error correction process, the supercapacitor can immediately discharge to provide the necessary transient current. During the error correction operation, the power monitoring module continuously tracks the transient power supply capacity of the core voltage rail. Once the voltage drop rate is detected to exceed a preset threshold, the system immediately reduces the parallelism of the error correction algorithm, for example, from processing four data blocks simultaneously to two, and suspends the non-critical subtask of writing the error correction results to the log until the power supply capacity returns to stability. In this way, even under less than ideal power conditions, high-intensity error correction attempts can be completed in a controlled and efficient manner, maximizing the success rate of data recovery.

[0086] In some embodiments described above, this application proposes a scheme to suspend data error correction processing when the instantaneous power supply capacity falls below a preset threshold, thereby saving power consumption and protecting system stability. However, in practical applications, simply suspending data error correction processing may not be sufficient for all situations. For example, during the suspension period, the system may receive external emergency commands or critical events, which may be highly time-sensitive and require immediate response. If the system merely remains suspended, it may lead to delays in responding to these critical events, or even miss the optimal processing opportunity, thereby causing more serious system problems or data loss.

[0087] In this regard, this application further proposes that, when the instantaneous power supply capacity is lower than a preset threshold, the data error correction process should be suspended, including: Obtain the pause instruction information for data error correction processing; Monitor the triggering of external emergency commands or critical events; When an external emergency command or critical event is detected, assess the response priority of the external emergency command or critical event; Based on response priority, the pause strategy for data error correction processing is dynamically adjusted, including: When the response priority indicates that an immediate response is required, the instantaneous energy buffer unit is activated, and the response operation for the emergency command or critical event is performed with limited power consumption. When the response priority indicator allows for a delayed response, the data error correction process remains paused, and the delay information for emergency instructions or critical events is recorded. During emergency command or critical event response operations, continuously monitor the instantaneous power supply capacity; When a decreasing trend in the instantaneous power supply capacity is detected, the intensity of emergency command or critical event response operations will be further reduced.

[0088] Specifically, the pause indication information for data error correction processing refers to a signal issued internally or externally by the system, indicating that the current data error correction process has entered a paused state due to insufficient instantaneous power supply. This indication information can be a flag bit in a status register, an interrupt signal, or a message notification, used to indicate the current status of error correction processing to other modules in the system.

[0089] Monitoring the triggering of external emergency commands or critical events refers to the system continuously listening for specific signals or events from external interfaces (such as communication ports or sensor inputs) or internal modules (such as watchdog timers or system health monitoring units). These commands or events typically have high priority, such as system reset requests, critical data write requests, security alarms, or user-mandated operations, and their triggering may be achieved through mechanisms such as interrupts, polling, or event queues.

[0090] Prioritizing responses to external emergency commands or critical events involves ranking monitored emergency commands or critical events according to predefined priority rules or strategies. For example, a system reset command might be assigned the highest priority, while some non-critical log recording requests might be assigned a lower priority. This assessment can be based on command type, source, scope of impact, or a predefined configuration table to ensure the system can distinguish the urgency of different events.

[0091] The dynamic adjustment of the pause strategy for data error correction processing is to flexibly change the current pause behavior of data error correction processing based on the assessed response priority.

[0092] When a response priority indicator requires an immediate response, it signifies an extremely high level of urgency, and power restoration cannot be delayed. In this case, the system activates a transient energy buffer unit, such as a supercapacitor or backup battery, to provide additional instantaneous power for a short period. Simultaneously, emergency commands or critical event responses are executed with limited power consumption—that is, minimizing power consumption while meeting functional requirements to avoid excessive stress on the main power supply. This can be achieved by reducing clock frequency, minimizing parallel operations, or activating only essential functional modules.

[0093] When the response priority indicator allows for a delayed response, it means that although the event is important, its timeliness requirement is not high, and it can wait for the power supply to be restored momentarily. In this case, the system will maintain the paused state of data error correction processing and record the delay information of emergency commands or critical events so that they can be processed or relevant modules can be notified after power is restored, avoiding unnecessary power consumption.

[0094] Continuously monitoring the instantaneous power supply capability during emergency command or critical event response operations is to ensure that the system remains vigilant about the power status during emergency response.

[0095] When a downward trend in the instantaneous power supply capacity is detected, the intensity of emergency command or critical event response operations will be further reduced. This means that if it is found that even if the instantaneous energy buffer unit is activated, the power supply capacity is still insufficient or shows signs of deterioration, the system will take further measures, such as reducing the processing frequency, reducing parallel operations, and shutting down non-core functions, to ensure that the most critical response operations can be completed while avoiding system crashes.

[0096] This application's solution effectively addresses the problem of the system's inability to respond promptly to high-priority events when data error correction processing is paused due to insufficient instantaneous power supply. By introducing a monitoring and response priority evaluation mechanism for external emergency commands or critical events, it effectively improves the system's robustness and responsiveness in scenarios where data error correction is paused due to insufficient instantaneous power supply. This solution avoids delays or failures in responding to critical events that may result from simple pauses, thus effectively preventing potential system failures or data loss. By intelligently evaluating the priority of emergency events and dynamically adjusting the pause strategy, the system can maintain low-power operation to the maximum extent while ensuring the response of core functions, achieving an optimized balance between power management and system response efficiency. Especially in environments with frequent power fluctuations or drastic system load changes, this application's solution ensures the reliability of the memory chip's data error correction process and improves the overall system availability and security.

[0097] In some preferred embodiments, suppose a memory chip in an embedded system is performing data error correction processing, but due to a sudden increase in system load, the instantaneous power supply capacity drops below a preset threshold. The system then suspends the data error correction processing and enters a low-power operating state. At this time, the system detects an "emergency data erase" command triggered by an external security module, which is assessed as the highest priority event requiring immediate response.

[0098] According to the scheme of this application, the system will not simply ignore the instruction, but will immediately activate its internal instantaneous energy buffer unit (e.g., a small supercapacitor bank). This buffer unit releases the stored energy in a very short time, providing additional instantaneous power to the system. Simultaneously, the system performs an "emergency data erase" operation with limited power consumption; for example, it only activates the necessary storage controller and erase logic, and operates at a lower clock frequency to avoid unnecessary power consumption. During the erase operation, the system continuously monitors the instantaneous power supply capability. If it detects that the power supply capability is still declining even with the buffer unit providing power, the system will further reduce the intensity of the erase operation, such as erasing data blocks in batches, or temporarily suspending the erasure of non-critical areas, prioritizing the erasure of the most sensitive data to ensure that critical safety instructions can be completed even under the worst power conditions.

[0099] On the other hand, if the system detects a "non-critical log upload" command during the pause, this command is assessed as allowing for a delayed response. In this case, the system will maintain the paused state of data error correction processing, mark the log upload command as pending, and record its delay information. Once the instantaneous power supply capacity recovers to above the preset threshold and data error correction processing restarts, the system will process the log upload task at an opportune time.

[0100] Through this dynamic adjustment strategy, the system can effectively manage power consumption when power is limited, while ensuring timely response to critical emergencies, thereby improving the overall reliability and security of the system.

[0101] In some of the embodiments described above in this application, a scheme is proposed to respond to emergency commands or critical events by activating an instantaneous energy buffer unit when the instantaneous power supply capacity is insufficient. However, in practical applications, the health status and energy release efficiency of the instantaneous energy buffer unit may decline due to long-term use or environmental factors. If a buffer unit in poor condition is activated directly, it may not be able to effectively provide the required instantaneous power supply capacity, thereby affecting the timeliness and reliability of the emergency response.

[0102] In this regard, this application further proposes to perform a health status assessment of the aforementioned instantaneous energy buffer unit before activating it, the health status assessment including: A preset test discharge pulse is applied to the instantaneous energy buffer unit; Monitor the rate of voltage drop of the instantaneous energy buffer unit under the action of the test discharge pulse; The instantaneous energy release efficiency of the instantaneous energy buffer unit is determined based on the voltage drop rate. When the instantaneous energy release efficiency is lower than a preset standard, the instantaneous energy buffer unit undergoes a pre-charge activation process, which includes: The instantaneous energy buffer unit is subjected to multiple charge-discharge cycles with a controlled current; After the pre-charge activation process is completed, the instantaneous energy release efficiency of the instantaneous energy buffer unit is evaluated again. When the instantaneous energy release efficiency is still lower than the preset standard, a buffer unit fault alarm is sent. Once the instantaneous energy release efficiency meets the preset standard, the instantaneous energy buffer unit is activated, and the emergency command or critical event response operation is executed with limited power consumption.

[0103] Specifically, before activating the instantaneous energy buffer unit, a health status assessment is first performed. This assessment simulates actual operating discharge conditions by applying a preset test discharge pulse to the instantaneous energy buffer unit. Under the test discharge pulse, the voltage drop rate of the instantaneous energy buffer unit is monitored. The voltage drop rate is a key indicator of the buffer unit's instantaneous energy release capability; a faster voltage drop rate usually indicates lower instantaneous energy release efficiency. Based on the monitored voltage drop rate, the current instantaneous energy release efficiency of the instantaneous energy buffer unit can be determined. The instantaneous energy buffer unit can be understood as a device capable of rapidly releasing stored energy, such as a supercapacitor or high-power-density battery pack, designed to provide short-term high-current support when the main power supply is insufficient. The preset test discharge pulse refers to parameters such as discharge current and discharge duration pre-set according to the buffer unit's specifications and application scenario, designed to simulate instantaneous load demands under actual emergency conditions. The voltage drop rate refers to how quickly the voltage across the buffer unit changes over time under the test discharge pulse, directly reflecting the buffer unit's internal resistance and energy output capability. Instantaneous energy release efficiency refers to the ability of a buffer unit to provide high power output in a short period of time, and its purpose is to evaluate its effectiveness in emergency situations.

[0104] When the evaluation results show that the instantaneous energy release efficiency is lower than the preset standard, it indicates that the buffer unit may be in a suboptimal state, and a pre-charge activation treatment will be performed. The pre-charge activation treatment involves multiple charge-discharge cycles of the instantaneous energy buffer unit with a controlled current. This cyclic charge-discharge helps activate the electrochemical characteristics of the buffer unit, restoring its capacity and instantaneous discharge capability, for example, by eliminating the passivation layer, homogenizing the electrolyte distribution, or activating the electrode material. Controlled current refers to the precise control of the current magnitude during the charge-discharge cycle to avoid overcharging and over-discharging damage to the buffer unit and to optimize the activation effect. Multiple charge-discharge cycles refer to repeatedly performing the charging and discharging process, the purpose of which is to improve the performance of the buffer unit through a dynamic process. After the pre-charge activation treatment is completed, the instantaneous energy release efficiency of the instantaneous energy buffer unit will be evaluated again to confirm whether its performance has recovered to above the preset standard. If the efficiency is still lower than the preset standard after activation treatment, a buffer unit fault alarm will be sent, indicating to the system that the buffer unit may have a hardware fault and cannot be used reliably. The instantaneous energy buffer unit will only be activated when the instantaneous energy release efficiency meets the preset standard, and will execute emergency commands or critical event response operations with limited power consumption to ensure that a stable and reliable instantaneous power supply can be provided at critical moments.

[0105] This application's solution effectively addresses the problem that the instantaneous energy buffer unit may fail to reliably provide instantaneous power when the power supply's instantaneous power capability is insufficient. By conducting a health status assessment and necessary pre-charge activation treatment before activating the instantaneous energy buffer unit, it addresses this issue. Through this technical solution, the system's emergency response reliability under limited instantaneous power supply conditions is significantly improved. By proactively evaluating and optimizing the performance of the instantaneous energy buffer unit, this solution effectively avoids potential system failures caused by the buffer unit's poor condition, thereby ensuring the smooth execution of critical operations. Furthermore, the introduction of a fault alarm mechanism enables the system to promptly detect and address hardware problems with the buffer unit, further enhancing the system's robustness and maintainability.

[0106] In some preferred embodiments, assuming that the system detects that the instantaneous power supply capacity is lower than a preset threshold while performing data error correction processing, and at this time receives an emergency command requiring immediate response, such as a critical data write request, the system first performs a health status assessment on the instantaneous energy buffer unit before activating it to provide additional power.

[0107] Specifically, the system applies a 100-microsecond test discharge pulse with a current of 5 amps to the buffer unit. During this period, the system monitors the voltage drop across the buffer unit. If the voltage drop rate exceeds 0.5 volts per microsecond, it indicates that its instantaneous energy release efficiency is lower than a preset standard. At this point, the system initiates a pre-charge activation process, performing 5 charge-discharge cycles on the buffer unit with a controlled current (e.g., charging at 1 amp for 1 second, then discharging at 2 amps for 0.5 seconds). After the activation process is complete, the system repeats the same test discharge pulse and voltage drop rate monitoring. If the voltage drop rate has now dropped below 0.3 volts per microsecond, meeting the preset standard, the system confirms that the buffer unit has recovered and immediately starts the buffer unit to perform critical data write operations with limited power consumption. Conversely, if the voltage drop rate is still higher than 0.5 volts per microsecond after reassessment, the system sends a buffer unit fault alarm and may switch to backup power or take other emergency measures to avoid data write failure due to buffer unit failure.

[0108] In some embodiments of this application described above, after the pre-charge activation process of the instantaneous energy buffer unit is completed, the instantaneous energy release efficiency of the instantaneous energy buffer unit needs to be evaluated again to ensure that its performance meets the preset standard. However, during this evaluation process, the system may receive an emergency command. If the system strictly waits for the evaluation to be completed before responding to the emergency command, it may cause delays in critical operations, thereby affecting the real-time performance and reliability of the system.

[0109] In response, this application further proposes a method for re-evaluating the instantaneous energy release efficiency of the instantaneous energy buffer unit after the pre-charge activation treatment is completed, which includes: Retrieve emergency instructions received by the system; When the emergency command is received, the current evaluation process of the instantaneous energy release efficiency of the instantaneous energy buffer unit is interrupted; The instantaneous energy buffer unit is activated according to the preset emergency response strategy; Record the current evaluation status of the buffer unit and the response time of the emergency command; After the emergency command response is completed, the evaluation of the instantaneous energy release efficiency of the instantaneous energy buffer unit continues in low power mode.

[0110] Specifically, receiving emergency instructions refers to the system's ability to monitor and identify high-priority operation requests or event notifications from external or internal sources in real time. These emergency instructions may include, but are not limited to, requests to write critical data, emergency system shutdown instructions, and power failure alarms, requiring the system to take immediate action to avoid potential risks or losses.

[0111] When the system receives the emergency command, the ongoing evaluation process of the instantaneous energy release efficiency of the instantaneous energy buffer unit will be immediately interrupted. This means that the evaluation task will be suspended or terminated to free up system resources and ensure that the emergency command can be processed with the highest priority.

[0112] The activation of the instantaneous energy buffer unit according to the preset emergency response strategy refers to the system having a predefined set of rules and procedures for handling emergencies. When an emergency command is triggered, the system will quickly and effectively activate the instantaneous energy buffer unit according to these strategies to provide the necessary instantaneous power supply. These strategies may include skipping certain non-critical self-test steps or activating the buffer unit with maximum efficiency rather than optimal efficiency to ensure the fastest possible response speed.

[0113] Simultaneously, the system records the current evaluation status of the buffer unit and the response time of the emergency command. The current evaluation status records the specific progress and parameters when the evaluation process was interrupted, so that the evaluation can be accurately resumed later. The response time of the emergency command records the time interval between receiving the emergency command and starting to execute the response operation, which is crucial for evaluating the real-time response performance of the system. After the response operation of the emergency command is completed, the system continues to evaluate the instantaneous energy release efficiency of the instantaneous energy buffer unit in a low-power mode. This means that after the emergency is resolved, the system will continue to execute the previously interrupted evaluation task in a low-resource-consumption manner, ensuring that the health status of the buffer unit is fully verified, while avoiding additional power consumption burden on the system.

[0114] This application's solution implements dynamic priority management of system tasks by introducing an emergency command interrupt mechanism. When the system receives an emergency command, it can immediately interrupt the ongoing evaluation process of the instantaneous energy buffer unit, thereby ensuring that critical tasks can be responded to in a timely manner. This mechanism avoids emergency response delays caused by waiting for non-urgent tasks to complete, effectively improving the system's real-time performance and reliability. By recording the evaluation status and response time, the system can track the state before and after the interruption, and resume the evaluation in a low-power mode after the emergency operation is completed, ensuring the integrity of the evaluation while optimizing resource utilization.

[0115] Through the above technical solution, this application can significantly improve the response speed and flexibility of the memory chip data error correction system in the face of emergencies. It ensures that the instantaneous energy buffer unit can be quickly activated when most needed, providing stable instantaneous power for critical operations, thereby effectively avoiding the risk of system performance degradation or data loss due to evaluation task blocking. Furthermore, after the emergency has passed, the system can still complete the health assessment of the buffer unit in an efficient and low-power manner, ensuring the long-term stability and reliability of the system.

[0116] refer to Figure 3 , Figure 3 This is a schematic diagram of a memory chip data error correction system provided in an embodiment of the present invention, comprising: The input terminal is used to obtain data processing priority information associated with the data in the memory chip. The processing unit is configured to perform differentiated correction processing on data errors in the memory chip according to the data processing priority information. The differentiated correction processing includes: When the data processing priority information indicates that the data has the first processing priority, the first correction process is performed. The first correction process is to decode the data using an encoding method that corrects multiple bit errors. When the decoding fails, the data is read multiple times by adjusting the reading parameters. When the data processing priority information indicates that the data has a second processing priority, a second correction process is performed. The second correction process is to perform an integrity check on the data. If the integrity check finds an error, the repair of the data is abandoned.

[0117] To address this issue, this application proposes a data error correction system for memory chips, designed to handle complex data errors generated by memory chips during long-term operation and under unstable power supply environments. The system acquires data processing priority information associated with the data in the memory chip through its input terminal, and the processing terminal performs differentiated correction processing on data errors of different importance based on this priority information. Thus, this system can optimize system resource consumption while ensuring the reliability of critical data, effectively solving the problem of insufficient capability of traditional error correction codes when facing complex multi-bit errors, and also meeting the requirements of low power consumption and long-lifespan operation.

[0118] The specific meanings and implementation details of data processing priority information, first processing priority, second processing priority, encoding method for correcting multiple bit errors, adjustment of reading parameters, and integrity checks have been described in the above embodiments and will not be repeated here. It should be emphasized that the system proposed in this application implements the above method through its specific structural components.

[0119] Specifically, the memory chip data error correction system of this application includes an input terminal and a processing terminal.

[0120] The input terminal is configured to acquire data processing priority information associated with data in the memory chip. This input terminal can be a dedicated hardware interface, such as communicating with the memory controller or main processor via a bus interface, to receive priority identifiers pre-stored in the metadata area. In a preferred embodiment, the input terminal can also be a software module that acquires priority information by reading specific registers or memory-mapped areas of the memory chip. In some embodiments, the input terminal can also dynamically infer data processing priority information by monitoring data access requests on the system bus and combining this with preset rules (e.g., based on data address ranges or data types).

[0121] Furthermore, the processing unit is configured to perform differentiated error correction processing on the data in the memory chip based on the data processing priority information. This processing unit can be a dedicated hardware logic unit integrated into the memory controller, such as a programmable gate array (FPGA) or application-specific integrated circuit (ASIC), containing modules for decoding multi-bit error correction codes, adjusting read parameters, and performing integrity checks. Alternatively, the processing unit can be implemented by a microcontroller or main processor executing specific firmware or software programs that call corresponding error correction subroutines based on the priority information. For example, when the data processing priority information indicates that the data has a first processing priority, the processing unit will activate its internal multi-bit error correction decoding module for decoding. If decoding fails, the processing unit will further control the memory chip's read circuitry, adjusting the read voltage or timing parameters and performing multiple read attempts. When the data processing priority information indicates that the data has a second processing priority, the processing unit will call its internal integrity check module, such as a cyclic redundancy checker (CRC), to quickly check the data and directly abandon repairs upon detecting errors to save resources.

[0122] The memory chip data error correction system of this application effectively solves the problem of insufficient capability of traditional error correction codes when facing complex multi-bit errors by introducing data processing priority information and performing differentiated correction processing on the processing end accordingly, while optimizing system resource consumption.

[0123] Specifically, the system of this application achieves refined management of data of varying importance through the collaborative work of its input and processing ends. Compared to existing systems that employ a uniform error correction strategy for all data, the system of this application can provide higher-level multi-bit error correction and read parameter adjustment attempts for critical data (first processing priority), significantly improving the recovery capability and reliability of critical data. For non-critical data (second processing priority), the system employs lightweight integrity checks and promptly abandons repairs, avoiding wasting computational resources and time on unnecessary data repairs, thereby effectively reducing the overall system's power consumption and latency. This differentiated processing mechanism enables the system to better adapt to the requirements of low power consumption and long-lifespan operation while ensuring the integrity of core functional data, demonstrating significant technological progress and innovation.

[0124] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for correcting data errors in a memory chip, characterized in that, include: Obtain data processing priority information associated with data in the memory chip; Based on the data processing priority information, differentiated correction processing is performed on the data errors in the memory chip. This differentiated correction processing includes: When the data processing priority information indicates that the data has the first processing priority, the first correction process is performed. The first correction process is to decode the data using an encoding method that corrects multiple bit errors. When the decoding fails, the data is read multiple times by adjusting the reading parameters. When the data processing priority information indicates that the data has a second processing priority, a second correction process is performed. The second correction process is to perform an integrity check on the data. If the integrity check finds an error, the repair of the data is abandoned.

2. The data error correction method for a memory chip according to claim 1, characterized in that, When decoding fails, the data is read multiple times by adjusting the reading parameters, including: Obtain the indication information for data decoding failure; In response to the indication information of data decoding failure, a dual-threshold alternating read sequence is initiated, the dual-threshold alternating read sequence comprising: Within a preset time window, the voltage is read at a level lower than the preset standard and at a level higher than the preset standard. By comparing the differences at the same bit position in the two data reads, bit difference information is obtained; Based on the bit difference information, determine whether the data error is a transient logic jitter mode; If so, then stop reading and adjusting the parameters; Obtain the correct version of the data from the backup area; Write the correct version of the data into the healthy area of ​​the storage chip.

3. The data error correction method for a memory chip according to claim 1, characterized in that, When the data processing priority information indicates that the data has a first processing priority, the first correction process is performed, including: Obtain the indication information for data decoding failure; Assess the instantaneous power supply capability of the current device; When the instantaneous power supply capacity of the power source is lower than a preset threshold, the data error correction process is suspended. During the pause, low-power operation is performed; When the instantaneous power supply capability of the power supply recovers to above the preset threshold, the data error correction process is restarted. A phased error correction strategy is employed to perform error correction processing on the data. The phased error correction strategy includes: The data is decoded using an encoding method capable of correcting multiple bit errors; If the decoding fails, the data is read multiple times by adjusting the reading parameters, and an interval is set between the reading attempts. Record the delay in the data error correction process; Send a warning message.

4. The data error correction method for a memory chip according to claim 3, characterized in that, The step of pausing data error correction processing when the instantaneous power supply capacity of the power source is lower than a preset threshold includes: Obtain the pause indication information for the data error correction process; Identify whether there are time-sensitive data segments in the data blocks that have been suspended from error correction; When the time-sensitive data segment exists, obtain the correct version of the time-sensitive data segment; When the correct version of the time-sensitive data segment cannot be obtained, an integrity check is performed on the time-sensitive data segment. Based on the integrity check results, the time-sensitive data segments are processed; Send instruction information.

5. A method for correcting data errors in a memory chip according to claim 3, characterized in that, The step of pausing data error correction processing when the instantaneous power supply capacity of the power source is lower than a preset threshold includes: Obtain indication information that the instantaneous power supply capability of the power source is continuously lower than the preset threshold; In response to the indicated information, the microcontroller is periodically woken up; Upon wake-up, assess the current power supply's instantaneous power delivery capability; When the instantaneous power supply capability of the power supply is still lower than the preset threshold, a minimum strength error correction attempt is performed on the first processing priority data block that has been suspended. Record the error correction pause duration of the first processing priority data block; When the error correction pause duration exceeds the preset maximum allowable pause duration, a high-intensity error correction attempt is forcibly executed. Send an emergency alert.

6. The data error correction method for a memory chip according to claim 5, characterized in that, When the error correction pause duration exceeds the preset maximum allowable pause duration, a high-intensity error correction attempt is forcibly executed, including: Obtain the voltage ripple amplitude information of the power supply; Based on the voltage ripple amplitude information, the execution timing of the high-intensity error correction attempt is adjusted so that high-power operation avoids the peak moment of power ripple. Activate the instantaneous energy buffer unit to provide additional instantaneous power supply during error correction operations; Monitor the instantaneous power supply capability; When a downward trend in power supply capacity is detected, reduce the intensity of error correction operations or suspend non-critical error correction subtasks.

7. The data error correction method for a memory chip according to claim 3, characterized in that, The step of pausing data error correction processing when the instantaneous power supply capacity of the power source is lower than a preset threshold includes: Obtain the pause indication information for the data error correction process; Monitor the triggering of external emergency commands or critical events; When the external emergency command or critical event is detected, the response priority of the external emergency command or critical event is assessed; Based on the response priority, the pause strategy for the data error correction process is dynamically adjusted, wherein the dynamic adjustment includes: When the response priority indication requires an immediate response, the instantaneous energy buffer unit is activated, and the response operation of the emergency command or critical event is performed with limited power consumption. When the response priority indication allows for a delayed response, the data error correction process remains paused, and the delay information of the emergency instruction or critical event is recorded. During the execution of the emergency instructions or response to the critical events, the instantaneous power supply capability is continuously monitored; When a decreasing trend in instantaneous power supply capacity is detected, the intensity of emergency command or critical event response operations will be further reduced.

8. A method for correcting data errors in a memory chip according to claim 7, characterized in that, When the response priority indication requires an immediate response, the instantaneous energy buffer unit is activated, and the response operation for the emergency command or critical event is performed with limited power consumption, including: Before activating the instantaneous energy buffer unit, a health status assessment of the instantaneous energy buffer unit is performed, including: A preset test discharge pulse is applied to the instantaneous energy buffer unit; Monitor the voltage drop rate of the instantaneous energy buffer unit under the action of the test discharge pulse; The instantaneous energy release efficiency of the instantaneous energy buffer unit is determined based on the voltage drop rate. When the instantaneous energy release efficiency is lower than a preset standard, the instantaneous energy buffer unit undergoes a pre-charge activation process, which includes: The instantaneous energy buffer unit is subjected to multiple charge-discharge cycles with a controlled current; After the pre-charge activation process is completed, the instantaneous energy release efficiency of the instantaneous energy buffer unit is evaluated again. When the instantaneous energy release efficiency is still lower than the preset standard, a buffer unit fault alarm is sent. Once the instantaneous energy release efficiency meets the preset standard, the instantaneous energy buffer unit is activated, and the emergency command or critical event response operation is executed with limited power consumption.

9. A method for correcting data errors in a memory chip according to claim 8, characterized in that, After the pre-charge activation process is completed, the instantaneous energy release efficiency of the instantaneous energy buffer unit is evaluated again, including: Retrieve emergency instructions received by the system; When the emergency command is received, the current evaluation process of the instantaneous energy release efficiency of the instantaneous energy buffer unit is interrupted. The instantaneous energy buffer unit is activated according to the preset emergency response strategy; Record the current evaluation status of the buffer unit and the response time of the emergency command; After the emergency command response operation is completed, the evaluation of the instantaneous energy release efficiency of the instantaneous energy buffer unit continues in low power mode.

10. A data error correction system for a memory chip, characterized in that, include: The input terminal is used to obtain data processing priority information associated with the data in the memory chip. The processing unit is configured to perform differentiated correction processing on data errors in the memory chip according to the data processing priority information. The differentiated correction processing includes: When the data processing priority information indicates that the data has the first processing priority, the first correction process is performed. The first correction process is to decode the data using an encoding method that corrects multiple bit errors. When the decoding fails, the data is read multiple times by adjusting the reading parameters. When the data processing priority information indicates that the data has a second processing priority, a second correction process is performed. The second correction process is to perform an integrity check on the data. If the integrity check finds an error, the repair of the data is abandoned.

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