49 results about "Sequential programming" patented technology

A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such that different pages of data are stored in different memory devices. A memory controller issues program commands for each memory device. As each memory device receives a program command, it either begins a programming operation or passes the command to the next memory device. Therefore, the memory devices in the Flash system sequentially program pages of data one after the other, thereby minimizing delay in programming each page of data into the Flash memory system. The memory controller can execute a wear leveling algorithm to maximize the endurance of each memory device, or to optimize programming performance and endurance for data of any size.

An apparatus and method for universal programming language conversion between two different sequential programming languages, e.g., sequential procedural and sequential object oriented programming languages. In particular, conversion is between a source program in a first programming language and a target program in a second programming language. Initially, the source program in the first programming language is parsed using a parsing interface specific to the first programming language. All syntax from the parsed source program is then stripped or removed. Classes in a framework are instantiated to capture semantics of the parsed source program independent of syntax and execution model of the sequential programming languages. The classes are C++ classes representing fundamental core constructs of all sequential programming languages. A semantic representation of the parsed source program without any syntax is produced. The semantic representation is received at a printer interface specific to the second programming language and syntax of the target program in the second programming language is added. This same process can be used for either high-level conversion or compilation depending on whether the target programming language is high level or low level, respectively.

A non-volatile memory device has multi-level cells (MLCs), which are programmed such that one page is written in the MLCs having previous states corresponding to at least one previous page. The non-volatile memory device includes a memory cell array, a row selection circuit and a page buffer block. The memory cell array includes the MLCs commonly coupled to a selected word line and respectively coupled to bitlines. The row selection circuit applies sequentially-decreasing read voltages to the selected wordline to read the previous states of the MLCs, and sequentially-decreasing verification voltages to the selected wordline to program states of the MLCs sequentially from a state having a highest threshold voltage to a state having a lowest threshold voltage. The page buffer block loads data corresponding to the one page, and controls a bitline voltage based on each previous state and each bit of the loaded data.

Embodiments are provided in which a method and an apparatus for sequentially programming electrical fuses are described. A fuse pointer is advanced to point to (i.e., select) the fuses sequentially. When the fuse pointer reaches (i.e., points to) a fuse that is not to be blown, the fuse pointer automatically and asynchronously (e.g. not synchronized to a programming clock signal) skips the fuse. On the other hand, when the fuse pointer reaches a fuse that is to be blown, the fuse pointer stops and the fuse is blown synchronously (e.g., in response to the programming clock signal). After the blow, the fuse pointer advances to the next fuse and the process described above repeats, until the last fuse is programmed. A fuse latch circuit associated with the blown fuse may be optionally reset prior to advancing the fuse pointer.

A test method and apparatus for a semiconductor memory device is characterized by the sequentially programmed use of two test different modes. A first test mode tests at least signal line integrity for the semiconductor memory device by testing a merged set of bits line. The second test mode further tests at least signal line integrity after first separating the merged bits lines. Logical combination of test data derived from the first and second test modes are used to generate error detection signals. At least one bit line associated with a parity bit is preferable merged and separated in the foregoing approach.

Methods and systems for modeling concurrent behavior in a sequential programming environment using sequential-execution languages to describe and model multiple different processes which are running simultaneously.

A flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed by downloading a bit stream, done tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit as part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that once data has arrived at its destination it is properly locked, not to be unintentionally overwritten.

In a method for sequentially programming an injection molding cycle of an injection molding machine comprising one or several injection molds, the injection molding cycle is started manually step by step. The parts of the injection molding machine and/or the parts of the injection mold(s) are manually displaced into the positions or states required for the injection molding cycle in the order required for the injection molding cycle. The movement sequence (the actions and the obtained states) of the machine parts and/or the mold parts is stored in a controller.

A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed by downloading a bit stream, done tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit as part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that once data has arrived at its destination it is properly locked, not to be unintentionally overwritten. The robust FLU is further equipped with cyclic redundancy check capabilities to provide indication of faulty column configuration.

A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit that is part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that loaded data is properly locked, to prevent overwrites. The robust FLU is further equipped with cyclic redundancy check capabilities to provide indication of faulty column configuration. The invention also provides for splitting the single FLU into multiple independent reconfigurable FLU sections, with independent user clock and reset, for implementing a plurality of independent functions or for establishing redundancy for critical functions.

A method of operating a phase change random access memory (PRAM) device comprises performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.

A one time programmable (OTP) memory includes an OTP cell array including a plurality of OTP cells provided at locations where a plurality of word lines and a plurality of bit lines cross each other, and a write circuit configured to sequentially program the OTP cells by selecting the bit lines one at a time and program a selected OTP cell connected to the selected bit line, wherein the write circuit is further configured to detect a voltage level of the selected bit line and select another bit line when the detected voltage level indicates that the selected OTP cell is in a programmed state.