5 results about "Sequential programming" patented technology

A method of programming a memory cell having a floating gate by applying a first program pulse to the memory cell to place electrons on the floating gate, wherein the first program pulse comprises a program voltage that includes a preliminary voltage level in a first portion of the first program pulse and a first voltage level in a second portion of the first program pulse, wherein the first voltage level is greater than the preliminary voltage level. The first voltage level is applied immediately successive to the preliminary voltage level. Then, applying successive program pulses to the memory cell to place additional electrons on the floating gate, wherein the successive program pulses include the program voltage, and wherein the program voltage increases in voltage level for each one of the successive program pulses relative to a previous one of the successive program pulses or the first program pulse.

A three tier memory has an upper sub block, a lower sub block, and a middle sub block. In the present disclosure, rather than precharging the upper and lower sub blocks, use is made of the middle sub block using a firmware (FW) scheme. Upon receiving a write request from a host, the FW will route the data to the middle sub block (SB1) through reverse order programming (ROP) so that the SB1 is pre-charged through the source side through the lower sub block (SB0). Once the SB1 is written, data is then routed to the SB0 and then to the upper sub block (SB2). When there is a garbage collection (GC) request, the FW will move the data from the SB2 and then erase the SB2. Then the data moves from the SB0 and SB0 is erased. Finally, the data moves from the SB1 and then SB1 is erased.

A storage device is disclosed herein. The storage device comprises a non-volatile memory, where the non-volatile memory includes a block of 3N wordlines partitioned into a plurality of sub-blocks. The plurality of sub-blocks include an upper sub-block of a first subset of the block of 3N wordlines, a lower sub-block of a second subset of the block of 3N wordlines, and a middle sub-block of a third subset of the block of 3N wordlines. Further, the storage device comprises control circuitry coupled to the block of 3N wordlines and configured to: perform a program operation in a normal order programming sequence on the upper sub-block; perform a program operation in a reverse order programming sequence on the lower sub-block; and perform a program operation in the reverse order programming sequence on the middle sub-block.

A method of programming a memory cell having a floating gate by applying a first program pulse to the memory cell to place electrons on the floating gate, wherein the first program pulse comprises a program voltage that includes a preliminary voltage level in a first portion of the first program pulse and a first voltage level in a second portion of the first program pulse, wherein the first voltage level is greater than the preliminary voltage level. The first voltage level is applied immediately successive to the preliminary voltage level. Then, applying successive program pulses to the memory cell to place additional electrons on the floating gate, wherein the successive program pulses include the program voltage, and wherein the program voltage increases in voltage level for each one of the successive program pulses relative to a previous one of the successive program pulses or the first program pulse.

Methods, systems, and devices for corrupt block detection for write ordering are described. A memory system may be configured to implement a sequential programming order or a reverse programming order based on dynamically reconfiguring memory dies to support storing data or parity data. For example, a memory system may receive a write command for writing data and parity data to a block stripe spanning the memory dies of the memory system. The memory system may determine whether the block stripe includes a corrupted block at a parity die of the memory system. The memory system may perform a write operation corresponding to the write command using the sequential programming order based on determining the block stripe does not include the corrupted block at the parity die, or the reverse programming order based on determining the block stripe includes the corrupted block at the parity die.