3 results about "Sequential programming" patented technology

A method of programming a memory cell having a floating gate by applying a first program pulse to the memory cell to place electrons on the floating gate, wherein the first program pulse comprises a program voltage that includes a preliminary voltage level in a first portion of the first program pulse and a first voltage level in a second portion of the first program pulse, wherein the first voltage level is greater than the preliminary voltage level. The first voltage level is applied immediately successive to the preliminary voltage level. Then, applying successive program pulses to the memory cell to place additional electrons on the floating gate, wherein the successive program pulses include the program voltage, and wherein the program voltage increases in voltage level for each one of the successive program pulses relative to a previous one of the successive program pulses or the first program pulse.

A method of programming a memory cell having a floating gate by applying a first program pulse to the memory cell to place electrons on the floating gate, wherein the first program pulse comprises a program voltage that includes a preliminary voltage level in a first portion of the first program pulse and a first voltage level in a second portion of the first program pulse, wherein the first voltage level is greater than the preliminary voltage level. The first voltage level is applied immediately successive to the preliminary voltage level. Then, applying successive program pulses to the memory cell to place additional electrons on the floating gate, wherein the successive program pulses include the program voltage, and wherein the program voltage increases in voltage level for each one of the successive program pulses relative to a previous one of the successive program pulses or the first program pulse.

Methods, systems, and devices for corrupt block detection for write ordering are described. A memory system may be configured to implement a sequential programming order or a reverse programming order based on dynamically reconfiguring memory dies to support storing data or parity data. For example, a memory system may receive a write command for writing data and parity data to a block stripe spanning the memory dies of the memory system. The memory system may determine whether the block stripe includes a corrupted block at a parity die of the memory system. The memory system may perform a write operation corresponding to the write command using the sequential programming order based on determining the block stripe does not include the corrupted block at the parity die, or the reverse programming order based on determining the block stripe includes the corrupted block at the parity die.