Error correcting memory systems

A memory system and data memory technology, applied in the field of computing memory, can solve the problems of changing the matrix, unable to use "reading and recovery, drifting, etc.

Pending Publication Date: 2021-06-08
SUPERMEM INC
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  • Abstract
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  • Application Information

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Problems solved by technology

However, most of these devices will drift during operation, gradually changing the value of the matrix multiplicand
If the

Method used

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Embodiment Construction

[0106] In the following description of the embodiments, reference is made to the accompanying drawings, which are shown by way of example of specific embodiments that may be practiced, as part of this description. Other embodiments may, of course, be utilized and structural changes may be made without departing from the scope of the disclosed embodiments.

[0107] figure 1 A memory system including memory system 100 is depicted. In some embodiments, memory system 100 is electrically coupled to host 160 and memory controller 170 . In some examples, memory system 100 may include more than 1 GB of storage space on a single die.

[0108] In some examples, host 160 or memory controller 170 may generate a flush data command to initiate data scrubbing of data memory in memory system 100 , or generate a protect command to initiate protection of data memory in memory system 100 . In some examples, the conditions for generating the command to initiate the flush data can be programmed...

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Abstract

Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.

Description

technical field [0001] The present invention generally relates to computing memory, and more specifically, the present invention relates to an apparatus and method for error correction of computing memory. Background technique [0002] Magnetic Random Access Memory (MRAM), Phase Change Memory (PCM), Resistive Random Access Memory (RRAM), and Ferroelectric Random Access Memory (FRAM) are some nonvolatile memory technologies that can be faster than FLASH Data write speed and higher rewrite durability. For example, high-performance MRAM can be used in edge artificial intelligence computing (Edge-AI) applications, which require complex data structures after model optimization. [0003] To achieve high performance, non-volatile memories like MRAM present many unique circuit challenges. In particular, read performance is limited due to read disturb errors under higher voltage read operations, and write performance is limited due to hard break down under higher voltage operations...

Claims

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Application Information

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IPC IPC(8): G06F3/06G06F11/10G11C29/00G11C29/52H03M13/00
CPCG11C29/52H03M13/19H03M13/152H03M13/1515H03M13/1102G06F11/106G11C2029/0409G11C2029/0411G11C7/04G06F3/064G06F3/0619G06F3/0611G06F3/0688G06F3/0659G06F11/1044G06F3/0644G06F3/0653G06F11/1068G11C11/161
Inventor 陆宇林潔予
Owner SUPERMEM INC
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