ECC memory manager, ECC memory management method and electronic equipment

Abstract

The invention discloses an ECC memory manager, an ECC memory management method and electronic equipment. A bus interface module is provided with a register group and is used for configuring configuration information of an ECC memory manager. The memory can be freely divided into an ECC memory area and a common memory area according to an address space; the ECC error correction function of the memory is freely switched; when the ECC memory area is configured to be 0, namely an ECC closed state, the two memory areas are consistent with a conventional use mode; and when the ECC is in an open state and an effective memory area range is configured, an ECC check value is generated at the corresponding ECC area address for all byte data written into the ECC memory area through the ECC error correction calculation module, and errors of the read data are carefully detected and corrected through the ECC error correction calculation module. Therefore, the invention has the technical characteristics that the memory utilization rate is high, the ECC function can be freely switched on and off, the size of the ECC memory is adjustable, and the read-write speed is high.

Description

technical field [0001] The invention belongs to the technical field of memory, and in particular relates to an ECC memory manager, method and electronic equipment. Background technique [0002] ECC is the abbreviation of "Error Correcting Code", and the Chinese name is "Error Correcting Code". ECC is a technology that can realize "error checking and correction". ECC memory is the memory that applies this technology, making the whole system more secure and stable when working. ECC can correct single-bit or multi-bit errors in the memory, and the calculation speed is very fast. This allows errors to be tolerated in the memory and corrected so that the system continues to operate normally without being interrupted by errors. [0003] For memories such as flash that perform erasing and writing operations in units of blocks or pages, an ECC check can be performed on the entire page (for example, 512 bytes) to generate a small amount of ECC check codes. However, for SRAM memory...

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Problems solved by technology

But this means that the data must be read and written in 32 bits. When only one byte of data is written, it is also necessary to read back the 32-bit data first, modify the byte data, and then perform an ECC check on the entire 32-bit word before writing it back. , which makes the read and write speed of byte data several times slower than the original

[0005] To sum up, memory security measures, memory overhead, and memory read / write speed are mutually restrictive, and system-on-chip designers can only choose a compromise solution to lose one or two of the performance

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