39 results about "Logic error" patented technology

The invention relates to the technical field of computers, and provides an agent generation method and device, a computer program product and electronic equipment. The method comprises the steps of generating an initial code corresponding to code task description information based on a pre-trained code generation model; code inspection is conducted on the initial code, when the inspection result indicates that the initial code has a code fault, the initial code is repaired based on the code fault, and a repaired code is generated; performing code logic error checking on the repair code, generating a repair strategy of the repair code based on the code improvement knowledge graph under the condition that a logic error checking result indicates that the repair code has a logic error, and inputting the repair strategy to the code generation model; enabling the code generation model to improve the repair code based on the repair strategy and the code task description, updating the repair code according to an improvement result, and iteratively executing the process until a preset condition is met, so as to obtain a target code. The code generation accuracy can be improved.

The invention provides a security tool access method for a security protection system and a related device. The security tool access method comprises the following steps: acquiring first guidance information of a first security tool; analyzing the first guidance information by using a first artificial intelligence model, and generating a first access scheme of the first security tool; obtaining a first running log; and in response to the fact that the first operation log represents that the first access scheme has a logic error, analyzing the first operation log by using a second artificial intelligence model, and determining a corrected first access scheme. According to the access method of the security tool, security protection systems such as a cloud security protection product and a security agent can quickly and efficiently access different types of third-party security tools.

The invention belongs to the technical field of software test automation, and discloses an automatic test script repair method and related device.The method comprises the steps that feature data in the test script execution process are obtained; detecting a preset error problem of the test script based on the feature data in the execution process of the test script to obtain a problem detection result of the test script; wherein the preset error problem of the test script comprises a grammar error, a logic error, an interface error and an interface error of the test script; based on the problem detection result of the test script, selecting an optimal repair strategy from a pre-constructed repair strategy library, and generating a repair instruction based on the optimal repair strategy; based on the repair instruction, performing automatic repair operation on the test script; according to the method and the device, automatic repair of the test script is realized, a tester does not need to manually check and modify codes related to the interface elements in the script one by one, time and labor cost are greatly saved, and test efficiency is remarkably improved.

The invention discloses a text error correction method and system based on logic consistency detection, a medium and equipment, and the method comprises the following steps: S1, receiving a text input by a user, carrying out grammar and semantic analysis on the input text, and extracting a logic relationship in the text; s2, performing consistency check on the extracted logic relationship through a preset logic rule base; s3, when the logic is detected to be inconsistent, generating a logic error prompt and recommending a correction suggestion; and S4, correcting the logic error according to user feedback, and performing secondary verification on the corrected text. The method has the advantages that logic errors in the text can be automatically recognized, the correct logic relation of the text is ensured, and the workload of manual auditing is reduced.

The invention provides an automatic test and quality evaluation system for game development. The system improves the diversity of test coverage and the precision of physical logic error detection. Firstly, a collision recovery coefficient and an initial random seed are collected through a physical engine bottom layer interface, and a standard physical parameter set is constructed; secondly, generating a test case set by adopting disturbance offset and a random trigger mechanism, and realizing scene disturbance simulation; and finally, performing difference analysis on a test result by calculating time sequence data such as a period, event response time and a frame rendering interval, and automatically correcting physical parameters and a trigger sequence based on feedback to realize closed-loop optimization. According to the method, three types of data including a periodic sequence, an event response timestamp sequence and a frame rendering interval sequence are introduced, a frame-level physical logic consistency criterion is established, and the problems of abnormal performance fluctuation, event delay and frame imbalance are finely captured through a combined judgment mechanism of a difference index and a tolerance threshold.

The application discloses a kind of UVM verification platform automatic generation system and method based on generative artificial intelligence, the system includes generative AI dynamic anchoring module, LLM-VCS self-feedback verification module and conflict detection correction module;The generative AI dynamic anchoring module is used to solve the context window limit problem on large language model, by the key component in UVM platform is marked as anchor file and generates subsequent file based on dependency relationship priority;LLM-VCS self-feedback verification module cooperates with large language model and EDA tool chain, forms closed loop system from specification input to UVM platform generation, simulation and debugging;The conflict detection correction module is used to detect and correct the interface inconsistency and logic error between generated files.The application can adapt to the verification needs of different RTL designs, effectively solve the interface consistency problem of high coupling between UVM modules, flexibly generate UVM platform of different structures, significantly improve the verification efficiency and quality.

The invention discloses an interface testing method and device, electronic equipment and a storage medium. The method comprises the steps of obtaining basic information of a to-be-tested interface and description information of a test case; on the basis of the basic information and the description information, constructing cue words; processing the cue word through a large language model, and generating a test script of the to-be-tested interface; and executing the test script to obtain test data of the to-be-tested interface, analyzing the test data through an artificial intelligence agent AI Agent to obtain an analysis result, and using the analysis result to optimize the test script and / or the test case. In this way, the test script can be quickly and automatically generated, the tedious process of traditional manual script writing is avoided, the generation efficiency of the test script is greatly improved, the problem of logic errors or inconsistent code styles possibly occurring during manual writing is avoided, and the quality and normalization of the test script are improved.

The invention belongs to the related technical field of analog-to-digital conversion, and discloses a dynamic logic circuit and a successive approximation type analog-to-digital converter, the dynamic logic circuit comprises a dynamic logic unit and a capacitor lower pole plate multiplexer switch, the first stage of the dynamic logic unit adopts a dynamic D trigger, the second stage adopts a dynamic latch, and the second stage adopts a successive approximation type analog-to-digital converter. The output end of the dynamic latch is additionally provided with a switch tube M14 and a switch tube M15 to form a pair of cross-coupled switch tubes, after the DP end and the DN end sample the output of the comparator, if DP is high level and DN is low level, the DP switches on the tube M14, so that DN is not influenced by charge leakage and always keeps low level, and if DP is low level and DN is high level, the DN switches on the tube M15, so that the DN is not influenced by charge leakage and always keeps low level. Therefore, the DP is not influenced by charge leakage and is always kept at a low level, so that the stability of an output result can be maintained, the influence of the charge leakage on the output result is reduced, and a logic error caused by the charge leakage is avoided.

The application discloses a flood scheduling gate operation logic anti-misoperation method and device based on rule self-learning, and particularly relates to the technical field of gate scheduling control systems. Trend results are generated by differentially determining the signs of the inflow and reservoir water level, consistency checking is performed in combination with the discharge variation direction and gate opening instruction to form an effective instruction sequence; the residual space amount of the downstream sensitive area is calculated, and the channel impact coefficient is generated in combination with the discharge impact amount and channel conditions; on this basis, the over-limit channel flow is reduced and distributed to the normal channel to form a rechecked sharing result. The application can realize trend dynamic judgment and instruction direction matching, guarantee discharge adjustment and hydrological condition consistency, and through the closed logic of reduction and distribution, the multi-channel flow sharing structure is optimized, the gate adjustment sequence logic is set according to the gate operation principle of the power station design, automatic matching of the discharge and gate adjustment is realized, and the situation of lower gate operation order is prevented.

An error injection technique involves: receiving a logic error including an injection address parameter and an injection error parameter, and matching the injection address parameter in the logic error with a request address parameter in a response to a data request in at least one workflow. The technique further involves: in a case that the injection address parameter is matched with the request address parameter, injecting the injection error parameter into the response to the data request. Such a technique provides a flexible error injection mode, which may fully test the reliability and availability of storage devices, thereby providing high-quality storage services for users.

The invention discloses a large language model reasoning path pruning method based on a satisfiability model theory, and aims to solve the problems that a heuristic evaluator depended by a multi-path reasoning framework such as an existing thinking tree is unreliable and the calculation cost is too high due to the unreliable heuristic evaluator. An intermediate reasoning step generated by a large language model LLM is automatically converted into formalized logic constraint, a satisfiability model theory SMT solver is used for carrying out millisecond-level satisfiability verification, logically inconsistent error reasoning branches can be actively and instantly recognized and cut off, and therefore computing resources are concentrated on potential correct branches. According to the method, the defects that an existing method passively accepts logic errors and depends on an unreliable evaluator, so that resources are wasted are overcome, the accuracy and reliability of large language model LLM complex reasoning are remarkably improved, and meanwhile the calculation overhead and token consumption are greatly reduced.

This application relates to a method and system for auditing operation timing logic based on state tracking, comprising: initializing and maintaining a device state tracker to record the state of the operated device during the simulated execution of an operation ticket; sequentially parsing the operation ticket, identifying the type of the current step in the operation ticket, and converting the current step into a structured instruction according to the type of the current step; the structured instruction includes a device identifier, an initial state, and a target state, or a device identifier and a target state; performing timing logic consistency verification based on the state records in the device state tracker according to the type of the current step and its structured instruction, and updating the device state tracker; outputting a successful audit result if all steps in the operation ticket pass the verification; and suspending the audit if any step in the operation ticket contains a timing logic error, and outputting an audit exception result containing the location and type of the timing logic error, thereby realizing the audit of operation timing logic.

The invention provides a built-in SQL (Structured Query Language) function logic error detection method and device based on function attribute driving. The method comprises the following steps: acquiring a built-in SQL function set; a triple model is constructed for each function in the built-in SQL function set to obtain a built-in SQL function model library, and each built-in SQL function model comprises signature, constraint and attribute information; generating a function expression according to a built-in SQL function model library, and embedding the function expression into a rich-context SQL statement to obtain an original SQL query set; analyzing the original SQL query set into an abstract syntax tree, traversing the abstract syntax tree to position function nodes, and constructing a variant SQL query set by applying function transformation through intra-function transformation or inter-function transformation; performing result comparison on the original SQL query set and the variable SQL query set to detect whether a built-in SQL function with a logic error exists or not; therefore, efficient and accurate detection of the built-in SQL function logic error is realized.

The present invention discloses a modeling verification and code generation method for integrated circuit design, including: dividing the functions in the requirement design document into different VerilogHDL statement modules, the VerilogHDL statement modules include top-level modules and bottom-level modules; filling the top-level module code, bottom-level module code, top-level module port number and bottom-level module port number into the corresponding module table respectively according to the internal functions and ports of the top-level module and the bottom-level module; verifying whether the code in the module table conforms to the principle of synthesizable model; verifying the syntax structure and logical structure of the code in the module table; filling in the functions required to be implemented by the code in the module table, and functionally verifying the principle of synthesizable model; converting the code that conforms to the principle of synthesizable model, syntax structure, logical structure and functional verification into usable VerilogHDL code. The present invention ensures that the code implementation stage conforms to the principle of synthesizable model, and reduces code implementation errors and functional logic errors.

The invention relates to a software code debugging technology, discloses a method for software debugging by using a code template technology, and aims to solve the problems that a software debugging tool supports too few programming languages and is not uniform in debugging means. Code templates are respectively adapted to different high-level languages for debugging, so that the supported programming languages are dozens of types, a unified debugging means is provided for the debugging of each programming language, breakpoints can be lowered, detailed code tracks can be output, so that collapse, crash and logic errors can be easily and accurately positioned, different assignments of variables can be completely recorded, code resource management can be tracked, and the debugging efficiency is improved. According to the method, time consumption statistics can be conducted on each line of codes, a unified debugging means can be provided for a single-chip microcomputer, an operating system kernel, a driver, an embedded type and the like through serial port terminals, numerous programming languages are supported, a unified debugging means is provided for debugging of the programming languages, and the software debugging technology is enriched.

The application discloses a kind of based on multidimensional system integrated interconnection assembly and assembly method, interconnection assembly is arranged between printed board, the interconnection assembly includes: protection unit;The inside of the protection unit forms a accommodating cavity, the inside of the accommodating cavity is provided with connecting unit;The connecting unit extends to the direction of multiple end surfaces of the protection unit, and is worn to the outside of the protection unit, and the printed board at different end surfaces of interconnection assembly is connected by the connecting unit;Through the interconnection assembly designed in the application, the interconnection of three faces of parallel printed board and vertical printed board can be realized, the assembly density of product is improved, the size of product is reduced, the length of interconnection line transmission can be shortened, signal noise is reduced, in high-performance system, the problem that excessively long interconnection line not only influences signal transmission quality but also causes logic error is solved.

The application provides a built-in SQL function logic error detection method and device based on function attribute driving, wherein the method comprises the following steps: obtaining a built-in SQL function set; constructing a triple model for each function in the built-in SQL function set to obtain a built-in SQL function model library, wherein each built-in SQL function model comprises signature, constraint and attribute information; generating a function expression according to the built-in SQL function model library and embedding the function expression into a rich context SQL statement to obtain an original SQL query set; parsing the original SQL query set into an abstract syntax tree and locating a function node by traversing the abstract syntax tree to apply function transformation by function internal conversion or function interconversion to construct a variant SQL query set; comparing the original SQL query set and the variant SQL query set to detect whether there is a built-in SQL function with a logic error; and thus, efficient and accurate detection of the built-in SQL function logic error is realized.

The invention discloses a modeling method and device based on a natural language, modeling requirements described by a user in a natural language form are automatically converted into Revit AP I calling or script commands based on a code matching model obtained through large language model training, the tedious process that the user manually searches nodes and parameters one by one in a Dynamo or Revit interface is omitted, and the modeling efficiency is improved. According to the method and the device, the dependency on professional operation knowledge of the Revit platform is greatly reduced, meanwhile, the retrieved first code text is normalized according to a preset code template or style, so that a script structure and a naming specification can be unified, subsequent maintenance and secondary development are facilitated, and the method and the device can also be used for performing static analysis or simple rule verification. Possible grammar or logic errors are found in advance, the correctness and readability of generated codes can be ensured, the manual debugging time is shortened, and the modeling efficiency is improved.

The application discloses a kind of nuclear safety grade DCS system engineering application software logic comparison method and device, it is related to nuclear power technical field, the underlying data in engineering application software is based on in the present application, the logic comparison of different units or different versions of engineering application software is realized, a large number of false positives caused by comparison based on image recognition technology is solved, the misidentification problem caused by the large displacement of the element position in drawing is eliminated, and it is also unnecessary to train through artificial intelligence big model, the workload of designer is reduced, the misidentification of comparison result caused by different algorithm modules used by different designers and different design styles is eliminated, work efficiency and work quality are greatly improved, and logic error caused by human error is avoided.

The application relates to the technical field of intelligent monitoring of rail transit trains, and discloses a train man-machine interface display intelligent analysis method based on artificial intelligence. The method analyzes the dynamic evolution track of the interface state in a historical period, evaluates the stability of display elements, and predicts potential fault paths. Simulated operations are applied to logic conflict nodes, underlying service features and user operation behavior features are separated from mixed responses, and independent tracing and positioning are respectively performed. The method can realize early warning of abnormal behaviors of interface elements, accurately distinguish and position different levels of faults caused by system service defects and interactive logic errors, and provides a core technical means for intelligent monitoring and efficient maintenance of a train man-machine interface.

A package structure and a related preparation method thereof are disclosed. The package structure includes: an interposer; and a logic chip structure and a signal channel structure that are located on a surface of the interposer, where the logic chip structure includes a logic chip on a surface of the interposer and a power supply channel structure on a surface of the logic chip. A power supply layer of the logic chip is close to the power supply channel structure, which is electrically connected to a corresponding conductive structure to achieve power supply. A signal layer of the logic chip is close to the interposer and connected to the corresponding conductive structure to realize signal transmission. In this way, the power supply does not interfere with signals, and a logic error is avoided; and an overall voltage and power consumption of a finished package is significantly reduced.

The application relates to a five-prevention logic auditing method and device for a power transformation operation ticket and a computer device. The method comprises the following steps: obtaining power transformation operation ticket data, identifying operation steps of equipment in the power transformation operation ticket data, extracting operation verbs and equipment numbers in the operation steps, sequentially obtaining five-prevention locking logic conditions of equipment corresponding to the equipment numbers, obtaining equipment states of target equipment, the target equipment being equipment contained in the five-prevention locking logic conditions of the current equipment, updating the states of the current target equipment when the equipment states of the target equipment meet the five-prevention locking logic conditions of the current equipment, and returning to the step of sequentially obtaining the five-prevention locking logic conditions of the target equipment corresponding to the equipment numbers according to the operation verbs and the equipment numbers. The method can quickly and accurately identify five-prevention logic errors in the power transformation operation ticket, and can avoid power grid accidents.

The invention relates to the technical field of smart building control, and discloses a cross-subsystem event-driven linkage control method and system for a smart building. The method comprises the following steps: performing deep detection and time sequence extraction on original operation data to obtain a two-dimensional time sequence data set; constructing a life cycle attenuation model and packaging to obtain a standardized data sequence; constructing a backtracking buffer pool, executing reverse interpolation and holding operation to generate virtual data points, and executing discretization segmentation to generate a time sequence alignment event slice sequence; and executing a logic replay matching operation to obtain an event set, executing a state judgment and instruction generation operation, and generating a self-adaptive cooperative control instruction. According to the method, sequential logic errors caused by heterogeneous network transmission uncertainty and sampling frequency aliasing are eliminated, the problems of causal inversion and decision lag of cross-system linkage are solved, and precise research and judgment and reliable control of global perception are achieved.

The application relates to the technical field of intelligent building control and discloses a cross-subsystem event-driven linkage control method and system for intelligent buildings. The method comprises the following steps: deeply detecting and time-series extracting original operation data to obtain a two-dimensional time-series data set; constructing a life cycle attenuation model and encapsulating to obtain a standardized data sequence; constructing a backtracking buffer pool, performing reverse interpolation and retention operations to generate virtual data points, and performing discretization segmentation to generate a time-series alignment event slice sequence; performing a logic replay matching operation to obtain an event set, performing state arbitration and instruction generation operations, and generating adaptive collaborative control instructions. The application eliminates time-series logic errors caused by heterogeneous network transmission uncertainty and sampling frequency aliasing, solves the problems of causal inversion and decision lag in cross-system linkage, and realizes accurate research and reliable control of global perception.

The embodiment of the invention provides a data query method, electronic equipment, a storage medium and a program product, and is applied to the technical field of computers. The method comprises the following steps: receiving a query statement sent by a terminal, wherein the query statement comprises a plurality of commands for the same data table; analyzing the data table identifier and the type of each command from each command, obtaining a preset strategy, and determining the execution sequence of each command according to the preset strategy and the type of each command; the preset strategy comprises a plurality of preset types and a correct execution sequence of each preset type; judging whether the execution sequence of each command is the same as the corresponding original sequence, if not, constructing a linked list array, and sequentially adding each command into the linked list array according to the execution sequence; and obtaining the data table according to the data table identifier, and obtaining a query result based on the linked list array added with the command and the data table. Execution abnormity caused by logic errors of the input sequence is avoided, and the efficiency and success rate of data table query are improved.

The invention provides a test oracle generation system based on LLM, and belongs to the field of software test automation. In order to solve the problems of low manual writing efficiency, LLM logic distortion and time sequence verification deficiency, retrieval enhancement (code / defect / contract triple constraint), confidence self-inspection (triple evaluation) and state sequence modeling (probe capture dynamic trajectory) technologies are adopted, and efficient and accurate oracle generation is realized. The method is mainly applied to system testing of finance, e-commerce and the like, the assertion generation speed is increased by 200 times, the logic error rate is reduced to 7%, and the time sequence defect capture rate reaches 82%.

This application discloses a method, apparatus, device, and medium for assertion code verification based on a pre-trained model, relating to the field of code generation technology. The method includes: extracting timing relationships from hardware design code; obtaining corresponding reference assertion code based on the timing relationships, and inputting the timing relationships into a pre-trained model after describing them in natural language to generate assertion code to be tested; integrating both into the same verification environment and applying an excitation signal, recording each successful trigger moment during simulation; comparing the successful trigger moments of the assertion code to be tested with those of the reference assertion code, and determining the functional correctness index of the assertion code to be tested based on the number of time matchings and the total number of triggers of the reference assertion code; and evaluating the functional correctness of the assertion code generated by the model based on the functional correctness index. Through the technical solution of this application, assertion logic errors can be avoided, establishing a benchmark and feedback loop for the reliable application of pre-trained models in the verification field.

The invention discloses a DBMS logic defect detection-oriented value semantic perception metamorphic test method and system, and relates to the technical field of database management, and the method comprises the following steps: designing a basic grammar for a to-be-tested DBMS to construct an original query; locally rewriting the original query to generate a variation query, wherein the original query and the variation query meet an approximate relationship; analyzing the original query and the variation query into an abstract syntax tree AST, searching a propagation link locally rewritten on the AST, and generating a query-level approximation relationship between the original query and the variation query; and executing the original query and the variation query on the to-be-tested DBMS, collecting an execution result, comparing the execution result with the query-level approximation relationship, and judging whether a logic defect exists or not. The invention provides a unified SQL (Structured Query Language) query approximation model fusing ensemble semantics and value semantics reasoning, and logic errors in a database management system are detected by changing SQL queries and spreading semantic approximation.

The utility model relates to the field of automation control and robot technology discloses a kind of self-adapting location-finding devices, comprising: terminal execution mechanism, for executing preset processing task, terminal execution mechanism includes installation base, and two groups of execution units are symmetrically provided on installation base;XY axis self-adapting mechanism, for clamping workpiece, to adjust own position;Z axis positioning mechanism, for adjusting terminal execution mechanism, XY axis self-adapting mechanism position according to workpiece position.The utility model is by being provided with terminal execution mechanism cooperation XY axis self-adapting mechanism, Z axis positioning mechanism, cancels complex kinematics solution, using precision operation mechanism replaces visual identification, laser scanning, realize in mechanism automatic tracing, reduce complex motion example, realize low code or no code operation, realize quick use and simple operation, save human resources, the cost of from production and manufacture, use maintenance, remanufacture etc. obviously reduce, reduce logic error.

The invention discloses a nuclear security level DCS system engineering application software logic comparison method and device, relates to the technical field of nuclear power, realizes logic comparison of engineering application software of different units or different versions based on underlying data in the engineering application software, solves a large amount of false alarms caused by comparison based on an image recognition technology, and improves the reliability of the engineering application software. The problem of misrecognition caused by a large amount of displacement of element positions in the drawing is eliminated, artificial intelligence large model training is not needed, the workload of designers is reduced, misrecognition of comparison results caused by different algorithm modules and different design styles used by different designers is eliminated, the working efficiency and the working quality are greatly improved, and the method is suitable for popularization and application. And logic errors caused by human errors are avoided.