133 results about "Logic error" patented technology

A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units and may consecutively dispatch a same floating-point instruction stream to a floating-point unit. The integer execution units may operate in lock-step such that during each clock cycle, each respective integer execution unit executes the same integer instruction. The floating-point unit may execute the same floating-point instruction stream twice. Prior to the integer instructions retiring, compare logic may detect a mismatch between execution results from each of the integer execution units. In addition, prior to the results of the floating-point instruction stream transferring out of the floating-point unit, the compare logic may also detect a mismatch between results of execution of each consecutive floating-point instruction stream. Further, in response to detecting any mismatch, the compare logic may cause instructions causing the mismatch to be re-executed.

In accordance with embodiments of the present invention, methods and systems analyze potential logic errors or problems of a business application by receiving a model representing the business application and processing the model using an object-oriented tool. The errors or problems may be corrected in the model and the correction applied to the business application. In one exemplary embodiment, the logic errors or problems may be marked in the model for identification to a user.

A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units operating in lock-step. The processor core also includes signature generation logic that may generate, concurrently with execution of the integer instructions, a respective signature from result signals conveyed on respective result buses in one or more pipeline stages within each of the integer execution units in response to the result signals becoming available. The processor core also includes compare logic that may detect a mismatch between signatures from each of the integer execution units. Further, in response to the compare logic detecting any mismatch, the compare logic may cause instructions causing the mismatch to be re-executed.

The invention discloses an anomaly detection method specific to an IEC61850 protocol SV (Sample Value) message. The method comprises the following steps: firstly, detecting a format and configuration information of a frame of SV message, and ending subsequent detection if any of the format and the configuration information is wrong; if the format and the configuration information of the SV message are correct, continuing to perform logic analysis on an smpCnt value to judge whether abnormal phenomena such as disorder, loss and repetition of the message occur or not; if the smpCnt value is free from a logic error, continuing to detect state information of the SV message in order to detect whether the SV message is in an interrupt state or a synchronous state; and finally, if the message is not in an abnormal state, continuing to detect quality values (test and validity) of the message, and judging whether a quality factor of the message is abnormal or not. The method has the advantages of comprehensive analysis and clear logic, is simple, clear and efficient, and can be applied to online data analysis and anomaly detection of transformer substations.

This invention relates to a new type of input low voltage/over voltage protection circuit used in assistant supply including a voltage sample circuit, a logic control circuit, a back lash control circuit used in low voltage back lash processing said sample output to be output to said logic control circuit, which ensures outputs of the assistant supply can fall to the safety low voltage and then starts up when the input meets with quick falling, transient, glittering or low frequency interference to avoid logic errors.

The invention discloses an orbital tracking method. The method comprises: searching, in an electronic map, a position of a physical section to be checked in an orbit line and the physical section round the physical section to be checked; determining whether the physical section to be checked and the physical section around the physical section to be checked are in an occupancy state or an idle state; if the sections are in the idle state, directly sending the state of the physical section to be checked to interlocking equipment; if the sections are in the occupancy state, further determining whether a logic section within the physical section to be checked and a logic section within the physical section around the physical section to be checked are in the occupancy state or the idle state; if the sections are in the idle state, directly guiding an automatic protecting system ATP of a ground train to a safe side, and warning in a downtime way that a logic error exists. The method avoids that the ground ATP system directly is directly guided to the safe side due to the logic error, and avoids a situation that affects the operation safety of the system like losing the car in a complex circumstance.

The invention discloses a fault-tolerant error correction decoding method and a fault-tolerant error correction decoding device of a quantum circuit, and a chip, which relate to the technical field ofartificial intelligence and quanta. The fault-tolerant error correction decoding method comprises the following steps of: acquiring real error symptom information of a quantum circuit, wherein the real error symptom information is obtained by performing noisy error symptom measurement on the quantum circuit by adopting a quantum error correction code; decoding the real error symptom information to obtain a logic error class and perfect error symptom information corresponding to the real error symptom information; and determining error result information of the quantum circuit according to thelogic error class and the perfect error symptom information, wherein the error result information is used for indicating data quantum bits with errors in the quantum circuit and corresponding error types. According to the fault-tolerant error correction decoding method and the fault-tolerant error correction decoding device, fault-tolerant error correction decoding is equivalent to a classification problem, so that an efficient neural network classifier is suitable to be adopted for performing fault-tolerant error correction decoding on the error symptom information, the fault-tolerant errorcorrection decoding speed is increased, and real-time fault-tolerant error correction decoding can be realized.

The invention discloses an automatic simulated verification system used for SDH/SONET logical design, which comprises a data generation unit for generating excitation data and positioning information, and a data detection unit for receiving the processed data of the logic to be test. The invention also discloses an automatic simulated verification method. The method comprises: determining the excitation bus and detection bus in the system, setting the corresponding configuration of the excitation bus, generating the excitation data and judging whether to adjust and process the pointer; outputting the excitation data and the corresponding positioning information; setting the corresponding configuration of the detection bus; and judging whether the data received by the detection bus is correct. The inventive system and method can rapidly, simply and efficiently provide a stimulating effect, realize the real-time detection of processed data of the logic to be test, and give an alarm when detecting logic error, thereby facilitating a user to position and modulate the logic error.

A method for backing up data of hard disc includes fetching file system of hard disc data into internal memory of computer system before back-up, automatically detecting logic error existed in file system of hard disc data, repairing detected out logic error of file system according in internal memory and backing up hard disc data with correct file system to mirror image file.

The invention discloses a basic electricity fee error detection method and a system based on a power grid charging system. The detection method comprises steps of anomaly analysis on capacity and demand and electricity consumption logic errors, line and transformer loss demand errors, capacity and demand comparison basic electricity fee errors, newly-installed user basic electricity fee errors, transformer pause errors, separate account avoidance basic electricity fee errors and error integration on electricity consumption charging data of the user in the power grid charging system sequentially. The detection system comprises a data acquisition unit, a capacity and demand and electricity consumption logic error detection unit, a line and transformer loss demand error detection unit, a capacity and demand comparison basic electricity fee error detection unit, a newly-installed user basic electricity fee error detection unit, a transformer pause error detection unit, a separate account avoidance basic electricity fee error unit and an error integration units totally corresponding to the basic electricity fee error detection method. Thus, the method and the system of the invention have the advantages that the basic electricity fee error anomalies can be accurately judged, the outstanding problems can be quickly found out and solved timely, and electricity fee errors can be effectively reduced.

The invention discloses a data processing method and device, and relates to the technical field of computers. The method comprises the steps that a service request sent by a web server is received; a corresponding request object and various corresponding statistics types are obtained according to the service request; a recording account ID is established by the request object and the various statistics types, responding data of a target server are obtained from the corresponding server of the request object through the web server, and recording is conducted according to the recording account ID. Accordingly, the data processing method and device solves the problems that the data size of analysis processing is large, the efficiency is low, the transaction process can not be recorded clearly, and logic errors can occur easily when late statistics is conducted. The advantages that the data size of analysis processing can be lowered, the processing efficiency is improved, interaction process data are recorded clearly, the service logic in the late statistics can be simple, and the statistics accuracy can be improved are achieved.

The invention discloses a power grid equipment data acquisition method and system. The method comprises the following steps: obtaining storage data from a service system, querying and analyzing the storage data to obtain storage problem data; according to the storage problem data, generating an acquiring and recording task; an acquiring and recording terminal obtaining the acquiring and recording task; according to the acquiring and recording task, acquiring and recording data of power grid equipment to be acquired to obtain acquiring and recording data; and according to the acquiring and recording, updating the storage data. According to the invention, the storage problem data is obtained by analyzing the storage data and is taken as a basis for acquiring and recording, such that the acquiring and recording data amount can be greatly reduced, data with information errors or logic errors can be accurately re-acquired, and the data acquisition efficiency is improved; and the acquiring and recording data is uploaded to the service system such that the acquiring and recording data can be conveniently managed.

Aspects disclosed in the detailed description include integrated circuit (IC) design methods using engineering change order (ECO) cell architectures. In particular, exemplary aspects provide a fill algorithm that is both single- and multi-row aware, considers a poly-pitch count, and utilizes metallization of the “empty space” relative to a suite of available fill cells. The algorithm is also aware of timing critical logic elements and may place ECO fill cells in near proximity to such timing sensitive circuits or other margin critical circuits to allow for decoupling or, if there is a logic error, an ECO cell is placed such that the ECO cell is well positioned to be repurposed as a delay circuit or other function to aid in margin control. For maximum flexibility, the algorithm may also address both pre- and post-route applications.

The invention relates to an industrial control system, aiming at providing a visualization method of industrial control network topology structure. The visualization method comprises the steps of: deploying a platform into the industrial control network which needs topology to ensure that the equipment in the industrial control network can reach; according to the position of the platform in the industrial control network, scanning the equipment in the industrial control network by the timing task, and saving the node information in the database, using the integrated node information to obtainthe topological line;according to the obtained topological line, returning the port connection information of each equipment, drawing the connection relationship between each equipment node, and finally obtaining the topological network diagram of the industrial control network. The invention adopts a very simple way, that is, the network structure requiring topology is obtained through the most basic ARP protocol and the SNMP protocol, and the structure is displayed on the visual interface, thereby avoiding the logic error that may occur in the complex algorithm.

The invention relates to a logic node tree-shaped visual game editing engine. Different name lists are constructed by adopting tree-shaped programming, wherein the name lists of a logic set are arranged at the left side of a visual programming interface; the name lists correspond to the function lists in programming languages; a tree-shaped logic list is arranged at the right side of the visual programming interface; in a programming process, execution of the whole programming logic is started from a first line; the nodes are equipped with different icons for distinguishing different logic properties of the nodes; the part at the most right side of the visual programming interface is the attribute setting part of a single node; dynamical adjustment can be carried out according to the currently selected nodes; and the most lower part of the visual programming interface is equipped with a debugging operation interface. According to the method provided by the invention, logic errors resulting from typing errors can be reduced; the tree-shaped structure is clear in logic and is convenient for organizing and reading the logic; and the speed and efficiency of debugging the logic can be greatly improved.

The invention discloses a method, a device, a system and a storage medium for storing data by an elastic block. The method comprises the following steps: a distributed file system Ceph is set as a system for storing data, and the communication protocol of the Ceph is an rbd protocol; a request for elastic block storage data with Ceph based on iSCSI protocol is received; upon request, the rbd protocol and the iSCSI protocol are converted; the elastic block stores data according to the converted same protocol. On the one hand, the embodiment of the invention can avoid the risk of logic error dueto the local hard disk mapped by ceph, effectively reduce the failure rate and improve the stability of the system; on the other hand, the embodiment of the invention can reduce the system performance consumption and the service response time delay by reducing one mapping.

A system and method for detecting and rectifying a proscribed non-complementary output from a complementary logic circuit. A complementary logic circuit having a true tree and a complement tree is provided. The true tree produces a true signal utilized to generate a true output signal from the complementary logic circuit. The complement tree produces a complement signal utilized to generate a complement output signal from the complementary logic circuit. Logic means coupled to the output of the complementary logic circuit detect an occurrence of a non-complementary output from the complementary logic circuit. Multiplexing means within the true tree is utilized to selectively replace the true signal with the complement signal within the true tree in response to detection by the logic means of a non-complementary output, such that a non-complementary output is seamlessly detected and rectified.