Simulation checking system and its method for SDH logical design

Abstract

The invention discloses an automatic simulated verification system used for SDH / SONET logical design, which comprises a data generation unit for generating excitation data and positioning information, and a data detection unit for receiving the processed data of the logic to be test. The invention also discloses an automatic simulated verification method. The method comprises: determining the excitation bus and detection bus in the system, setting the corresponding configuration of the excitation bus, generating the excitation data and judging whether to adjust and process the pointer; outputting the excitation data and the corresponding positioning information; setting the corresponding configuration of the detection bus; and judging whether the data received by the detection bus is correct. The inventive system and method can rapidly, simply and efficiently provide a stimulating effect, realize the real-time detection of processed data of the logic to be test, and give an alarm when detecting logic error, thereby facilitating a user to position and modulate the logic error.

Description

Technical field [0001] The present invention relates to logic design technology in the field of optical communications, in particular to a simulation verification technology for logic design circuits in the field of optical communications. Background technique [0002] At present, in the optical synchronous digital transmission system, with the widespread application of large-scale logic circuits and the increasing complexity of logic functions, the test scheme for verifying whether the logic functions are correct has become very complicated and cumbersome. As a result, for logic design verification engineers, the problem of how to simply and efficiently determine whether the logic circuit functions are correct has become more prominent, and it has also become a major difficulty in the current simulation verification technology of logic design circuits. [0003] In the prior art, there are mainly the following test schemes to verify whether the logic design circuit is correct. On...

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Problems solved by technology

[0004] However, for the first method, it is only suitable for the test situation where the logic design function is relatively simple. Once the function of the logic design is relatively complicated, it is difficult to guarantee the accuracy and reliability of the analysis results by using the waveform observation method, and it is even possible Lead to potential errors in logic design functions; on the other hand, when using programmable logic devices such as FPGAs for logic verification, FPGAs with a huge number of logic gates are required, which are costly and long-term

Moreover, the logic design circuit to be tested must be verified only when the FPGA-based hardware circuit has been debugged; even if the FPGA-based hardware circuit is debugged, once a logic error occurs in the logic design circuit to be tested, the test environment gives There is less help information, and it is very difficult to locate logic errors

For the third method, although rigorous verification results can be obtained, it is quite complicated and cumbersome to use software programming to imitate hardware functions, and because the logic functions implemented by different logic verification projects are different, then for different logic Verification projects need to independently write different behavioral models, which is difficult to achieve modular programming and lacks versatility

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