Method for testing communication bandwidth of 10-gigabit network between FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit) applied to radar system

Abstract

The invention provides a method for testing the communication bandwidth of a 10-gigabit network between an FPGA (Field Programmable Gate Array) and a CPU (Central Processing Unit), which is applied to a radar system. The FPGA completes a function of regularly generating data and a function of downlink transmission of the data; the 10-gigabit network exchange board card completes data transmission and sends data to the CPU board card through a 10-gigabit network; and the CPU board card receives the data and calculates the communication bandwidth and the network quality. According to the invention, the limitation of traditional single-port point-to-point transmission or simple multi-port parallel transmission on synchronization, load balancing or protocol overhead is solved, and a solution is provided for how to effectively utilize multiple ports, enable the multiple ports to simultaneously and efficiently work and ensure parallel transmission of data without mutual interference.

Description

Technical Field

[0001] This invention relates to the field of radar testing, and in particular to a method for testing the communication bandwidth of a 10 Gigabit Ethernet between an FPGA and a CPU in a radar system. The method is mainly used to test the ideal network bandwidth and the estimated bandwidth of services under this connection, and to determine the network quality level based on the difference between the estimated bandwidth of services and the ideal network bandwidth, thus laying the foundation for 10 Gigabit Ethernet communication between an FPGA and a CPU in a radar system. Background Technology

[0002] With the development of fiber optic technology, traditional Ethernet transmission can no longer meet the ever-evolving needs of technological advancements, making the demand for higher-capacity, higher-speed data transmission technologies increasingly urgent. This is especially true in the radar field, where the requirements for high data rates and strong real-time performance pose even greater challenges to communication technologies. Therefore, 10 Gigabit Ethernet (10 Gigabit Network) has emerged. 10 Gigabit Ethernet is a computer network technology used to transmit data at a rate of 10 gigabits per second, providing faster data transmission speeds and greater efficiency in handling complex data processing tasks. For radar systems requiring high bandwidth and low latency transmission, 10 Gigabit Ethernet offers a perfect solution.

[0003] The proposed bandwidth testing method for 10 Gigabit Ethernet aims to develop a universal bandwidth testing method for FPGA-CPU communication. Utilizing multi-port synchronization and multi-threading design principles, it tests the ideal network bandwidth of the link and the estimated bandwidth for specific services. The difference between these two values ​​determines the network quality level, thereby revealing the maximum available bandwidth for a specific service and improving the accuracy and effectiveness of 10 Gigabit Ethernet bandwidth testing results.

[0004] Currently, in radar systems, communication between FPGAs and CPUs primarily relies on PCIe and SRIO, with limited research on 10 Gigabit Ethernet (10 Gigabit Ethernet) technology. This lack of testing methods and communication quality analysis for 10 Gigabit Ethernet bandwidth leads to unclear data transmission bandwidth and low efficiency. Therefore, to address these data transmission bottlenecks in radar systems, research is urgently needed on testing methods for 10 Gigabit Ethernet communication bandwidth between FPGAs and CPUs. Summary of the Invention

[0005] To overcome the shortcomings of existing technologies, this invention provides a method for testing the communication bandwidth of a 10 Gigabit Ethernet network between an FPGA and a CPU in a radar system. It is mainly used to test the ideal network bandwidth and estimated service bandwidth of a 10 Gigabit Ethernet network, thereby analyzing network quality and improving the accuracy and effectiveness of network bandwidth test results.

[0006] The technical solution adopted by this invention to solve its technical problem is:

[0007] A method for testing the communication bandwidth of a 10 Gigabit Ethernet network between an FPGA and a CPU in a radar system, comprising the following steps:

[0008] Step 1: The FPGA generates test data and sends large blocks of data in parallel through different ports. Dynamic load balancing based on real-time link status is implemented on the FPGA. The minimum queue depth algorithm is used to allocate data streams according to the port latency or congestion of real-time traffic.

[0009] Step 2: Use UDP protocol for data transmission to avoid TCP congestion control overhead. Implement a selective retransmission mechanism on the FPGA side and use the FPGA hard core to implement UDP checksum calculation to improve processing efficiency; combine with CPU-side cache sorting to improve reliability.

[0010] Step 3: Enable dynamic LACP on the 10 Gigabit Ethernet switching board, and combine it with the MAC / IP multi-homing configuration of the FPGA to achieve logical single-link bandwidth aggregation. At the 10 Gigabit Ethernet switching board, allocate a dedicated VLAN and DiffServ code point for FPGA-CPU traffic to ensure traffic priority forwarding. After receiving data, parse the data according to IP address, MAC address and port number to complete data distribution.

[0011] Step 4: Use DPDK (Data Plane Development Kit) on the CPU board to bypass the kernel protocol stack and directly access the network card DMA buffer, reducing latency and binding the receiving thread to a specific NUMA node and CPU core to reduce cache invalidation and context switching overhead.

[0012] Step 5: Monitor the throughput, packet loss rate and latency of each port under a certain IP address range in real time on the CPU board, and dynamically adjust the FPGA transmission strategy through the out-of-band management channel PCIe;

[0013] Step 6: Simultaneously, the CPU board records the bandwidth, end-to-end latency, jitter, and packet out-of-order rate of different ports to provide a comprehensive performance evaluation.

[0014] Step 7: Evaluate network quality based on bandwidth test results.

[0015] The specific steps of step 7 are as follows:

[0016] The Interval data is input into iperf3 to calculate the standard deviation. When the volatility in the standard deviation is less than 5%, it is grade A. At this time, the nping tool is used to test the UDP packet round-trip latency. The average latency is required to be less than 50us, the jitter is required to be less than 10us, the 10 Gigabit link is continuously fully loaded for 30 minutes, and the packet loss rate is less than 0.001%. If all four conditions are met, the network quality is considered to meet the requirements.

[0017] A system for testing the communication bandwidth of a 10 Gigabit Ethernet between an FPGA and a CPU in a radar system includes an FPGA, a 10 Gigabit Ethernet switching board, and a CPU board. The FPGA performs the functions of timed data generation and downlink data transmission; the 10 Gigabit Ethernet switching board performs data transmission and sends data to the CPU board via the 10 Gigabit Ethernet; and the CPU board receives the data and calculates the communication bandwidth and network quality.

[0018] The system for testing the communication bandwidth of 10 Gigabit Ethernet between FPGA and CPU in a radar system is implemented through multiple ports. During system operation, the FPGA generates test data and sends it to the 10 Gigabit Ethernet switching board through different communication ports. The 10 Gigabit Ethernet switching board sends the data to the CPU board through the 10 Gigabit Ethernet according to the FPGA's sending instructions. The CPU board summarizes the bandwidth of different ports. The sending instructions include IP, MAC address, and port. Each IP address segment is allocated several ports. The bandwidth of several ports under this IP is summarized as the measured bandwidth of that IP address segment. By summarizing and classifying the bandwidth according to different ports, the difference between the measured bandwidth and the actual bandwidth can be reduced, providing more accurate statistical data for calculating network quality levels.

[0019] The beneficial effects of this invention lie in its method for testing the communication bandwidth of a 10 Gigabit Ethernet between an FPGA and a CPU in a radar system. This method primarily enables multi-port 10 Gigabit Ethernet bandwidth testing to determine network quality, providing a reliable means to improve the effectiveness of 10 Gigabit Ethernet bandwidth testing. It overcomes the limitations of traditional single-port point-to-point transmission or simple multi-port parallel transmission in terms of synchronization, load balancing, and protocol overhead. It offers a solution for effectively utilizing multiple ports to ensure efficient simultaneous operation and parallel data transmission without mutual interference. Attached Figure Description

[0020] Figure 1 This invention relates to a hardware architecture for 10 Gigabit Ethernet communication bandwidth between an FPGA and a CPU in a radar system.

[0021] Figure 2 This is a flowchart of a method for testing the communication bandwidth of a 10 Gigabit Ethernet network between an FPGA and a CPU in a radar system. Detailed Implementation

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] like Figure 2 As shown, the steps of a method for testing the communication bandwidth of a 10 Gigabit Ethernet between an FPGA and a CPU in a radar system are as follows:

[0024] Step 1: The FPGA generates test data and sends large blocks of data in parallel through different ports. Dynamic load balancing based on real-time link status is implemented on the FPGA. The minimum queue depth algorithm is used to allocate data streams according to the port latency or congestion of real-time traffic.

[0025] Step 2: Use UDP protocol for data transmission to avoid TCP congestion control overhead. Implement a selective retransmission mechanism on the FPGA side and use the FPGA hard core to implement UDP checksum calculation to improve processing efficiency; combine with CPU-side cache sorting to improve reliability.

[0026] Step 3: Enable dynamic LACP on the 10 Gigabit Ethernet switching board, and combine it with the MAC / IP multi-homing configuration of the FPGA to achieve logical single-link bandwidth aggregation. At the 10 Gigabit Ethernet switching board, allocate a dedicated VLAN and DiffServ code point for FPGA-CPU traffic to ensure traffic priority forwarding. After receiving data, parse the data according to IP address, MAC address and port number to complete data distribution.

[0027] Step 4: Use DPDK technology on the CPU board to bypass the kernel protocol stack and directly access the network card DMA buffer to reduce latency. Also, bind the receiving thread to a specific NUMA node and CPU core to reduce cache invalidation and context switching overhead.

[0028] Step 5: Monitor the throughput, packet loss rate and latency of each port under a certain IP address range in real time on the CPU board, and dynamically adjust the FPGA transmission strategy through the out-of-band management channel PCIe;

[0029] Step 6: Simultaneously, the CPU board records the bandwidth, end-to-end latency, jitter, and packet out-of-order rate of different ports to provide a comprehensive performance evaluation.

[0030] Step 7: Evaluate network quality based on bandwidth test results. Calculate the standard deviation using iperf3 Interval data. A volatility of less than 5% is grade A. Use the nping tool to test UDP packet round-trip latency, requiring an average latency of less than 50us and jitter of less than 10us. Test a 10 Gigabit link under continuous full load for 30 minutes, with a packet loss rate of less than 0.001%.

[0031] like Figure 1 As shown, a system for testing the communication bandwidth of a 10 Gigabit Ethernet between an FPGA and a CPU in a radar system comprises three parts: an FPGA, a 10 Gigabit Ethernet switching board, and a CPU board. The FPGA performs the functions of timed data generation and downlink data transmission; the 10 Gigabit Ethernet switching performs the function of data transmission and sending data to the CPU via the 10 Gigabit Ethernet; and the CPU board receives the data and calculates the communication bandwidth and network quality.

[0032] The communication bandwidth testing method is performed through multiple ports: During system operation, the FPGA generates test data and sends it to the 10 Gigabit Ethernet switching board through different communication ports. The switching board, based on the FPGA's sending instructions (IP, MAC address, port), sends the data to the CPU board via the 10 Gigabit Ethernet. The CPU board then aggregates the bandwidth from different ports. Each IP address segment is allocated several ports, and the bandwidth of these ports is aggregated to form the measured bandwidth for that IP address segment. Categorizing and aggregating bandwidths according to different ports reduces the discrepancy between measured and actual bandwidth, providing more accurate statistical data for determining network quality.

[0033] The key technical points of this invention are: 1. A multi-port testing method for 10 Gigabit Ethernet; 2. A mode architecture for communication testing between CPU and FPGA; 3. Analyzing and determining network quality by summarizing the test bandwidth of multiple ports.

[0034] This invention relates to a method for testing the communication bandwidth of a 10 Gigabit Ethernet between an FPGA and a CPU in a radar system. It is primarily used to perform multi-port 10 Gigabit Ethernet bandwidth testing to determine network quality, providing a reliable means to improve the effectiveness of 10 Gigabit Ethernet bandwidth testing. It overcomes the limitations of traditional single-port point-to-point transmission or simple multi-port parallel transmission in terms of synchronization, load balancing, and protocol overhead. It provides a solution for effectively utilizing multiple ports, enabling multiple ports to work efficiently simultaneously, and ensuring parallel data transmission without mutual interference.

Claims

1. A method for testing the communication bandwidth of a 10 Gigabit Ethernet network between an FPGA and a CPU in a radar system, characterized in that... Includes the following steps: Step 1: The FPGA generates test data and sends large blocks of data in parallel through different ports. Dynamic load balancing based on real-time link status is implemented on the FPGA. The minimum queue depth algorithm is used to allocate data streams according to the port latency or congestion of real-time traffic. Step 2: Use UDP protocol for data transmission to avoid TCP congestion control overhead. Implement a selective retransmission mechanism on the FPGA side and use the FPGA hard core to implement UDP checksum calculation to improve processing efficiency. Improve reliability by combining CPU-side cache sorting; Step 3: Enable dynamic LACP on the 10 Gigabit Ethernet switching board, and combine it with the MAC / IP multi-homing configuration of the FPGA to achieve logical single-link bandwidth aggregation. At the 10 Gigabit Ethernet switching board, allocate a dedicated VLAN and DiffServ code point for FPGA-CPU traffic to ensure traffic priority forwarding. After receiving data, parse the data according to IP address, MAC address and port number to complete data distribution. Step 4: Use DPDK (Data Plane Development Kit) on the CPU board to bypass the kernel protocol stack and directly access the network card DMA buffer, reducing latency and binding the receiving thread to a specific NUMA node and CPU core to reduce cache invalidation and context switching overhead. Step 5: Monitor the throughput, packet loss rate and latency of each port under a certain IP address range in real time on the CPU board, and dynamically adjust the FPGA transmission strategy through the out-of-band management channel PCIe; Step 6: Simultaneously, the CPU board records the bandwidth, end-to-end latency, jitter, and packet out-of-order rate of different ports to provide a comprehensive performance evaluation. Step 7: Evaluate network quality based on bandwidth test results.

2. The method for testing the communication bandwidth of a 10 Gigabit Ethernet network between an FPGA and a CPU in a radar system according to claim 1, characterized in that: The specific steps of step 7 are as follows: The Interval data is input into iperf3 to calculate the standard deviation. When the volatility in the standard deviation is less than 5%, it is grade A. At this time, the nping tool is used to test the UDP packet round-trip latency. The average latency is required to be less than 50us, the jitter is required to be less than 10us, the 10 Gigabit link is continuously fully loaded for 30 minutes, and the packet loss rate is less than 0.001%. If all four conditions are met, the network quality is considered to meet the requirements.

3. A test system for testing the communication bandwidth of a 10 Gigabit Ethernet network between an FPGA and a CPU in a radar system, as described in claim 1, comprising an FPGA, a 10 Gigabit Ethernet switching board, and a CPU board, characterized in that: The system described in the invention relates to a method for testing the communication bandwidth of a 10 Gigabit Ethernet network between an FPGA and a CPU in a radar system. The FPGA performs timed data generation and downlink data transmission; the 10 Gigabit Ethernet switching board performs data transmission and sends data to the CPU board via the 10 Gigabit Ethernet network; and the CPU board receives the data and calculates the communication bandwidth and network quality.

4. The method for testing the communication bandwidth of a 10 Gigabit Ethernet network between an FPGA and a CPU in a radar system according to claim 3, characterized in that: The system for testing the communication bandwidth of 10 Gigabit Ethernet between FPGA and CPU in a radar system is implemented through multiple ports. During system operation, the FPGA generates test data and sends it to the 10 Gigabit Ethernet switching board through different communication ports. The 10 Gigabit Ethernet switching board sends the data to the CPU board through the 10 Gigabit Ethernet according to the FPGA's sending instructions. The CPU board summarizes the bandwidth of different ports. The sending instructions include IP, MAC address, and port. Each IP address segment is allocated several ports. The bandwidth of several ports under this IP is summarized as the measured bandwidth of that IP address segment. By summarizing and classifying the bandwidth according to different ports, the difference between the measured bandwidth and the actual bandwidth can be reduced, providing more accurate statistical data for calculating network quality levels.

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