Method for improving transmission quality of twenty-five gigabit symmetric passive optical network and related device

Abstract

The invention relates to the technical field of optical network transmission, in particular to a twenty-five gigabit symmetric passive optical network transmission quality improvement method and a related device. The method comprises the steps that PCB routing layout optimization is conducted on an LD + / LD-differential signal line in a transmission link, impedance control over the differential signal line is achieved by adjusting the wiring gap and the wiring width of the LD + / LD-differential signal line and the integrity of a reference layer area, the consistency difference in PCB production is improved, and loss and interference in the signal transmission process are reduced. The PCB layout parameters of the LD + / LD-differential signal line are specifically optimized, the wiring gap is adjusted from 11.49 mi of a reference golden finger bonding pad to 5.75 mi of a reference chip BGA bonding pad, the wiring width is reduced from 20 mi to 10 mi, the integrity of a reference layer area is synchronously optimized, the differential impedance is accurately controlled from original 30 ohms to 60 ohms, and the reliability of the circuit is improved. And the parasitic parameter influence in signal transmission is effectively suppressed.

Description

Technical Field

[0001] This invention relates to the field of optical network transmission technology, specifically to a method and related apparatus for improving the transmission quality of a 25 Gigabit symmetrical passive optical network. Background Technology

[0002] In 25G SPON transmission, the incompleteness of high-speed differential signals restricts the performance of optical modules. In existing technologies, the printed circuit board (PCB) layout design of the transmission link typically references the electrical parameters of traditional interface pads, such as using the gap and width of the gold finger pads as the basis for routing LD+ / LD- differential signal lines. However, such designs do not fully consider the impedance matching differences between chip-level packages such as BGA pads and the transmission interface. This leads to "coarsening" of the eye diagram envelope during differential signal transmission due to insufficient routing parameters and reference layer integrity, resulting in degraded signal-to-noise margin and timing symmetry deviations between rising and falling edges. Specifically, in prototype testing, the eye diagram margin is generally below 25%, such as... Figure 2 As shown, the signal quality consistency of different batches of products is difficult to control. The core reason is that the traditional layout strategy does not make fine-grained design for the impedance characteristics of high-speed differential signals. There is room for optimization in the timing of the bias voltage access path and the timing of the laser driving signal, which leads to the accumulation of reflection, crosstalk and phase distortion during signal transmission. Summary of the Invention

[0003] This disclosure proposes a method and related apparatus for improving the transmission quality of a 25 Gigabit symmetrical passive optical network, with the aim of overcoming at least one defect in the prior art.

[0004] To achieve the above objectives, the technical solution disclosed in this invention is as follows:

[0005] According to one aspect of this disclosure, a method for improving transmission quality in a 25 Gigabit symmetric passive optical network is provided, the method comprising the steps of:

[0006] PCB routing layout optimization is performed on the LD+ / LD- differential signal lines in the transmission link. By adjusting the wiring gap, wiring width, and reference layer area integrity of the LD+ / LD- differential signal lines, impedance control of the differential signal lines is achieved, which is used to improve consistency differences in PCB production and reduce signal loss and interference during signal transmission.

[0007] The impedance control accuracy of the LD+ / LD- differential signal lines is optimized from 30 ohms to 60 ohms, and the PCB process is controlled based on the impedance control accuracy. The eye diagram envelope used for signal link testing is refined to improve signal quality.

[0008] In the PCB layout, the LD+ bias voltage access position is adjusted to be closer to the laser, the MFB9 with the same value as the MFB6 is added, a 0-ohm resistor MR104 is connected across the power supply network line, the MC79 filter capacitor is reserved and the MFB6 position is reserved, which is used to slow down the introduction timing of the LD+ bias voltage excitation signal, so that the rising curve in the eye diagram envelope is delayed in the time domain.

[0009] Further, the wiring gap of the LD+ / LD- differential signal line is adjusted from the original gold finger pad gap of 11.49 mil to the BGA pad gap of 5.75 mil, and the wiring width of the LD+ / LD- differential signal line is adjusted from the original gold finger pad of 20 mil to the BGA pad of 10 mil. The impedance simulation result for realizing the differential signal line is 60.80 ohms, so as to match the impedance requirement of high-speed signal transmission and reduce signal reflection and distortion.

[0010] Further, the MFB6 is not added, and the MFB9 and the MR104 are replaced, which are used to access the data transmission position of the bias power supply later. The time domain position of the bias voltage access is adjusted to increase the eye diagram margin caused by the dislocation of the intersection point of the rising curve and the falling curve in the eye diagram envelope, and to improve the symmetry of signal transmission.

[0011] Further, the power supply network line provides stable bias voltage for the laser, and the MR104 is connected as a short circuit line between the power supply network line and the LD+ bias voltage access point to form a low-impedance signal transmission path. The MFB9 and the MFB6 have the same parameters, which are used to maintain the stability of the bias voltage. The time domain delay of the bias voltage excitation signal is realized by adjusting the hardware layout, so as to optimize the time symmetry of the rising edge and the falling edge in the eye diagram and expand the signal decision window.

[0012] Further, the PCB wiring layout optimization includes a reference layer of the entire LD+ / LD- differential signal line, so as to ensure that the reference plane of the differential signal line on the transmission path is continuous and has no breakage, and to reduce the influence of parasitic parameters on signal transmission. In the impedance control process, the wiring gap, width and reference layer parameters of the differential signal line are jointly simulated to verify the optimized impedance matching effect, so as to narrow the eye skin area of the eye diagram envelope and improve the clarity of the signal eye diagram.

[0013] According to another aspect of the present disclosure, a twenty-five thousand gigabit symmetric passive optical network transmission quality improvement circuit is provided for implementing the twenty-five thousand gigabit symmetric passive optical network transmission quality improvement method as described above, and the circuit comprises:

[0014] A laser driver circuit for generating LD+ and LD- differential signals;

[0015] The impedance matching circuit is connected with the laser driver circuit, and includes an LD+ / LD- differential signal line, a wiring gap of the differential signal line is 5.75 mil, a wiring width of the differential signal line is 10 mil, and a differential impedance of the differential signal line is controlled to be 60 ohms with an accuracy of ±10 ohms, and a reference layer area of the differential signal line is complete without fracture, so as to optimize the transmission impedance of the differential signal and reduce signal loss.

[0016] The bias voltage adjustment circuit is connected with the LD+ signal end of the laser driver circuit, and includes an MFB9 with the same value as the MFB6, a 0-ohm resistor MR104, and a reserved MC79 filter capacitor, the MR104 is connected in cross between a power supply network line and the LD+ signal end, the MFB9 is connected in series on a transmission path of the bias voltage, and the MC79 filter capacitor is connected in parallel between the LD+ signal end and the ground, so as to delay the access time of the LD+ bias voltage and optimize the eye diagram symmetry.

[0017] Further, an input end of the LD+ / LD- differential signal line is connected with a differential signal output end of a laser driver chip, and an output end is connected to a gold finger pad of an optical module; the differential signal line is routed according to the gap and width parameters of a reference BGA pad in a PCB layout, and the reference layer is an inner layer signal reflow plane of the PCB, so as to suppress common mode noise.

[0018] The position of the MFB6 is reserved without being mounted, and the combination of the MFB9 and the MR104 is connected in an access path; the power supply network line provides a 3.3V direct current bias voltage for the laser, the MR104 is used as a short-circuit line to reduce the impedance of the bias voltage transmission, and the MC79 filter capacitor is used to filter high-frequency noise to ensure the stability of the bias voltage.

[0019] Further, the system further includes a power filter module connected with the laser driver circuit, the power filter module includes a plurality of decoupling capacitors connected in parallel to a power input end, so as to suppress the interference of power noise on the laser driving signal; a ground protection wire is arranged around the LD+ / LD- differential signal line, the ground protection wire is connected with a ground layer of the PCB, so as to reduce the influence of external electromagnetic interference on the differential signal transmission, and improve the signal transmission quality in cooperation with the impedance matching circuit.

[0020] According to another aspect of the present disclosure, a system for improving the transmission quality of a 25-gigabit symmetric passive optical network is provided, which is integrated with the 25-gigabit symmetric passive optical network transmission quality improvement circuit as described above, and the system includes:

[0021] A signal processing module is configured to generate and process a differential signal of the 25-gigabit symmetric passive optical network.

[0022] The impedance control module integrates an impedance matching circuit for 60-ohm impedance control of the LD+ / LD- differential signal lines, including adjusting the wiring gap, width, and reference layer integrity.

[0023] The layout optimization module integrates a bias voltage adjustment circuit, which is used to adjust the LD+ bias voltage input position and delay the timing of the introduction of the bias voltage excitation signal.

[0024] The production control module is used to control the process of the optimized PCB to ensure the impedance parameters and wiring accuracy of the LD+ / LD- differential signal lines.

[0025] The differential signal generated by the signal processing module is impedance matched by the impedance control module, and after the bias voltage timing is adjusted by the layout optimization module, it is output to the optical module to improve the eye diagram margin and transmission quality.

[0026] According to another aspect of this disclosure, a storage medium is provided that stores a computer program, which, when executed by a processor, implements the method for improving the transmission quality of a 25 GHz symmetric passive optical network as described above.

[0027] The beneficial effects of this invention are:

[0028] This invention optimizes the PCB layout parameters of the LD+ / LD- differential signal lines, adjusting the wiring gap from 11.49 mil for the reference gold finger pad to 5.75 mil for the reference chip BGA pad, reducing the wiring width from 20 mil to 10 mil, and simultaneously optimizing the integrity of the reference layer area. This allows the differential impedance to be precisely controlled from 30 ohms to 60 ohms, effectively suppressing the influence of parasitic parameters in signal transmission, reducing signal reflection and common-mode noise, thereby refining the eye diagram envelope area and improving the clarity of the signal decision window.

[0029] Furthermore, by adding an MFB9 with the same parameters in the schematic and PCB layout, bridging a 0-ohm resistor MR104 to a specific power supply network line, and reserving a filter capacitor MC79, the LD+ bias voltage access position was optimized, the timing of the introduction of the bias excitation signal was delayed, and the rising and falling curves in the eye diagram envelope became more symmetrical in the time domain, the intersection point deviation was significantly reduced, and the eye diagram margin was ultimately increased to over 32.1%.

[0030] This invention, through the synergistic optimization of hardware layout and impedance control, not only solves the engineering problem of insufficient signal quality consistency in existing technologies, but also ensures the electrical performance stability of mass-produced PCBs through strict control of impedance parameters in the manufacturing process. This provides a reliable technical path for the large-scale application of 25G SPON optical modules, fundamentally improving the transmission quality and industrial feasibility of symmetrical passive optical networks.

[0031] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the following describes the preferred embodiments of the present invention in detail with reference to the accompanying drawings. Attached Figure Description

[0032] Figure 1 This is a flowchart of a method for improving the transmission quality of a 25 Gigabit symmetrical passive optical network in one embodiment of the present invention;

[0033] Figure 2 This is a schematic eye diagram of the transmitted signal in one embodiment of the present invention. Figure 1 ;

[0034] Figure 3 This is a schematic diagram of the PCB layout in one embodiment of the present invention. Figure 1 ;

[0035] Figure 4 This is a schematic diagram of the PCB layout in one embodiment of the present invention. Figure 2 ;

[0036] Figure 5 This is a schematic diagram illustrating the differences in PCB layout in one embodiment of the present invention;

[0037] Figure 6 This is a simulation diagram of differential line impedance in one embodiment of the present invention. Figure 1 ;

[0038] Figure 7 This is a simulation diagram of differential line impedance in one embodiment of the present invention. Figure 2 ;

[0039] Figure 8 This is a schematic eye diagram of the transmitted signal in one embodiment of the present invention. Figure 2 ;

[0040] Figure 9 This is a circuit diagram for improving the transmission quality of a 25 Gigabit symmetrical passive optical network in one embodiment of the present invention. Detailed Implementation

[0041] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0042] The present application provides the following preferred embodiments:

[0043] Embodiment one: In order to solve the problem of insufficient signal quality consistency and limited eye diagram margin caused by PCB layout parameters and bias voltage access timing in 25G symmetrical passive optical network transmission, this embodiment provides a 25G symmetrical passive optical network transmission quality improvement method, which further optimizes the electrical connection and layout design of the transmission link. As shown in the figure, Figure 1 The flow of the method is as follows:

[0044] S100: The LD+ / LD- differential signal line in the transmission link is optimized for PCB wiring layout. By adjusting the wiring gap, wiring width and reference layer area integrity of the LD+ / LD- differential signal line, the impedance control of the differential signal line is realized, which is used to improve the consistency difference in PCB production and reduce the loss and interference in the signal transmission process.

[0045] S200: The impedance control precision of the LD+ / LD- differential signal line is optimized from the original 30 ohms to 60 ohms, and the PCB process is controlled based on the impedance control precision, which is used for eye diagram envelope refinement of signal link test and improves signal quality.

[0046] S300: In the PCB layout, adjust the LD+ bias voltage access position to be closer to the laser, add MFB9 with the same value as MFB6, cross 0 ohm resistance MR104 to the power supply network line, reserve MC79 filter capacitor and keep MFB6 position, which is used to slow down the introduction timing of LD+ bias voltage excitation signal, and make the rising curve in the eye diagram envelope delayed in time domain.

[0047] Specifically, for the transmission characteristics of the LD+ / LD- differential signal line, first, the fine adjustment of the printed circuit board wiring layout is carried out: in the PCB design stage, abandon the traditional reference "gold finger" pad layout strategy, and instead take the electrical parameters of the chip side BGA pad as the benchmark, reduce the wiring gap of the differential signal line from 11.49 mil to 5.75 mil, and optimize the wiring width from 20 mil to 10 mil. The parameter setting is matched with the physical size of the BGA pad and the signal transmission demand, which can effectively reduce the influence of parasitic capacitance and inductance of the wiring. At the same time, through the integrity optimization of the reference layer area, it is ensured that the differential signal has a continuous and uniform return path in the transmission process, avoiding the impedance mutation caused by the reference layer fracture or discontinuity.

[0048] Further, to achieve precise impedance control, the impedance control target of the differential signal line is adjusted from the original 30 ohms to 60 ohms, and the impedance precision is maintained within ±10 ohms through PCB process control means. It should be understood that the adjustment of this impedance parameter is not a simple numerical change, but an optimized solution determined through joint simulation and verification of parameters such as trace width, dielectric layer thickness, and dielectric constant based on high-speed differential signal transmission theory using electromagnetic simulation software. During PCB production, by controlling the substrate thickness tolerance, copper foil roughness, and etching process parameters, the actual impedance of each layer of differential signal line is ensured to match the design value, thereby suppressing reflection loss and crosstalk noise during signal transmission, and refining the eye diagram envelope in signal link testing to provide a clearer window for subsequent signal decision.

[0049] Further, regarding the optimization of the LD+ bias voltage access position, specific circuit adjustment measures are taken in the PCB layout: during schematic design, an MFB9 component of the same specification as MFB6 is added, and it is connected to the power supply network line labeled "N21117471" through a 0-ohm resistor MR104, and the access point is as close as possible to the laser package position in the layout, as shown in Figures 3 to 5 It should be noted that the position of MFB6 is retained and the MC79 filter capacitor pad is reserved to provide debugging redundancy for subsequent adaptation to different brands of lasers. The essence of this layout adjustment is to shorten the physical distance of the bias voltage transmission path, optimize the component selection and connection method, and delay the actual injection time of the bias voltage excitation signal, so that the rising edge of the laser drive signal is controllably delayed in the time domain. This timing adjustment can effectively correct the misalignment of the intersection point of the rising curve and the falling curve in the prior art, and promote the symmetric distribution of the two around the axis in the eye diagram, thereby expanding the effective decision region of the eye diagram.

[0050] The benefits of the present embodiment are that, through precise control of the layout parameters of the differential signal line and optimization of the bias voltage access timing, a transmission link design scheme that takes into account impedance matching and signal timing is constructed. This scheme not only solves the problem of signal loss caused by inconsistent differences in PCB production, but also improves the transmission quality of high-speed signals from the physical layer through the coordinated optimization of electromagnetic compatibility design and circuit layout, providing a reusable technical path for the engineering production of twenty-five thousand gigabit symmetric passive optical network optical modules. Those skilled in the art can understand that the selection of the type of each element in the above specific embodiments, such as the parameters of MFB9 and MR104, and the setting of the layout rules, are based on signal integrity theory and actual simulation verification to ensure that each technical feature forms an organic whole in solving the transmission quality problem.

[0051] Example 2: To address the issue of "too thick" eye diagram envelope lines, impedance control and simulation were performed on the LD+ / LD- differential signal lines. This was done to optimize wiring gaps, wiring widths, and the integrity of the reference layer area, thereby improving consistency differences in PCB production.

[0052] like Figures 3 to 5 As shown, the LD+ / LD- differential line routing gap is 11.49mil, as indicated by the pink arrow on the right, and the routing width is approximately 20mil, as indicated by the pink arrow on the right, as indicated by the pink arrow.

[0053] In the optimized design, the LD+ / LD- differential line routing gap is 5.75 mil, referencing the "BGA" pad gap of the left-side chip, as shown by the blue arrow. The routing width is approximately 10 mil, referencing the diameter of the "BGA" pad of the left-side chip, as shown by the orange arrow (8 mil). In the original design, the LD+ / LD- differential line impedance simulation results were as follows: Figure 6 As shown, the differential impedance is approximately 38.60Ω. After optimization, the simulation results for the LD+ / LD- differential line impedance are as follows: Figure 7 As shown, the differential impedance is approximately 60.80.

[0054] Furthermore, regarding the asymmetry caused by the "misalignment" of the intersection points of the upper and lower edges of the eye diagram envelope, analysis revealed that the rising curve of the eye diagram rises too quickly, while the falling curve lags behind with a time delay. Based on the schematic and layout, the LD+ bias voltage input position was adjusted to be closer to the laser to improve this. Specifically, in the schematic and PCB layout, MFB9 paired with MR104 was used to replace the MBF6 component. This utilizes the spatial distance to slow down the entry of the bias power supply into the data transmission, allowing the bias voltage excitation signal of the LD+ to be introduced "later." This achieves a time-domain delay in the two rising curves within the eye diagram envelope, effectively "shifting" the eye diagram to the right. This provides more white space in the eye, allowing the eye to open wider. Figure 8 As shown.

[0055] Embodiment three: To solve the problem of insufficient eye diagram symmetry caused by the inaccuracy of the timing coordination between the bias voltage excitation signal access opportunity and the laser driver signal in the prior art, the embodiment further optimizes the hardware configuration and connection relationship of the bias voltage adjustment circuit. In the circuit design, the use strategy of MFB6 component is adjusted, and the combination of MFB9 and MR104 is used to replace the original bias voltage access path, realizing the delay optimization of the bias power supply access data transmission position. It should be understood that MFB6 and MFB9 are magnetic components with the same parameters, and the consistency of their inductance values ensures the stability of the bias voltage transmission characteristics, and MR104 is a 0 ohm resistor connected between the power supply network line and the LD+ bias voltage access point, which forms a flexible low-impedance connection path.

[0056] Further, at the PCB layout level, the embodiment shortens the physical distance between the power supply network line labeled "N21117471" and the LD+ signal end of the laser package, and builds a bias voltage transmission path with controllable delay characteristics through the series connection of MFB9 and the cross-connection of MR104. It should be noted that the pad position of MFB6 is reserved but not soldered, which not only avoids the interference of the original path on the new design, but also provides a hardware foundation for possible circuit reuse in the future. The reserved pad of MC79 filter capacitor allows selective soldering of a capacitor element with appropriate capacitance value during debugging to adjust the time domain position of the bias voltage access according to the bias voltage response characteristics of different brands of lasers. This adjustment mechanism realizes fine calibration of the timing of the laser driver signal by changing the rising slope of the bias signal.

[0057] Further, the above hardware adjustment corrects the misalignment of the intersection point of the rising curve and the falling curve in the eye diagram envelope by changing the transmission delay of the bias voltage excitation signal. When the new path formed by MFB9 and MR104 increases the electrical length of signal transmission compared to the original design, the time of bias voltage reaching the LD+ signal end is delayed, so that the opening timing and closing timing of the laser are symmetrically optimized in the time domain. This timing adjustment is not simply a physical distance shortening, but based on signal integrity theory, the parasitic inductance and capacitance parameters of the transmission path are accurately calculated by electromagnetic simulation software to ensure that the delay is controlled within the nanosecond level of precision, thereby avoiding signal distortion caused by excessive timing offset.

[0058] In actual engineering applications, the circuit configuration of the embodiment can effectively adapt to laser modules of different process. For example, when the bias voltage response of a certain brand of laser has an inherent rising edge leading problem, a 10nF capacitor can be welded at the MC79 position to further delay the effective injection time of the bias voltage by using the charging and discharging characteristics of the capacitor, so that the rising edge is delayed by about 0.3ns in the eye diagram, and the time difference with the falling edge is reduced from the original 1.2ns to within 0.5ns. The flexibility of this debugging mechanism solves the problem that a single fixed circuit cannot adapt to the characteristics of various devices in the prior art, and improves the compatibility and engineering practicability of optical module design.

[0059] The benefit of the embodiment is that a bias voltage access scheme with dynamic timing adjustment capability is constructed by selective configuration of hardware elements and optimized design of layout paths. This scheme not only realizes low impedance and stability of bias signal transmission through the combination of MFB9 and MR104, but also provides debugging space for the adaptation of different devices through the reserved interface of MC79, solving the problem of limited margin caused by the misalignment of the intersection point of the rising curve and the falling curve in the eye diagram envelope from the circuit level, and providing a quantifiable technical means for improving the time domain symmetry of high-speed differential signals. Those skilled in the art should know that the selection of the above element parameters and the setting of the connection mode are based on the coupling relationship analysis of signal transmission delay and device response characteristics, to ensure that each technical feature forms an organic whole in solving the timing matching problem, and realizes substantial improvement over the prior art.

[0060] Embodiment Four: To solve the problem of timing deviation of excitation signal caused by impedance mismatch of bias voltage transmission path, the embodiment further refines the hardware connection structure between the power supply network line and the LD+ bias voltage access point. In circuit design, the function of the power supply network line is to provide stable DC bias voltage for the laser, and its potential accuracy needs to be controlled within ±1% to avoid the influence of bias fluctuation on signal quality. MR104 is a 0 ohm resistor connected between the power supply network line and the LD+ bias voltage access point. Although its physical form is a short circuit, it actually has the characteristics of low parasitic inductance in high-frequency signal transmission, which can effectively reduce the impedance of the bias voltage transmission path and ensure that the excitation signal reaches the laser drive end with minimal loss.

[0061] Further, MFB9 and MFB6 are magnetic elements with the same parameters, and the consistency of the inductance value is the key to maintaining the stability of the bias voltage. It needs to be understood that in the original design, the presence of MFB6 may introduce additional signal delay, and in the embodiment, the position of MFB6 is not inserted, only the series setting of MFB9 is reserved, so that the inductance parameter of the bias voltage transmission path is closer to the driving requirements of the laser. The adjustment of this hardware layout is essentially an active optimization of the time domain characteristics of the bias voltage excitation signal—by reducing unnecessary element insertion, shortening the effective path of signal transmission, and using the low impedance characteristics of MR104 to form a direct bias voltage supply channel, thereby achieving precise control of the excitation signal introduction timing.

[0062] Further, in the PCB wiring process, the embodiment requires that the width of the power supply network line and the LD+ bias voltage access point be not less than 50 mil to reduce the voltage drop caused by the direct current resistance, and a ground protection belt is provided on both sides of the wiring to suppress the coupling effect of external electromagnetic interference on the bias signal. The welding position of MR104 needs to be close to the pin of the laser package to ensure that the time domain delay of the bias voltage is controlled within 0.1 ns, which is verified by signal integrity simulation software, which can improve the time symmetry of the rising edge and falling edge in the eye diagram by more than 15%. In addition, the installation direction of MFB9 needs to be parallel to the reference layer in the PCB layer structure to reduce the additional impact of its own parasitic parameters on the signal timing.

[0063] Further, the synergistic effect of the above hardware design and layout rules solves the timing distortion problem of the bias voltage excitation signal caused by the impedance discontinuity of the transmission path in the prior art. When the laser driver circuit generates high-speed differential signals, stable and timing-accurate bias voltage can ensure that the threshold current operating point of the laser remains stable, avoiding the phenomenon of rising edge leading or lagging caused by bias delay. In laboratory tests, the optical module sample using the embodiment reduces the cross-point deviation of the rising edge and falling edge of the eye diagram from the original 80ps to 30ps at a rate of 25Gbps, and the effective width of the signal decision window increases by 22%, verifying the actual effect of the scheme on time domain symmetry optimization.

[0064] The embodiment has the benefit that by specifying the electrical performance indicators of the power supply network line, the low impedance connection characteristics of the MR104, and the parameter consistency design of the MFB9, a bias voltage supply system with stability and accuracy is constructed. The system not only ensures the stable output of the laser bias voltage, but also realizes the controllable adjustment of the time domain delay of the excitation signal through the fine adjustment of the hardware layout, providing an engineering implementation path for solving the time symmetry problem of the rising edge and falling edge in the eye diagram. Those skilled in the art can understand that the combination of the above technical features is not a simple element replacement, but an impedance matching and timing optimization of each link on the bias voltage transmission link based on high-speed circuit design theory, thereby forming a complete signal quality improvement scheme.

[0065] Embodiment five: To solve the problem of differential signal parasitic parameter mismatch caused by the discontinuity of the PCB reference layer in the prior art, the embodiment further optimizes the reference layer design and impedance control method of the LD+ / LD- differential signal line. In the PCB layout stage, the complete design of the reference layer is defined as: the inner layer under the differential signal line transmission path is provided with a continuous and unbroken metal plane as a signal return path, the copper foil coverage of the plane needs to reach more than 95%, and the thickness tolerance of the insulating medium of the adjacent layer is controlled within ±5% to ensure the stability of the electromagnetic coupling characteristics of the differential signal.

[0066] Further, in the impedance control process, the embodiment adopts a joint simulation method to cooperatively optimize the wiring gap, width and reference layer parameters of the differential signal line. Specifically, first, a PCB layer structure model is established by an electromagnetic simulation software such as HFSS, the dielectric constant, copper foil thickness and other parameters of the medium layer are input, and the differential impedance theoretical value when the wiring gap is 5.75 mil and the width is 10 mil is calculated. Subsequently, by adjusting the integrity of the reference layer such as avoiding the plane cutting caused by the dense distribution of vias in the key area, the change trend of the impedance simulation result is observed, and until the differential impedance is stabilized within 60 ohms. This joint simulation not only verifies the rationality of the wiring parameters, but also ensures the electromagnetic compatibility of the reference layer on the entire transmission path.

[0067] It needs to be understood that the fracture of the reference layer will cause the differential signal return path to detour, thereby introducing additional parasitic inductance and capacitance, causing phase distortion and amplitude attenuation in the signal transmission process. The embodiment specifies the split forbidden zone of the reference layer in the PCB design rules, such as prohibiting the arrangement of power vias or non-related signal traces directly below the differential signal line, and adopts a full-plane copper cladding process to eliminate the potential risk of discontinuity of the reference layer from a physical level. At the same time, a fixed dielectric thickness is provided between the differential signal line and the reference layer, and the uniform electric field distribution characteristics are used to further reduce the influence of parasitic parameters on signal transmission.

[0068] Further, in the signal integrity test, the optimized reference layer design and impedance control scheme show significant effect: the "eyelid" area width of the eye diagram envelope is reduced from the original 150 mV to 80 mV, indicating that the signal noise margin is effectively improved; at the same time, the signal edge overshoot phenomenon caused by parasitic parameters is suppressed to within 30 mV, the original peak value is 120 mV, reducing the risk of misjudgment in signal judgment. This optimization is not only dependent on single parameter adjustment, but through the multi-dimensional coordination of wiring geometric parameters, layer structure and reference layer integrity, the systematic improvement of differential signal transmission characteristics is realized.

[0069] The benefit of the embodiment is that by establishing strict reference layer design specifications and joint simulation verification mechanism, the impedance matching failure problem caused by the extensive PCB layout in the prior art is solved. The scheme not only clearly defines the quantitative relationship between the differential signal line wiring gap, width and reference layer parameters, but also ensures the landing of design intention through engineering process control means, providing a replicable technical solution for low-loss transmission of high-speed differential signals on PCB. Those skilled in the art should know that the cooperative optimization of reference layer integrity and impedance control is the core technical link to solve the signal quality problem of 25G SPON optical modules, and the realization of its technical effect depends on the deep application of electromagnetic theory and the accumulation of engineering practice experience.

[0070] Embodiment six: to realize the systematic optimization of high-speed differential signal transmission quality, the embodiment provides a circuit structure suitable for the foregoing method, as shown in Figure 9 The circuit integrates impedance matching and bias voltage timing adjustment in the same hardware platform through the cooperative design of functional modules. The circuit as a whole includes a laser driver circuit, an impedance matching circuit and a bias voltage adjustment circuit, and the electrical connection and parameter configuration of each module comply with the electromagnetic compatibility principle of high-speed circuit design.

[0071] Specifically, the laser driver circuit as a signal source, its function is to convert digital signals into LD+ / LD- differential signals conforming to the 25G SPON standard. The circuit uses an integrated drive chip, whose output swing is set to 800 mVpp, and the rise and fall time is controlled within 15 ps to meet the timing requirements of high-speed transmission. The differential signal output end of the drive chip is directly connected to the input end of the impedance matching circuit, and the connection wire length between the two is controlled within 200 mil to reduce signal attenuation caused by too long wire length.

[0072] Further, the LD+ / LD- differential signal line included in the impedance matching circuit is laid out on the PCB according to the parameters of 5.75 mil wiring gap and 10 mil wiring width, and the inner layer continuous metal plane is used as the reflow path to ensure that the differential impedance is stable at 60 ohms with an accuracy of ±10 ohms. It should be understood that the setting of this impedance parameter is not an empirical value, but is calculated by matching the output impedance of the driving chip and the input impedance of the laser, aiming to reduce signal reflection through gradual impedance transition. The output end of the differential signal line is connected to the gold finger pad of the optical module, and an impedance compensation section with a length of 50 mil is arranged between the two to further optimize the transmission continuity of the signal at the module boundary.

[0073] Further, the bias voltage adjustment circuit is connected to the LD+ signal end of the laser driving circuit, and the structure thereof includes an MFB9 with the same parameters as the MFB6, a 0-ohm resistor MR104, and a reserved MC79 filter capacitor. The MFB9 is connected in series in the bias voltage transmission path, and uses its inductive characteristic to suppress high-frequency noise and ensure the stability of the direct current component of the bias voltage; the MR104 is connected across the 3.3V power supply network line marked as "N21117471" and the LD+ signal end to form a low-impedance direct connection channel, and the soldering mode uses a surface-mounted package (0402 size) to reduce parasitic inductance; the pads of the MC79 filter capacitor are reserved for 1206 package positions, allowing a capacitor element with a capacitance in the range of 1nF to 100nF to be soldered to adapt to the bias voltage filtering needs of different lasers.

[0074] During the operation of the circuit, the differential signal generated by the laser driving circuit is first transmitted through the impedance matching circuit to optimize the transmission parameters and reduce signal reflection and crosstalk caused by impedance mismatch; at the same time, the bias voltage adjustment circuit delays the access timing of the bias voltage through the combination of MFB9 and MR104, so that the opening timing of the laser is accurately matched with the rising edge of the driving signal. As a result of this hardware cooperative design, the time domain symmetry of the rising curve and the falling curve in the eye diagram envelope is significantly improved, and the noise margin of the signal decision window is increased from the original 25% to more than 32%.

[0075] The benefit of the present embodiment is that by specifying the specific structure, element parameters and connection relationship of each functional circuit, the abstract method claim is converted into an engineering-realizable hardware scheme. The circuit not only solves the impedance matching problem in differential signal transmission, but also provides a hardware foundation for timing optimization of the laser driving signal through the modular design of the bias voltage adjustment circuit, thereby forming a complete quality improvement system from signal generation to output. As can be understood by those skilled in the art, the model selection and parameter configuration of each element in the circuit, such as the amplitude setting of the driving chip and the package specification of the filter capacitor, are based on actual engineering verification to ensure the feasibility and reliability of the technical solution.

[0076] Embodiment Seven: To further clarify the connection details and layout rules of each module of the circuit, this embodiment carries out physical level detailed design on the circuit structure described above. In the PCB layout, the input end of the LD+ / LD- differential signal line is directly soldered to the BGA package pin of the laser driver chip, and the output end corresponds to the 12th and 13th pads of the optical module gold finger. The pad spacing is geometrically consistent with the 5.75mil wiring gap of the differential signal line, ensuring the continuity of signal transmission at the module boundary. The wiring direction of the differential signal line follows the principle of "away from high-speed clock lines and power lines", and the reference layer below is the second layer inner layer GND plane of the PCB. This plane is connected to the surface layer ground pad through a via array to form a complete signal return path.

[0077] Further, regarding the layout optimization of the bias voltage adjustment circuit, this embodiment explicitly reserves the pad position of MFB6 but does not install components, instead setting the soldering position of MFB9 and MR104 within a range of 50mil from the laser package pin. MR104, as a 0 ohm resistor, has its two ends connected to the power supply network line labeled "N21117471" and the LD+ signal end respectively. The wiring width of this connection path is set to 30mil to reduce the DC resistance, and the wiring length is controlled within 100mil to reduce signal transmission delay. The inductance value of MFB9 is consistent with that of MFB6, and its installation direction is perpendicular to the direction of the differential signal line to avoid magnetic field coupling interference on high-speed signals.

[0078] Further, the design of the power supply network line "N21117471" follows the power integrity principle. Its input end is connected to the module power supply filtering circuit (not shown in the figure), and its output end is directly loaded to the LD+ pin of the laser through MR104, forming an independent bias voltage supply channel. The network line uses copper plating treatment in the inner layer of the PCB, with a copper foil thickness of 2oz, ensuring that it can carry a bias current of more than 200mA without significant voltage drop. The reserved pad of the MC79 filter capacitor is connected in parallel with the LD+ signal end, and its pad position is adjacent to the laser package, facilitating the quick soldering of capacitive elements of different capacitance values during debugging to adjust the high-frequency filtering characteristics of the bias voltage.

[0079] It needs to be understood that the wiring of the differential signal line with reference to the left chip BGA pad parameters is essentially following the "source matching" principle, making the impedance characteristics of the output end of the driver chip well connected with the PCB wiring parameters. The reference layer serves as an inner layer signal return plane, and its integrity is ensured by prohibiting the placement of unrelated vias in this area, thereby suppressing the generation of common mode noise. In signal testing, this layout design improves the common mode rejection ratio (CMRR) of the differential signal to more than 40dB, significantly better than the 30dB index of traditional layout schemes.

[0080] The benefit of the embodiment is that by specifying the physical location, connection parameters and layout rules of each element of the circuit, the engineering conversion problem between "theoretical parameters" and "actual implementation" in hardware design is solved. From the differential signal path from the drive chip to the gold finger, to the bias voltage channel from the power supply network to the laser pin, each layout detail is verified by electromagnetic simulation and signal integrity test to ensure that the transmission characteristics of high-speed signals on the PCB meet the design expectations. Those skilled in the art should know that such detailed layout design is the key to solving the consistency problem of signal quality in mass production of optical modules, and the realization of its technical effect depends on the comprehensive application of PCB manufacturing process, element parasitic parameters and signal transmission theory.

[0081] Embodiment eight: In order to improve the anti-interference ability of the circuit system, the embodiment adds a power filter module and a ground protection trace on the basis of the circuit in claim 6, and constructs a multi-level electromagnetic compatibility design scheme. The power filter module is connected in parallel to the power input end of the laser driver circuit, and includes multiple decoupling capacitors with different capacitance values - 100nF ceramic capacitors for filtering out gigahertz-level high-frequency noise, 10μF electrolytic capacitors for suppressing low-frequency power supply ripple, and 1μF tantalum capacitors for providing transient current compensation. These capacitors are arranged in a star layout, and their ground ends are directly connected to the main ground layer of the PCB, ensuring efficient filtering of power supply noise.

[0082] Further, a ground protection trace is arranged around the LD+ / LD- differential signal line, the width of the trace is 20 mil, and the spacing between the differential signal line and the trace is maintained to be more than 15 mil, so as to avoid electromagnetic coupling caused by too close traces. The protection trace is connected to the inner ground plane through an array of vias, forming a shielding structure around the differential signal, effectively reducing the influence of external electromagnetic interference such as clock signal and power device switching noise on the differential signal. It should be understood that the ground protection trace is not simply a copper foil ring, and its design should follow the principle of "equipotential connection" to ensure the potential consistency of the entire shielding structure and avoid forming a new electromagnetic radiation source.

[0083] Further, the synergistic effect of the power filter module and the ground protection trace improves the anti-interference ability of the circuit from two dimensions of the power supply end and the signal transmission end. At the power input end, the combination of multiple filter capacitors can suppress the power supply noise peak-to-peak value to within 50mV, which is much lower than the tolerance requirement (100mV) of the laser driver circuit for power supply ripple; at the signal transmission path, the joint shielding of the ground protection trace and the reference layer reduces the crosstalk noise amplitude of the differential signal from the original 80mV to below 30mV, significantly improving the purity of the signal.

[0084] Further, in the PCB layer structure design, the embodiment adopts a 6-layer board layout: the first layer is a signal layer (differential signal line and bias voltage trace), the second layer is a ground reference layer, the third layer is a power supply layer, the fourth layer is an inner signal layer, the fifth layer is an auxiliary ground layer, and the sixth layer is a gold finger welding layer. This layering method sets the power supply layer and the ground layer adjacent to each other, uses the flat plate capacitance effect to improve the power integrity, and at the same time provides a stable reference plane for the differential signal. The dielectric thickness between the layers is strictly controlled, such as 5 mil from the first layer to the second layer, and 4 mil from the second layer to the third layer, to ensure the consistency of impedance control parameters.

[0085] The benefit of the embodiment is that, by introducing the electromagnetic compatibility design of power filtering and ground protection, the problem of being easily disturbed by external noise in high-speed signal transmission is solved. This scheme not only improves the stability of the circuit system, but also forms a synergistic effect with the impedance matching circuit - pure power input and low-noise transmission environment, which further improves the eye diagram margin of the differential signal by 3%-5%, providing technical support for the reliable operation of the optical module in a complex electromagnetic environment. Those skilled in the art can understand that this multi-level anti-interference design is a necessary link in the engineering of high-speed optical modules, and the combination of its technical features is not a simple additional measure, but a systematic optimization based on electromagnetic compatibility theory.

[0086] Embodiment Nine: To realize the whole-process quality improvement from signal processing to production control, the embodiment provides a 25G symmetric passive optical network transmission quality improvement system, which integrates the system architecture of the foregoing circuit. This system combines hardware optimization and process control through modular design to form a complete 25G SPON transmission quality improvement scheme. The system as a whole includes a signal processing module, an impedance control module, a layout optimization module, and a production control module, and the modules interact with each other through standardized interfaces and function synergistically.

[0087] Specifically, the signal processing module is the input end of the system, and its function is to generate a 25G symmetric passive optical network differential signal that meets the ITU-T G.9807.1 standard. This module integrates a high-speed digital signal processor (DSP) and a digital-to-analog converter (DAC), and can generate a high-precision LD+ / LD- differential signal according to the input digital data stream. The signal amplitude, rise time, and other parameters can be configured through software to adapt to the driving needs of different lasers. The generated differential signal is first transmitted to the impedance control module for physical layer optimization.

[0088] Further, the impedance control module integrates an impedance matching circuit, which functions to control the impedance of the LD+ / LD- differential signal line to 60 ohms. The module includes an electromagnetic simulation submodule and a parameter configuration submodule: the former calculates the transmission characteristics of the differential signal by importing PCB layering parameters and wiring geometry data, and outputs optimized wiring gap, width, and reference layer parameters; the latter converts the simulation results into PCB design rules to ensure consistency in parameter implementation at the production end. During signal transmission, the impedance control module monitors the signal reflection coefficient (such as the S11 parameter) in real time, and triggers a warning mechanism when the reflection amplitude exceeds -15 dB, prompting adjustment of the wiring parameters.

[0089] Further, the layout optimization module corresponds to the aforementioned bias voltage adjustment circuit, and functions to achieve timing optimization by adjusting the LD+ bias voltage access position. The module includes a layout rule library and a component parameter database: the layout rule library defines the soldering position and connection method of MFB9, MR104, and MC79; the component parameter database stores recommended values of filter capacitors corresponding to different brands of lasers, such as recommending MC79 as 22nF for a Japanese laser and 47nF for an American laser, supporting automatic matching of optimal parameters through a human-computer interaction interface during the debugging stage to realize intelligent adjustment of the bias voltage access timing.

[0090] Further, the production control module serves as the system output end, and functions to control the process of the optimized PCB. The module includes an impedance detection submodule and a size measurement submodule: the former detects the differential impedance of the finished PCB through a network analyzer to ensure that the impedance accuracy of each batch of products is maintained within ±10 ohms; the latter uses an automatic optical inspection (AOI) device to check the wiring gap, width, and reference layer integrity, and controls the production deviation within 5%. The detection data is fed back to the impedance control module and the layout optimization module in real time, forming a closed-loop control of design-production-detection.

[0091] In the system workflow, the differential signal generated by the signal processing module is impedance matched by the impedance control module, and then the bias voltage timing is adjusted by the layout optimization module, and finally output to the optical module for signal emission. The production control module runs through the entire design and manufacturing process to ensure that the hardware implementation is highly consistent with the design intent. This whole-process system architecture allows the signal eye diagram margin of the optical module to be predicted through simulation in the research and development stage, and to ensure consistency through process control in the production stage, fundamentally solving the engineering problem of "excellent performance of the prototype but fluctuating quality in mass production" in the prior art.

[0092] The benefit of the embodiment is that by constructing a complete system including signal processing, impedance control, layout optimization and production control, a single hardware improvement is elevated to the technical height of full-process quality control. The function definition and interaction mechanism of each module not only retains the flexibility of hardware design such as supporting parameter adaptation of different lasers, but also ensures the repeatability of the technical solution through quantitative control of the production end, providing a systematic solution for the mass production of 25G SPON optical modules. Those skilled in the art should know that this system-level design thinking is the key to solving the engineering problems of high-speed optical communication devices, and the realization of its technical effect depends on the efficient collaboration between modules and the deep understanding of manufacturing processes.

[0093] Embodiment ten: to realize the software and intelligence of the foregoing method, the embodiment provides a storage medium in which a computer program is stored, which can be executed by a processor to realize a 25G symmetric passive optical network transmission quality improvement method. The storage medium includes but is not limited to a solid state disk (SSD), an optical disk, a U disk and other non-volatile storage devices, and the program code stored therein contains an instruction set for executing the following steps:

[0094] Further, the program instructions direct the processor to perform PCB layout optimization of the LD+ / LD- differential signal lines in the transmission link. Specifically, by calling the built-in PCB design rule library, the wiring gap of the differential signal lines is automatically set to 5.75 mil, the wiring width is set to 10 mil, and a reference layer integrity check script is generated to ensure the continuity of the reference plane on the transmission path. This process can be connected with the API of electromagnetic simulation software to automatically import medium layer parameters such as dielectric constant and copper foil thickness for impedance precalculation, and generate a preliminary layout scheme.

[0095] Further, the program instructions contain an impedance control algorithm for optimizing the impedance control accuracy of the differential signal lines from the original 30 ohms to 60 ohms. Based on the microstrip line impedance calculation formula, the algorithm combines PCB process parameters such as substrate thickness tolerance and etching factor to dynamically adjust the wiring geometry parameters and generate process control files to clearly define the key parameters that need to be controlled by the production end, such as medium layer thickness and copper foil roughness. When the processor executes the instructions, it can simultaneously call historical production data for machine learning to continuously optimize the impedance control model and improve the prediction accuracy.

[0096] Further, regarding the adjustment of the bias voltage access position, the program instruction contains element configuration logic: in the PCB layout stage, the MFB6 position is automatically identified and marked as "not on the piece", while the welding position of MFB9 and MR104 is generated near the laser package, and the MC79 filter capacitor pad is reserved. This logic supports the intelligent adaptation of hardware configuration by automatically calculating the inductance value of MFB9 and the recommended capacitance value of MC79 according to the input laser model by scanning the device barcode to retrieve the corresponding bias voltage timing parameters from the database.

[0097] During the program execution process, each step instruction does not run in isolation, but realizes information sharing through data interface: the layout optimization result is fed back to the impedance control algorithm for secondary verification, and the measured data in the process control file is fed back to the layout rule library for iterative optimization, forming a closed-loop software system of "design-simulation-production-feedback". This system can run on mainstream EDA design platforms such as Cadence Allegro and Altium Designer, and can be embedded in the existing design process through plug-in form to improve the work efficiency of engineers.

[0098] The benefit of the embodiment is that by converting the method claim into an executable computer program, the automation and intelligentization of high-speed optical module design are realized. The algorithm and rule library contained in the storage medium not only solidifies the optimization scheme in the prior art, but also supports future technology iteration through data-driven way, providing a standardized design tool for R&D personnel. Those skilled in the art can understand that this software implementation method and the hardware scheme form a complement, which not only ensures the standardization of the design process, but also leaves room for future technical improvement.

[0099] Although the present application has been described above with reference to the preferred embodiments, it is to be understood that the application is not limited to the embodiments described above, but that various modifications and changes can be made without departing from the spirit of the application, and such modifications and changes are to be included within the scope of the appended claims and their equivalents.

Claims

1. A method for improving transmission quality in a 25 GHz symmetrical passive optical network, characterized in that, The steps of the method include: PCB routing layout optimization is performed on the LD+ / LD- differential signal lines in the transmission link, the routing gap, the routing width and the reference layer area integrity of the LD+ / LD- differential signal lines are adjusted, the impedance control of the differential signal lines is realized, the consistency difference in PCB production is improved, and the loss and interference in the signal transmission process are reduced; The impedance control precision of the LD+ / LD- differential signal lines is optimized from the original 30 ohms to 60 ohms, and the PCB process is controlled based on the impedance control precision, the eye diagram envelope line of the signal link test is refined, and the signal quality is improved; In the PCB layout, the LD+ bias voltage access position is adjusted to be closer to the laser, the MFB9 with the same value as the MFB6 is added, a 0-ohm resistor MR104 is connected to the power supply network line, the MC79 filter capacitor is reserved and the MFB6 position is reserved, and the introduction time of the LD+ bias voltage excitation signal is slowed down, so that the rising curve in the eye diagram envelope is delayed in the time domain.

2. The method for improving transmission quality of a 25-gigabit symmetric passive optical network according to claim 1, wherein, The routing gap of the LD+ / LD- differential signal lines is adjusted from the original gold finger pad gap of 11.49 mil to the BGA pad gap of 5.75 mil; the routing width of the LD+ / LD- differential signal lines is adjusted from the original gold finger pad of 20 mil to the BGA pad of 10 mil; and the impedance simulation result of the differential signal lines is 60.80 ohms, so as to match the impedance requirement of high-speed signal transmission and reduce signal reflection and distortion.

3. The method for improving transmission quality of a 25-gigabit symmetric passive optical network according to claim 1, wherein, The MFB6 is not added, the MFB9 and the MR104 are replaced, the bias power supply access position of the data transmission is later, the time domain position of the bias voltage access is adjusted, the eye diagram margin caused by the dislocation of the intersection point of the rising curve and the falling curve in the eye diagram envelope is increased, and the symmetry of the signal transmission is improved.

4. The method for improving transmission quality of a 25-gigabit symmetric passive optical network according to claim 1, wherein, The power supply network line provides stable bias voltage for the laser, the MR104 is connected between the power supply network line and the LD+ bias voltage access point as a short circuit line to form a low-impedance signal transmission path, the parameters of the MFB9 and the MFB6 are the same, the stability of the bias voltage is maintained, the time domain delay of the bias voltage excitation signal is realized through the adjustment of the hardware layout, the time symmetry of the rising edge and the falling edge in the eye diagram is optimized, and the signal decision window is expanded.

5. The method for improving transmission quality of a 25-gigabit symmetric passive optical network according to claim 1, wherein, The PCB routing layout optimization includes a reference layer of the LD+ / LD- differential signal lines to ensure that the reference plane of the differential signal lines on the transmission path is continuous and has no breakage, and the influence of the parasitic parameters on the signal transmission is reduced; in the impedance control process, the routing gap, the width and the reference layer parameters of the differential signal lines are jointly simulated to verify the optimized impedance matching effect, so as to narrow the eye skin area of the eye diagram envelope and improve the clarity of the signal eye diagram.

6. A 25 G symmetrical PON transmission quality improvement circuit for implementing the 25 G symmetrical PON transmission quality improvement method according to any one of claims 1 to 5, characterized in that, The circuit includes: A laser driver circuit for generating LD+ and LD- differential signals; An impedance matching circuit is connected with the laser driver circuit, and includes an LD+ / LD- differential signal line, a wiring gap of the differential signal line is 5.75 mil, a wiring width is 10 mil, and differential impedance control of the differential signal line is 60 ohms, with an accuracy of ±10 ohms, and a reference layer area of the differential signal line is complete without breakage, for optimizing transmission impedance of the differential signal and reducing signal loss; A bias voltage adjustment circuit is connected with an LD+ signal end of the laser driver circuit, and includes an MFB9 with the same value as the MFB6, a 0-ohm resistor MR104, and a reserved MC79 filter capacitor, the MR104 is connected in cross between a power supply network line and the LD+ signal end, the MFB9 is connected in series on a transmission path of the bias voltage, and the MC79 filter capacitor is connected in parallel between the LD+ signal end and the ground, for delaying an access timing of the LD+ bias voltage and optimizing eye diagram symmetry.

7. The 25 gigabit symmetric passive optical network transmission quality improvement circuit of claim 6, wherein, An input end of the LD+ / LD- differential signal line is connected with a differential signal output end of a laser driver chip, and an output end is connected to a gold finger pad of an optical module; the differential signal line is routed according to gap and width parameters of a reference BGA pad in a PCB layout, a reference layer is an inner layer signal reflow plane of the PCB, and is used for suppressing common mode noise; A position of the MFB6 is reserved without adding a component, and an access path is combined by the MFB9 and the MR104; the power supply network line provides a 3.3V direct current bias voltage for the laser, the MR104 is used as a shorting wire to reduce impedance of bias voltage transmission, and the MC79 filter capacitor is used for filtering high-frequency noise to ensure stability of the bias voltage.

8. The 25-gigabit symmetric passive optical network transmission quality improvement circuit of claim 6, wherein, A power filter module connected with the laser driver circuit is further included, the power filter module includes a plurality of decoupling capacitors connected in parallel to a power input end, for suppressing interference of power supply noise on laser drive signals; a ground protection wire is arranged around the LD+ / LD- differential signal line, the ground protection wire is connected with a ground layer of the PCB, for reducing influence of external electromagnetic interference on differential signal transmission, and improving signal transmission quality in cooperation with the impedance matching circuit.

9. A 25 G symmetrical passive optical network transmission quality improvement system integrated with the 25 G symmetrical passive optical network transmission quality improvement circuit according to any one of claims 6-8, characterized in that, The system comprises: a signal processing module, configured to generate and process differential signals of a 25 G symmetrical passive optical network (GPON); an impedance control module, integrated with an impedance matching circuit, configured to perform 60-ohm impedance control on an LD+ / LD- differential signal line, including adjusting a wiring gap, a width, and a reference layer integrity; a layout optimization module, integrated with a bias voltage adjustment circuit, configured to adjust an access position of an LD+ bias voltage and delay an introduction timing of a bias voltage excitation signal; a production control module, configured to perform process control on the optimized PCB, to ensure impedance parameters and wiring accuracy of the LD+ / LD- differential signal line; the differential signals generated by the signal processing module are subjected to impedance matching by the impedance control module, and are output to an optical module after adjustment of bias voltage timing by the layout optimization module, so as to improve an eye diagram margin and transmission quality.

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