High dynamic range imaging CMOS camera based on K7 gigabit network

Abstract

The invention discloses a high-dynamic-range imaging CMOS camera based on a K7 gigabit network. The high-dynamic-range imaging CMOS camera comprises a camera shell 9, and a high-dynamic-range imaging CMOS camera body is installed in the camera shell 9. The CMOS camera body comprises a CMOS sensor chip 1, an FPGA (Field Programmable Gate Array) programmable logic device 2, a DDR3 (Double Data Rate 3) high-speed memory 3, a FLASH memory chip 4, a gigabit Ethernet interface 5, a GPIO (General Purpose Input / Output) isolation interface 6 and a power supply module 7. The FPGA chip receives high-gain and low-gain 2048 * 2048 resolution image data from the CMOS sensor chip at the same time, data caching is carried out through the DDR3 high-speed memory, high-dynamic-range image synthesis is completed in real time, images with 46 frames per second (the resolution is 2048 * 2048) and the dynamic range reaching 70.3 dB are output through the gigabit Ethernet interface, and working parameters of the camera can be configured through a computer.

Description

Technical Field

[0001] This invention relates to the field of optical detection technology, and specifically to a K7 gigabit network-based high dynamic range imaging CMOS camera. Background Technology

[0002] Imaging technology is now developing not only towards higher resolution but also towards higher dynamic range (HDR). HDR imaging technology can provide richer dynamic information about a scene, but most current imaging devices acquire images with low dynamic range. To obtain HDR images, existing methods often involve taking multiple images of the same scene with different apertures and exposure times, and then using algorithms to process these multiple frames to obtain the HDR image. This method requires large-capacity image storage units and a long image acquisition and processing time.

[0003] Therefore, how to quickly and efficiently obtain high dynamic range images is an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a K7 gigabit network-based high dynamic range imaging CMOS camera that can directly output high dynamic range images.

[0005] The technical solution to achieve the purpose of this invention is as follows: a high dynamic range imaging CMOS camera body is installed inside the camera housing 9. The CMOS camera body includes a CMOS sensor chip 1, an FPGA programmable logic device 2, a DDR3 high-speed memory 3, a FLASH memory chip 4, a gigabit Ethernet interface 5, a GPIO isolation interface 6, and a power module 7. The FPGA chip simultaneously receives high-gain and low-gain 2048*2048 resolution image data from the CMOS sensor chip, caches the data through the DDR3 high-speed memory, completes high dynamic range image synthesis in real time, and outputs images at 46 frames / second (2048*2048 resolution) with a dynamic range of 70.3dB through the gigabit Ethernet interface. Furthermore, the camera's operating parameters can be configured via a computer.

[0006] The CMOS sensor chip (1) is Changchun Changguang Chenxin Optoelectronics GSENSE2020s.

[0007] The FPGA programmable logic device (2) is a Xilinx Kintex7 series XC7K160T-2FFG676.

[0008] The DDR3 high-speed memory (3) is Micron DDR3 MT41K256M16.

[0009] The FLASH storage chip (4) is ST EEPROM M95020.

[0010] The Gigabit Ethernet interface (5) is a MARVELL 88E1111.

[0011] The GPIO isolation interface (6) is MOCD207M.

[0012] The power module (7) converts the input DC 12V voltage into various DC voltages to power the camera system.

[0013] High dynamic range image processing is completed in real time on the FPGA programmable logic device (2) and output through the gigabit Ethernet interface (5). Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the internal structure of a high dynamic range imaging CMOS camera.

[0015] Figure 2 This is a schematic diagram of the housing of a high dynamic range imaging CMOS camera. Detailed Implementation

[0016] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description:

[0017] A high dynamic range imaging CMOS camera includes a camera housing 10, within which the high dynamic range imaging CMOS camera body is mounted. The CMOS camera body includes a CMOS sensor chip 1, an FPGA programmable logic device 2, a DDR3 high-speed memory 3, a FLASH memory chip 4, a Gigabit Ethernet interface 5, a GPIO isolation interface 6, and a power module 7.

[0018] The CMOS sensor chip (1) is Changchun Changguang Chenxin Optoelectronics GSENSE2020s.

[0019] The FPGA programmable logic device (2) is a Xilinx Kintex7 series XC7K160T-2FFG676.

[0020] The DDR3 high-speed memory (3) is Micron DDR3 MT41K256M16.

[0021] The FLASH storage chip (4) is ST EEPROM M95020.

[0022] The Gigabit Ethernet interface (5) is a MARVELL 88E1111.

[0023] The GPIO isolation interface (6) is MOCD207M.

[0024] The power module (7) converts the input DC 12V voltage into various DC voltages to power the camera system.

[0025] After the FPGA programmable logic device 2 powers on and initializes the CMOS sensor chip 1, it outputs control timing signals for the CMOS sensor chip 1. It reads high-gain and low-gain background noise signals from the CMOS sensor chip 1 and stores this signal data in the DDR3 high-speed memory 3. Then, it reads high-gain and low-gain image noise signals from the CMOS sensor chip 1, and simultaneously reads high-gain and low-gain background noise signals from the DDR3 high-speed memory 3. The image signal is obtained by subtracting the background noise signal from the image noise signal, and then a high dynamic range image processing algorithm is performed to obtain a high dynamic range image signal, which is output through the Gigabit Ethernet interface 5. The FPGA programmable logic device 2 outputs the exposure time signal for each frame of the image through the GPIO isolation interface 7. The host computer sends commands through the Gigabit Ethernet interface 5, the FPGA programmable logic device 2 receives the commands, completes the relevant command functions, and stores the configuration parameters in the FLASH memory chip 4. In external trigger mode, the FPGA programmable logic device 2 receives external trigger signals transmitted through the GPIO isolation interface 6, or trigger signals sent by the host computer to the FPGA programmable logic device 2 through the Gigabit Ethernet interface 5 and the GPIO isolation interface 6, to determine the trigger time of each frame of image.

[0026] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A high dynamic range imaging CMOS camera based on K7 gigabit network, comprising a camera housing 9, wherein a high dynamic range imaging CMOS camera body is installed inside the camera housing 9. The CMOS camera body comprises a CMOS sensor chip (1), an FPGA programmable logic device (2), a DDR3 high-speed memory (3), a FLASH memory chip (4), a gigabit Ethernet interface (5), a GPIO isolation interface (6), and a power module (7). The power module (7) provides stable power supply to the CMOS sensor chip (1), the FPGA programmable logic device (2), the DDR3 high-speed memory (3), the FLASH memory chip (4), and the gigabit Ethernet interface (5). The CMOS sensor chip (1) outputs differential image signals to the FPGA programmable logic device (2), the FPGA programmable logic device (2) stores the image signals in the DDR3 high-speed memory (3), and reads the stored image signals from the DDR3 high-speed memory (3) according to the corresponding timing relationship to perform high dynamic range image processing algorithms. The processed image data is output through the gigabit Ethernet interface (5). The host computer can send instructions via the Gigabit Ethernet interface (5), which are received and executed by the FPGA programmable logic device (2). The instructions include functions such as changing the display area, setting the frame rate, setting the exposure time, selecting the trigger mode and trigger signal, and saving and reading the working parameters. The FPGA programmable logic device (2) performs read and write operations on the FLASH memory chip (4) to meet the user's needs for saving and reading the working parameters. The FPGA programmable logic device (2) receives external trigger signals through the GPIO isolation interface (6) and outputs exposure time synchronization signals through the GPIO isolation interface (6).

2. The high dynamic range imaging CMOS camera based on K7 gigabit network according to claim 1, characterized in that: The CMOS sensor chip (1) is Changchun Changguang Chenxin Optoelectronics GSENSE2020s.

3. The high dynamic range imaging CMOS camera based on K7 gigabit network according to claim 1, characterized in that: The FPGA programmable logic device (2) is a Xilinx Kintex7 series XC7K160T-2FFG676.

4. A high dynamic range imaging CMOS camera based on K7 gigabit network according to claim 1, characterized in that: The DDR3 high-speed memory (3) is Micron DDR3 MT41K256M16.

5. A high dynamic range imaging CMOS camera based on K7 gigabit network according to claim 1, characterized in that: The FLASH storage chip (4) is ST EEPROM M95020.

6. A high dynamic range imaging CMOS camera based on K7 gigabit network according to claim 1, characterized in that: The gigabit Ethernet interface (5) is a MARVELL 88E1111.

7. A high dynamic range imaging CMOS camera based on K7 gigabit network according to claim 1, characterized in that: The GPIO isolation interface (6) is MOCD207M.

8. A high dynamic range imaging CMOS camera based on K7 gigabit network according to claim 1, characterized in that: The power module (7) converts the input DC 12V voltage into various DC voltages to power the camera system.

9. A high dynamic range imaging CMOS camera based on K7 gigabit network according to claim 1, characterized in that: High dynamic range image processing is completed in real time on the FPGA programmable logic device (2) and output through the gigabit Ethernet interface (5).

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