EEPROM reading device used for passive UHF RFID chip

Abstract

The invention discloses an EEPROM reading device used for a passive UHF RFID chip. The reading device is mainly used for solving problems in existing EEPROM reading devices of high peak and average power consumption, large process variation and floating-gate performance degradation. The reading device comprises: a reading controlling logic circuit, an edge self-detection circuit, a reading unit array, and a storing unit array. The storing unit array is connected to the reading unit array through bit lines (BL). Under the controlling of a reading clock signal CLKR, the reading controlling logic circuit generates a reset signal rst, a precharge signal enpch, and a latch signal enlat, and the signals are transmitted to the reading unit array. A data signals DBO is transmitted from the reading unit array to the edge self-detection circuit, and a controlling signal latch is generated. The signal is fed back to the reading controlling logic circuit. The reading device provided by the invention has advantages of low peak and average power consumption, process variation resistance and floating-gate performance degradation resistance.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and relates to an electrically erasable programmable read-only memory (EEPROM) of a semiconductor integrated circuit, in particular to an EEPROM reading device, which can be used for a passive UHF RFID tag chip circuit. Background technique [0002] With the continuous deepening of research on passive UHF RFID tag chips, many original technical problems have been overcome. However, EEPROM, which is the mainstream storage unit and memory of UHF RFID tag chips, is still difficult due to its special process and design complexity. Restricting the progress of passive UHF RFID, especially the EEPROM data reading device, has always been a bottleneck restricting the research and practical application of passive UHF RFID. [0003] A traditional EEPROM reading device is composed of a reading circuit and a storage cell array, wherein the storage cell array is used to store data to be saved, and the...

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Problems solved by technology

[0004] The traditional reading circuit generally adopts the method of current detection, which has a complex structure and generally requires a reference current Iref to distinguish the data signal stored in the floating gate of the memory unit. In order to ensure sufficient discrimination and anti-interference ability, the reference current generally Not less than 10μA, higher power consumption

At the same time, due to the process deviation of the floating gate of the memory cell, the degradation of the characteristics of the floating gate device, and the deviation of the reference current Iref, etc., the discrimination of the EEPROM reading circuit is reduced, or even completely invalid. This problem propose

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