5 results about "Large peak" patented technology

The application provides a signal peak-to-average ratio suppression method and system, an electronic device and a storage medium. The peak-to-average ratios of transmission sequences corresponding to two factor sequences before and after flipping of a phase rotation factor of each signal block are sequentially compared, the phase rotation factor with a smaller peak-to-average ratio of the signal block is determined, and the phase rotation factor with a larger peak-to-average ratio of the signal block is no longer considered in the comparison process of subsequent signal blocks. Thus, the number of peak-to-average ratio calculations and comparisons is reduced, and the calculation complexity and calculation time are greatly reduced while ensuring a certain peak-to-average ratio suppression effect.

To provide a peeling apparatus and a signal processing method capable of identifying the positional information of the butt joints of rod materials continuously supplied to the peeling apparatus. [Solution] From the source signal output from the peeling device, a main signal is obtained that includes a first peak caused by the butt joint of the bar passing through any part of the peeling device, a second peak caused by noise, and, if a processing abnormality occurs during processing of the bar, a third peak caused by the processing abnormality. Simultaneously, one or more sub-signals are obtained from the source signal to identify the first peak included in the main signal. Furthermore, an assumed boundary range in which the first peak is expected to appear is calculated based on the sub-signals, and the largest peak that appears within the assumed boundary range of the main signal is identified as the first peak.

The embodiment of the present application discloses a dead time control circuit and method. In a specific embodiment, the circuit comprises a feedback circuit for generating a first enable signal and a second enable signal when a modulation signal is high; wherein the first enable signal is low for controlling the lower tube to be closed; a floating ground circuit for outputting an upper tube gate control signal when the second enable signal is high; and an upper tube gate potential detection circuit for opening the upper tube when the upper tube gate control signal is low. The embodiment automatically adjusts the discharge delay time without any manual setting intervention, ensures that the upper and lower tubes are not connected, and the discharge delay is as small as possible, thereby preventing large peak current from burning the power tube and chip, ensuring the performance of the chip while improving the reliability of the chip.

The application discloses a ZP89 type frequency shift signal center frequency detection method, equipment and a storage medium, the method comprises the following steps: sampling the ZP89 type frequency shift signal by an undersampling method; performing FFT analysis on the sampling data; finding six peaks, i.e., left and right main peaks and corresponding left and right secondary peaks, on the spectrum obtained in step two; selecting the two largest peak values or four peak values according to the ratio of the left secondary peak amplitude of the left main peak or the right secondary peak amplitude of the right main peak to complete energy barycenter correction of a t point, and obtaining corrected peak values; calculating the undersampling center frequency according to the corrected peak values obtained in step three; and performing spectrum restoration on the calculation result of step four to obtain the ZP89 type frequency shift signal center frequency. The scheme improves the frequency resolution through energy barycenter correction, and further improves the calculation accuracy; and the combination of the two-peak method and the four-peak method solves the problem of large center frequency jumping that may occur in frequency domain analysis.

The invention relates to a parallel processor, an automatic frequency modulation method thereof and electronic equipment. The method comprises the following steps: predicting load information of a parallel processor when loading a calculation task, wherein the load information comprises a maximum load, a minimum load and an average load; according to the load information, the rated power consumption of the parallel processor and a preset power consumption model, predicting the maximum working frequency, the minimum working frequency and the average working frequency when the parallel processor runs the calculation task; the power consumption model is used for representing the relationship among the load, frequency and power consumption; and adjusting the frequency of the parallel processor to the average working frequency to start running, and dynamically adjusting the working frequency of the parallel processor within the maximum working frequency and the minimum working frequency according to the real-time power consumption of the parallel processor during running of the calculation task, so that the power consumption of the parallel processor is maintained at the rated power consumption. According to the invention, the problems of slow frequency rising and large peak current in the operation process of the existing parallel processor can be improved.