169 results about "Pwm modulator" patented technology

A class AD audio amplifier system (10) with reduced noise capability in muting and unmuting events is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which can be constructed to include a pulse-width-modulator (PWM) (24). The PWM modulator (24) includes a pair of comparators (39A, 39B; 52+, 52−) that generate complementary PWM output signals based upon the comparison between a filtered difference signal and a reference waveform. When the system is muted, a common mode voltage (CM_RAMP) is applied to the inputs of the comparators (39A, 39B; 52+ 52−) to suppress the duty cycle at the amplifier output, preferably to a zero duty cycle. In the transition from a muted state to an unmuted state, the common mode voltage (CM_RAMP) is ramped from the suppressing voltage to zero common mode voltage, permitting the duty cycle of the complementary PWM signals to gradually increase, thus reducing clicks and pops. The converse operation is performed in the transition from unmuted to muted. Pulse-width-modulation control logic (26) is also included to ensure that that the PWM “on” and “off” pulses are of at least a minimum duration, and also to generate compensating pulses on the complementary PWM line at low duty cycles.

A class AD audio amplifier system (10) with improved recovery from clipping events is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which can be constructed to include a pulse-width-modulator (PWM) (24). The PWM modulator (24) includes a pair of comparators (39A, 39B; 52+, 52−) that generate complementary PWM output signals based upon the comparison between a filtered difference signal and a reference waveform. Clip detection logic (26) is provided to detect clipping at the output of the channel (20), preferably by detecting successive edges of the reference waveform without an intervening edge of a PWM output signal. In response to detecting clipping, a first integrator (30; 45) is reset to remove residuals and to eliminate the first integrator (30; 45) from the loop filter of the modulator (24). A saturation level circuit (35) applies a clamping voltage, preferably in both clipping and non-clipping situations, to a second integrator (36; 47). As a result, the loop filter is prevented from entering extreme conditions during clipping, which greatly reduces the clipping recovery time.

A class AD audio amplifier system (10) with DC output detection logic (26) is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which includes a pulse-width-modulator (PWM) (24). The DC detection logic (26) includes a sigma-delta modulator (60) and a digital low-pass filter (62) that monitors the PWM output signals from the PWM modulators (24). The sigma-delta modulator (60) operates at a first clock frequency, while the low-pass filter (62) operates at a much lower clock frequency, so that AC audio components, PWM harmonics, and sigma-delta quantization error is suppressed from the DC detection. The modulated filtered signal is compared against a threshold level (THRSH) to determine whether the amplitude of a DC component at the PWM output is sufficiently high to constitute a fault. If so, a fault detection signal (DC_DET) is issued, and the PWM modulators (24) are disabled to prevent unsafe conditions in the system (10).

A power generation system comprises at least two electrical systems connected at an electrical connection point. Each electrical system comprises a power conversion system comprising a converter including a plurality of switches for converting direct current power into alternating current power. The power generation system comprises a control system including at least two pulse width modulation (PWM) modulators, each PWM modulator for obtaining a fundamental waveform and a carrier signal, using the fundamental and carrier signals to generate a PWM pattern, and for providing the PWM pattern to a respective converter for driving the switches of the respective converter. The control system is configured to interleave carrier signals, fundamental waveforms, or a combination of carrier signals and fundamental waveforms of the at least two electrical systems to generate interleaved PWM patterns respectively for the at least two converters.

A circuit for transitioning between a discontinuous and a fixed frequency continuous conduction mode (DCM) and (CCM) of a power converter having a driver receiving PWM signals and controlling a switching stage comprises a control switch and a sync switch connected at a common switching node for driving a load. The circuit including a PWM modulator for providing PWM signals; and a mode selector for receiving a duty cycle value, a preset switching period, and a duty cycle at a critical conduction point having a switching frequency equal to the preset switching period and providing an on-time of the control switch and a switching period to the PWM modulator, wherein if the duty cycle value is greater than the duty cycle at a critical conduction point, the PWM modulator will drive will provide the PWM signals to operate the switching stage in the CCM with constant-frequency duty cycle control, and if the duty cycle value is less than duty cycle at a critical conduction point, the PWM modulator will drive will provide the PWM signals to operate the switching stage in the DCM by turning off the sync switch when a load current becomes negative.

A modulation system and method having a high linearity. The system is a PWM modulator or a class D amplifier and includes an integrator, a low pass filter (LPF), a comparator, and an output circuit. The LPF is located before the comparator. Jitter noise produced by the comparator and/or switching noise of the output circuit are removed by feedback to the input. Thus, the linearity of the modulation system is provided.

A control circuit controls a switching power factor corrector based on switch off-time modulation by controlling the input electric charge during on-time. The circuit includes a charge current generator that generates charge current as a replica of a current sense signal amplified with a gain corresponding to the square of peak value of a rectified input voltage, a loop capacitor charged with the charge current during on-time intervals and discharged with a discharge current during off-time intervals, a discharge current generator that generates the discharge current proportional to a product of a comparison voltage and a difference between a regulated output voltage and the rectified input voltage, and a PWM modulator that senses a charge voltage of the loop capacitor, turns on the switch for an on-time duration in response to detecting that the charge voltage nullifies, and turns off the switch when the on-time duration has elapsed.

A control system is provided for an inverter assembly associated with an induction motor. The system includes a current determination module configured to generate q- and d-axis current commands based on a torque command. The current determination module is further configured to generate the q-axis current command based on an observed flux linkage and a flux linkage command. The system further includes a motor current control module coupled to the current determination module and configured to generate q- and d-axis voltage commands based on the q- and d-axis current commands generated by the current determination module and a PWM modulator coupled to the motor current control module configured to generate duty cycle signals for operating the inverter assembly based on the q- and d-axis voltage commands generated by the motor current control module.

A pulse width modulation (PWM) modulator for a multiphase power converter and related adaptive firing order (AFO) method includes a multiphase leading edge generator having pulse generating circuitry associated with each of the regulator phases, wherein the pulse generating circuitry generates phase pulses associated with each of the phases. An adaptive firing order (AFO) controller having circuitry including a mixer receives and sums the phase pulses into a summing signal and uses the summing signal to generate a series of turn-on pulses therefrom. A multiphase PWM generator has inputs coupled to an output of the AFO controller coupled to receive the series of turn-on pulses, the multiphase PWM generator having circuitry for generating said PWM signals therefrom. An adaptive firing order (AFO) controlled multi-phase power converter includes a plurality of parallel connected regulator phases controlled by respective pulse width modulation (PWM) signals provided by the PWM modulator.

Class-D amplifiers have evolved from using binary pulse-width modulation (PWM) modulators to three-level PWM modulators. Three-level PWM drivers for audio applications offer the benefits of eliminating costly elements at the output of an audio system. However, they also introduce increased common-mode interference. Three-level PWM generates three states, but one state has two interchangeable representations which can be scrambled in order to shape the common-mode output spectrum.

A PWM modulator according to an embodiment includes a first comparator configured to compare a first input signal with a first carrier and output a comparison result, a second comparator configured to compare a second input signal with a second carrier and output a comparison result, and a selector configured to output the comparison result while switching between the comparison result of the first comparator and the comparison result of the second comparator in a cycle according to a cycle of the first or the second carrier.

A pulse width modulation (PWM) controller includes a shutter circuit interposed between a PWM modulator and a driver circuit. The shutter circuit receives a raw PWM output signal from the PWM modulator and processes the raw PWM signal to eliminate double pulsing that may be present on the raw PWM signal. Bypass logic responsive to a switch or software controlled enable input is provided to permit the shutter circuit to be included in the PWM controller or alternatively, to be bypassed.

The invention relates to a method for inhibiting second harmonic current of a preceding-stage inverter of a two-stage inverter and a control circuit of the preceding-stage inverter of the two-stage inverter. By the method, the low-frequency pulse current of the preceding-stage direct current inverter can be inhibited obviously, the dynamic performance can be improved and the dynamic response speed is increased. The control circuit of the preceding-stage inverter consists of a band-pass filter, a voltage regulator, a summator, a power-width modulation (PWM) modulator and a driving circuit. The work principle is as follows: a voltage sampling circuit detects intermediate bus voltage, compares the intermediate bus voltage with a voltage reference signal to generate an error signal and transmits the error signal to the voltage regulator; a current sampling circuit detects the inductive current of the preceding-stage direct current inverter; the inductive current of the preceding-stage direct current inverter, an output signal of band-pass filter and an output signal of the voltage regulator are added by the summator to generate a modulation signal; the modulation signal is transmitted to a PWM modulation circuit; and a driving signal of a switch tube is acquired by the driving circuit, so that operation of the preceding-stage direct current inverter is controlled.

An electronic device (11) according to the present invention includes a semiconductor integrated circuit (16) on which a pulse conversion circuit (17) for converting an acoustic signal received by a radio receiver (13) into a pulse signal is integrated. The pulse conversion circuit (17) includes a clock generator (110) which generates plural clocks and selects word clocks (210,211) according to the reception frequency of the radio receiver (13), an FSC (111) which performs sampling frequency conversion so as to make a sample sequence of an A/D converted acoustic signal have the same frequency as that of the word clock (210), a noise shaper (112) for performing noise shaping to the sample sequence outputted from the FSC (111) using the word clock (211), and a PWM modulator (113) for generating a pulse signal from the output of the noise shaper (112) using the word clock (211). Therefore, it is possible to avoid radio reception interference which may caused by the pulse signal when driving a speaker with the pulse signal.

The invention discloses a power supply system of an IGBT (Insulated Gate Bipolar Transistor) drive module. The power supply system comprises a PWM (Pulse-Width Modulation) modulator, a power switch tube and an inverter transformer, wherein a first initial end tap (T1) of a secondary first coil (B1) is connected with an anode of a first rectification diode (D1); a cathode of the first rectification diode (D1) is connected with one end of a first energy-storage capacitor (C1); the other end of the first energy-storage capacitor (C1) is connected with a first tail end tap (T3); a first middle tap (T2) is connected with a cathode of a second rectification diode (D2); an anode of the second rectification diode (D2) is connected with one end of a second energy-storage capacitor (C2); the other end of the second energy-storage capacitor (C2) is connected with the first tail end tap (T3); and the layout of a rectification and energy-storage capacitor of a secondary second coil (B2) is symmetrical with that of the secondary first coil (B1). According to the power supply system, positive and negative output voltages are mutually isolated in an inverting way, and do not interfere mutually, so that the problem of unbalance of magnetic flow of a transformer is solved, the aim of balance of magnetic flow is achieved, the stability of the power supply system of the IGBT drive module is ensured, and the interior demand of an electric automobile is met.

A switching audio amplifier circuit drives a switching audio amplifier stage using a digital PWM signal from an audio source. A PWM duty ratio modifier modifies an edge timing of the digital PWM signal to produce a modified digital PWM signal. A mode switch switches between the digital PWM signal and the modified digital PWM signal in a way that masks audible noise such as clicks and pops at power-up and power-down of the switching audio amplifier. An integrating error amplifier compares a difference between the digital PWM signal and an amplified PWM signal and integrates the difference to control the edge timing modified by the PWM duty ratio modifier. A mode controller can apply an offset signal to the integrating error amplifier and can control the switching of the mode switch.