10 results about "Word clock" patented technology

An application processor is provided. The application processor includes: a phase locked loop circuit (PLL); a sleep control logic circuit configured to control the PLL to enter and exit a sleep mode; a wake-up generation logic circuit configured to provide a wake-up request signal to the sleep control logic circuit to control the PLL to exit the sleep mode based on an early wake-up signal; an always-on video timer circuit configured to output a synchronization signal to a display driving chip in a sleep mode section and generate the early wake-up signal; a display video timer circuit configured to receive the synchronization signal from the always-on video timer and indicate the sleep control logic to provide an idle section; and clock switching logic circuit configured to alternately provide, as an operation clock of the sleep control logic, one of an always-on clock and a word clock.

1. The name of this design product: Stereo Word Clock (G2424S). 2. Purpose of this design product: It has the function of displaying time and decoration. 3. The key design point of this design product lies in the combination of shape and pattern. 4. The picture or photo that best illustrates the key points of the design: Main view of Design 1. 5. Designate Design 1 as the base design.

The present invention provides a phase adjustment circuit for a divided-frequency clock, comprising: a phase control word generation circuit for generating a set of control words based on a reference clock and a divided-frequency clock to be adjusted; and a clock adjustment circuit, connected to the phase control word generation circuit, for adjusting the phase of the divided-frequency clock based on the control words to obtain a divided-frequency synchronous clock synchronized with the reference clock. The present invention can rapidly adjust the clock phase in real time, using half-cycles of the system clock as steps, without losing the clock sampling edge, and is applicable to integrated circuits requiring high sampling accuracy.

An application processor is provided. The application processor includes a phase-locked loop (PLL) circuit, a sleep control logic circuit configured to control the PLL to enter and exit a sleep mode, and a wake-up generation logic circuit configured to provide a wake-up request signal to the sleep control logic circuit to control the PLL to exit the sleep mode based on an early wake-up signal, the normally-open video timer circuit is configured to output a synchronizing signal to a display driving chip in a sleep mode section and generate the early wake-up signal; a display video timer circuit configured to receive the synchronization signal from the normally-on video timer and instruct the sleep control logic to provide an idle section; and a clock switching logic circuit configured to alternately provide one of a normally-on clock and a word clock as an operating clock of the sleep control logic.

A method for detecting a timing error of a Digital-to-Analog-Converter (DAC). The DAC comprises: a digital control circuit configured to encode a digital input word into an encoded word, each bit of the encoded word having a corresponding bit weight, and further configured to encode each encoded word to a control word by mapping the bits of the encoded word to bits of the control word; clocked buffers comprising a first pair of clocked buffers and configured to sample the bits of the control word; analog weights, each weight associated with one of the bits in the control word; and summation circuitry configured to generate an analog sample by summing the sampled bits of the control word weighted by the respective associated analog weights. The method comprises: generating (901), a first pair of bits of the control word by periodically swapping a pair of mappings of bits of a first pair of bits of the encoded word having the same bit weight such that an error signal proportional to a timing error between a first clocked buffer and a second clocked buffer of the first pair of clocked buffers is generated; and detecting (902) the error signal.

A digital clock data recovery device for recovering a clock and data in a data signal includes a phase difference compensation unit configured to selectively output an upper bit value and a lower bit value of a phase difference value between a first input signal and a second input signal according to a condition based on a range of the phase difference value, a digital loop filter configured to receive an output of the phase difference compensation unit; and a digital controlled oscillator configured to transfer a feedback signal to the phase difference compensation unit based on an output value of the digital loop filter.

The invention relates to the field of digital audio equipment, provides a multi-clock-source low-jitter burr-free switching audio clock management device, and aims to solve the problems that multi-clock switching generates shock-wave lock falling and forced resampling loses tone quality. The device comprises a multi-channel clock source module, a clock selection and gating module and an audio processing unit. The clock selection and gating module comprises a burr-free multiplexer and an interlocking logic unit, and ensures that only one path of clock is enabled and output at any moment; the device physically monitors the audio word clock frequency through the independent external microcontroller, and outputs a hardware trigger signal, thereby realizing clock source autonomous interlocking switching without a main control chip, and controlling the audio processing unit to realize bypass straight-through transmission. The method is suitable for high-fidelity audio equipment such as a Bluetooth receiver and the like.

The application provides a satellite broadcast audio clock synchronization method, device, medium and product, relates to the technical field of digital clock synchronization, and the method comprises the steps of extracting a PCR time stamp from a satellite TS stream and decoding PCM audio data; calculating the difference between the PCR time stamp and a local numerical control oscillator counter as a time error value; inputting the time error value into a PI controller for proportional integral operation, and performing smoothing processing on the output of the PI controller through an IIR low-pass filter to obtain a frequency adjustment amount; writing the frequency adjustment amount into the local numerical control oscillator to adjust the frequency, so that the restored PCR clock signal is obtained through convergence; phase-locked frequency division of the restored PCR clock signal to generate an audio output clock signal, and synchronization output of the PCM audio data is realized based on the audio output clock signal. The problem that loud noise and broken noise are prone to occurring during master-backup switching due to large clock restoration jitter when the existing satellite broadcast receiving device operates independently without external synchronization source is solved.

The invention relates to a digital clock data recovery device. A digital clock data recovery device according to one embodiment of the present disclosure is a digital clock data recovery device that recovers a clock and data from a data signal, and may include: a phase difference compensation section that compensates a phase difference value in accordance with a condition in accordance with a range of the phase difference value; selectively outputting a high-order value and a low-order value in phase difference values of the first input signal and the second input signal; a digital loop filter to which the output of the phase difference compensation unit is input; and a digitally controlled oscillator that transmits a feedback signal to the phase difference compensation unit on the basis of the output value of the digital loop filter.

An application processor is provided. The application processor includes: a phase locked loop circuit (PLL); a sleep control logic circuit configured to control the PLL to enter and exit a sleep mode; a wake-up generation logic circuit configured to provide a wake-up request signal to the sleep control logic circuit to control the PLL to exit the sleep mode based on an early wake-up signal; an always-on video timer circuit configured to output a synchronization signal to a display driving chip in a sleep mode section and generate the early wake-up signal; a display video timer circuit configured to receive the synchronization signal from the always-on video timer and indicate the sleep control logic to provide an idle section; and clock switching logic circuit configured to alternately provide, as an operation clock of the sleep control logic, one of an always-on clock and a word clock.