Fractional frequency all-digital phase-locked loop and control method thereof

Abstract

The invention provides a fractional frequency all-digital phase-locked loop and a control method thereof. The method comprises the following steps: S1, a fractional frequency controller generates a delay control word, a frequency division ratio control word, an integer frequency control word and a fractional frequency control word according to an external fractional frequency control word; s2, theclock generation and control circuit generates a clock signal ckr according to the reference clock and the frequency control word; s3, the digital time converter generates a low-frequency clock signal according to the ckr and the delay control word; s4, the feedback signal generation circuit outputs a feedback signal fb according to the frequency division ratio control word and a high-frequency clock signal ckv generated by the numerical control oscillator; s5, the phase discriminator generates phase error digital signals phe of ckr and fb; s6, the auxiliary frequency locking loop outputs a control signal ft1 according to the integer frequency control word, the fractional frequency control word and the low-frequency clock signal, and the numerical control oscillator updates ckv accordingto the sum of ft1 and phe.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a fractional frequency all-digital phase-locked loop and a control method thereof. Background technique [0002] The all-digital phase-locked loop uses digital circuits to realize loop control, so it has a high degree of design and implementation flexibility, is easy to integrate with other on-chip systems, and can achieve better performance with the development of integrated circuit manufacturing processes, so it has a very wide range of applications. application. However, in the fractional frequency all-digital phase-locked loop of the traditional structure, due to the existence of fractional quantization errors, the phase error range between the clock signals input by the phase detector is very large, which affects the design complexity of the time-to-digital converter and the power consumption. and error control requirements are very high. In order to redu...

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Problems solved by technology

The larger output delay time range puts forward higher requirements on the design difficulty, power consumption, area, linearity and noise of the digital-to-time converter, which limits the energy efficiency and performance of the phase-locked loop

[0004] In order to alleviate the design requirements of the digital-to-time converter in the output delay time range, circuit designers usually have to adopt compromise methods, such as using low-order modulators, or even not using modulators, sacrificing fractional spurious performance; using resolution A digital-time converter with a higher rate, in order to obtain a wider range of output delay time, sacrifices linearity, causing serious fractional spurious problems; adding jitter (dither) to the output of a digital-time converter with poor linearity, will Fractional spurs at specific frequencies are converted to noise distributed over the entire frequency spectrum, deteriorating PLL noise performance

Recently, some researchers have used the falling edge of the clock to reduce the required digital-to-time converter output delay time range, but this method requires the clock signal to strictly meet the 50% duty cycle, so precise duty cycle correction is required circuit, which increases the complexity and power consumption of the design, and the loops that work simultaneously in the phase-locked loop may introduce additional phase noise or errors, resulting in unstable loop operation

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