Serial communication device and method for removing data clock skew therein

Abstract

A serial communication device and a method of removing data clock skew therein are provided. The device comprises an MIPI D-PHY physical layer, and the physical layer comprises a clock receiving device which is used for receiving an analog clock signal from a first channel of a serial link of the MIPI D-PHY physical layer and processing the analog clock signal to obtain a digital initial clock signal; each data receiving device receives an analog data signal from a second channel of the serial link of the MIPI D-PHY physical layer, obtains an initial clock signal from the clock receiving device, and outputs a digital data signal and a corresponding word clock signal after processing; and the synchronous processing device is used for respectively determining starting points of respective effective data from the plurality of received data signals and correcting phase deviation between each effective data and a first word clock signal according to the starting points, and the first word clock signal is selected from a plurality of word clock signals output by the plurality of data receiving devices. The device aligns data signals in all data channels to a specific clock signal.

Description

technical field [0001] The present application relates to the technical field related to MIPI D-PHY, in particular to a serial communication device and a method for removing data clock skew in the serial communication device. Background technique [0002] MIPI (Mobile Industry Processor Interface) is not only an alliance, but also the name of a group of interface protocol specifications. It has different working groups to meet the different needs of each subsystem of the mobile terminal. Different working groups are responsible for formulating specific protocols and defining a set of internal interface standards for mobile devices with different hardware devices, such as Camera Serial Interface (CSI), Display Serial Interface (DSI), Radio Frequency Interface (DigRF), etc. D-PHY is one of the MIPI protocols. MIPI D-PHY provides a specification for serialized signaling at the physical layer. [0003] The MIPI D-PHY protocol defines two transmission modes: High Speed ​​Mode ...

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Problems solved by technology

Therefore, in the discontinuous mode, the signal transmission will switch between the low power mode and the high speed mode within the parameter range stipulated in the protocol, but the analog clock signal will produce a glitch when switching from the low power mode to the high speed mode. , each of the four data transmission channels receives a clock signal containing different glitches, processes the data signal it transmits accordingly, and outputs the processed data signal and the processed clock signal (word_clk), thus resulting in the processed There is a skew between the data signal and the clock signal between the four data transmission channels (skew)

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