15 results about "Serial computer" patented technology

The application discloses a kind of control host computer and robot control system.The control host computer includes: mainboard and extension board, the mainboard and the extension board are connected by high-speed serial computer expansion bus standard PCIE extension interface;The extension board integrates AUTBUS module;The control host computer communicates with the node board of robot foot by the AUTBUS module.The above technical solution expands AUTBUS module for control host computer, and the control host computer can control robot using AUTBUS, improves uplink and downlink bandwidth, and improves data transmission efficiency.

The application provides a network card, a bandwidth performance test method and device of a PCIE link and a medium, and belongs to the technical field of computers, wherein the network card comprises a bandwidth loop device, one end of the bandwidth loop device is connected with a sending engine of the network card, and the other end of the bandwidth loop device is connected with a receiving engine of the network card; and the bandwidth loop device is used for, in the case of being enabled, breaking through the internal loop of the network card to form a high-speed serial computer expansion bus standard PCIE bandwidth loop. The bandwidth loop device is arranged in the network card, the bandwidth loop device is enabled, and the internal loop of the network card is broken through, so that the high-speed serial computer expansion bus standard PCIE bandwidth loop is formed in a single network card, and then the bandwidth performance test of the PCIE link can be realized based on the single network card, and external equipment or a jig is no longer needed, and the test efficiency can be improved.

The utility model relates to a wireless communication module and a wireless communication system. The wireless communication module comprises a baseband chip, an M.2 connector and a power management unit, the baseband chip comprises a multiplexing function module and an interface type selection pin; wherein the multiplexing function module is used for selecting a level state input by a pin according to the interface type to transmit a high-speed serial computer expansion bus standard PCIe signal or a serial gigabit media independent interface SGMII signal; the M.2 connector comprises an M.2 interface and a selection circuit; the M.2 interface is connected with the multiplexing function module, one end of the selection circuit is connected with the interface type selection pin, and a high level or a low level is output to the interface type selection pin through the connection state of the other end of the selection circuit. Therefore, the wireless communication module is compatible with the SGMII interface besides supporting the PCIe interface defined by the original specification, and the compatibility and the product competitiveness of the wireless communication module are improved.

The embodiment of the application discloses a data transmission method and device, equipment and a storage medium, the method is applied to a first system on chip, the first system on chip and a second system on chip are connected through a high-speed serial computer expansion bus standard (PCIe bus), and the method comprises the following steps: obtaining target channel corresponding to to-be-transmitted data, wherein the target channel is one of PCIe channels between the first system on chip and the second system on chip, the target channel is configured with corresponding channel resources, the channel resources comprise shared memory resources and direct memory access (DMA) resources; and sending the to-be-transmitted data to the second system on chip through target channel resources of the target channel, wherein the target channel resources are one of the shared memory resources and the DMA resources, the target channel resources are matched with target information corresponding to the to-be-transmitted data, and the target information comprises a service type or a data length. The efficiency of cross-system on chip data transmission based on the PCIe bus can be improved.

The present disclosure relates to a method for determining the bit error rate of an optical module during data transmission, applied to an optical module based on high-speed serial computer expansion bus technology, comprising: initializing the high-speed serial computer expansion bus port of the computing processing unit and detecting the hardware connection state; in the case of completing initialization and normal connection state, resetting the error counter associated with the optical module; sending a control instruction by the central processor to control the computing processing unit or sending a predetermined data packet by the central processor and correspondingly acquiring the error count by the central processor or the computing processing unit; and calculating the bit error rate based on the error count and the predetermined data packet. The method accurately determines the error count of the error counter by means of the high-speed serial computer expansion bus technology data transmission interface, so as to accurately calculate the bit error rate based on the error count and the predetermined data packet, and realize accurate analysis of the transmission performance of the corresponding optical module.

This invention relates to the field of computer technology, specifically disclosing a computing system and its control method, apparatus, device, medium, and switch. A first switch utilizes a high-speed serial computer expansion bus to interconnect accelerator cards located on multiple servers. The first switch obtains the local device address of each accelerator card on the server, configures an address mapping table for each server based on the local device address of each accelerator card, and forwards data between accelerator cards on different servers according to the address mapping table. This effectively solves the problems of limited computing power in a single server and insufficient bandwidth and high latency in interconnecting multiple servers via Ethernet. It realizes cross-server vertical expansion based on a high-speed serial computer expansion bus, improves the bandwidth of cross-server communication, reduces the latency of cross-server communication, and lays the foundation for realizing high-bandwidth domain communication computing clusters with multiple machines and multiple cards.

The present disclosure provides a server resource allocation system, method and device, relates to the field of computers, in particular to the field of cloud computing. The specific implementation scheme is: a terminal is installed with a device BMC (baseboard management controller), a device resource allocation system and a PCIE (high-speed serial computer expansion bus) device set, wherein the device BMC is configured to receive a PCIE resource request of a user and forward the PCIE resource request to the device resource allocation system, the device resource allocation system is configured to select a target PCIE device from the PCIE device set according to the PCIE resource request and allocate the target PCIE device to the user, and the device BMC is configured to send a server restart request for loading the target PCIE device to a server; the server is configured to receive a server restart request sent by the device BMC and load the PCIE device indicated in the server restart request. The implementation can simplify the server elasticity scaling process and improve reliability.

This application discloses an in-vehicle domain controller, electrical equipment, data communication method, and computer-readable storage medium. The in-vehicle domain controller includes a field-programmable gate array (FPGA), a first system-on-a-chip (SoC), and at least one second SoC, each SoC being electrically connected to the FPGA. The first SoC is configured to establish a first high-speed serial computer expansion bus standard link with the FPGA. The second SoC is configured to establish a second high-speed serial computer expansion bus standard link with the FPGA if the first high-speed serial computer expansion bus standard link fails to be established. Thus, by switching to the second high-speed serial computer expansion bus standard link in the event of a failure in establishing the first high-speed serial computer expansion bus standard link, uninterrupted data transmission and stable operation of vehicle functions can be ensured.

This invention discloses a high-speed serial computer extended bus standard terminal device and its clock distribution circuit, belonging to the field of integrated circuit design. When the level conversion circuit receives a "dual-port enable signal from the host", it can control the multiplexer to work in dual-port mode, thereby leading the two reference clocks of the host to the first physical medium sublayer and the second physical medium sublayer respectively. When the dual-port enable signal is not received, it can control the multiplexer to work in single-port mode, so that the reference clock provided by the host through the first output terminal can be synchronously output through the two output terminals of the multiplexer, thereby keeping the two reference clocks synchronized and not affecting the collaborative work of the two physical medium sublayers. Moreover, the forwarding processing performed by the multiplexer does not affect the reference clock quality. In addition, the host can accurately control the working mode of the PCIe terminal device through the dual-port enable signal.

This disclosure provides a storage device and an electronic device. The storage device includes a carrier for carrying and conducting electronic components, a conversion chip disposed on the carrier, and a storage module. The storage device can be detachably connected to an electronic device. The carrier is provided with a first connection interface, through which the storage device can establish a first communication connection with the electronic device. A second communication connection is established between the storage module and the conversion chip. The conversion chip is used to convert first protocol data obtained from the first communication connection into second protocol data and transmit the second protocol data to the storage module through the second communication connection. The storage module can respond to the second protocol data by performing corresponding target read operations and / or target write operations. The first communication connection is a high-speed serial computer expansion bus standard PCIe connection, and the second communication connection is a general-purpose flash memory storage (UFS) connection.

The application provides a data packet processing method, device, equipment, medium and computer program product, the method comprising: generating a first framework driver corresponding to an input / output framework and a second framework driver corresponding to a data plane development kit; adapting a structure of the data plane development kit to the input / output framework, loading the first framework driver and the second framework driver; in the case that a network card hardware interface is a peripheral component interconnect standard interface or a high-speed serial computer expansion bus standard interface, processing a data packet according to the second framework driver; in the case that the network card hardware interface is not the peripheral component interconnect standard interface and the high-speed serial computer expansion bus standard interface, processing a data packet according to the first framework driver, which reduces the maintenance work in the later stage.

The application discloses a data processing method and device, equipment and medium, and relates to the technical field of storage. The method comprises the following steps: a current data page acquisition command is sent to a bottom chip, and a target data page carrying a first check value returned by the bottom chip based on the current data page acquisition command is acquired; wherein the bottom chip is an expander of a high-speed serial computer expansion bus standard; a second check value corresponding to the received target data page is generated; if the first check value is inconsistent with the second check value, the target data page is determined as an abnormal frame, and when the number of recorded abnormal frames reaches a preset threshold, a corresponding abnormal alarm is generated, a control command is sent to the bottom chip to control a target uplink port corresponding to the abnormal frame in the bottom chip to be closed. When the bottom chip is an expander of a high-speed serial computer expansion bus standard, the abnormal frame can be accurately identified and corresponding abnormal processing can be performed, so that the reliability of the storage system is ensured.

The invention discloses a Bluetooth keyboard and mouse management method, device and equipment and a medium, and relates to the technical field of keyboard and mouse management.The Bluetooth keyboard and mouse management method comprises the steps that the start-stop state of a Bluetooth keyboard and mouse is determined according to target data of a current server, and if the Bluetooth keyboard and mouse are started, the current server and the Bluetooth keyboard and mouse are connected through a high-speed serial computer expansion bus standard channel; judging whether the current server is successfully connected with the Bluetooth keyboard and mouse or not according to the target information; the target information comprises a media access control address, an internet protocol address of the server and a job number of a current operation and maintenance worker; after the connection is successful, interacting with the current server through a Bluetooth keyboard and mouse, if a connection switching request exists, determining a to-be-connected server according to a predetermined priority of each server, determining the to-be-connected server as a new current server, and sending the new current server to the Bluetooth keyboard and mouse; and skipping to the step of determining the start-stop state of the Bluetooth keyboard and mouse according to the target data of the current server until a preset cycle ending condition is met. And collaborative management of the Bluetooth keyboard and mouse is realized.

This application discloses communication methods, systems, devices, and electronic devices. One specific embodiment of the method includes: in response to determining the existence of data to be transmitted, calling a target interface to move the data to be transmitted to a target storage area, wherein the target storage area is a pre-allocated storage area on the Double Rate Synchronous Dynamic Random Access Memory of a target accelerator card, the target accelerator card is a high-speed serial computer expansion bus standard accelerator card, the data to be transmitted is data sent to the protocol stack of the Transmission Control Protocol or Internet Protocol by a target application calling a socket interface function, and the target interface is used to implement communication between the protocol stack and the target accelerator card; calling the target interface to send a notification to a data receiving device, wherein the notification is used to indicate that the data to be transmitted has been placed in the target storage area. This embodiment can form an IP network between the host and all PCIe accelerator cards, realizing communication between the host and the PCIe accelerator cards.

The invention relates to a password card data processing method and device, computer equipment, a storage medium and a computer program product. The method comprises the following steps: establishing high-speed serial computer expansion bus standard link connection with a field-programmable gate array chip, configuring a base address register of the field-programmable gate array chip, initializing a direct memory access engine of the field-programmable gate array chip, carrying out initialization setting on a scheduling acceleration module of an anti-quantum algorithm system on the field programmable gate array chip; constructing a descriptor table, wherein the descriptor table is configured to cooperate with the scheduling acceleration module to execute the operation of the anti-quantum algorithm system; the descriptor table is analyzed through the scheduling acceleration module, the anti-quantum algorithm system is called to execute calculation, and a calculation result is output to a target address. By adopting the method, the security and flexibility of the password card can be improved, and a traditional algorithm and an anti-quantum algorithm are compatibly supported.