47 results about "Serial computer" patented technology

The present application relates to the technical field of data processing, and discloses a data processing method and apparatus, a device, and a medium. The method comprises: on the basis of a bus address space allocated for a first slave device, writing data to be processed into a storage component of the first slave device by means of a first peripheral component interconnect express link, so that the first slave device processes said data to obtain result data; obtaining the result data sent by the first slave device; and determining a destination address of the result data, and if the destination address points to a storage space of a second slave device, writing the result data into a storage component of the second slave device by means of a second peripheral component interconnect express link. The problems of high communication delay and high hardware resource overhead during data transmission exist in the prior art. The present application can reduce cross-node communication delay and hardware resource overhead.

The present application relates to the technical field of computers, and provides a computing device, a server, a data processing method, and a storage medium. The computing device comprises a central processing unit (CPU), an accelerator, and a first high-speed serial computer extension bus standard PCIe switch; the accelerator is connected to a first downlink port of the first PCIe switch; an uplink port of the first PCIe switch is connected to the CPU; each port of the first PCIe switch supports a compute express link (CXL) protocol; the accelerator is configured to perform an access operation on a main memory on the basis of the CXL protocol.

The present application relates to the technical field of signal transmission. Disclosed are a method and apparatus for establishing a peripheral component interconnect express (PCIe) optical interconnection link, and a device, a non-volatile readable storage medium and a system. The method comprises: acquiring an upstream data signal which is transmitted by means of an electrical path, and detecting whether there is an electrical idle ordered set in the upstream data signal (S11); if there is an electrical idle ordered set, recording the current link rate, and by means of counting the electrical idle ordered set, determining whether the current sending of the electrical idle ordered set has been completed (S12); and when the current sending of the electrical idle ordered set has been completed, generating a target signal sequence of a corresponding rate according to the link rate, and sending the target signal sequence to an opposite end by means of a PCIe optical interconnection link, such that the opposite end maintains stable operation on the basis of the target signal sequence (S13). A PCIe optical interconnection link can be established, and the success rate of establishing the PCIe optical interconnection link can be increased, thereby avoiding the problem of a link establishment failure caused by an electrical idle state during link establishment.

The invention discloses a sending end equalization parameter testing method, device and equipment for a high-speed serial computer expansion bus and a medium, relates to the technical field of computers, and is applied to a target device. The target device comprises a first loop constructed based on an uplink port and a downlink port and a second loop constructed based on an acquisition component and an analysis component. The method comprises the following steps: configuring a current sending end equalization parameter in the uplink port or the downlink port; performing error code check according to the signal sent by the downlink port and the received signal; if the verification is passed, a signal sent by a downlink port is collected through a collection assembly; a target voltage is calculated according to an acquired signal through an analysis component, a de-emphasis parameter and a pre-emphasis parameter are calculated according to the target voltage, and a target sending end equalization parameter determined based on the de-emphasis parameter and the pre-emphasis parameter is compared with a current sending end equalization parameter. Therefore, the test cost is reduced and the test period is shortened.

The invention relates to the technical field of network transmission, and discloses a bandwidth adjustment method and device, equipment, a medium and a product. The method is applied to a high-speed serial computer expansion bus standard system, and comprises the following steps: acquiring a real-time data volume of a target port in a target link; determining a target channel number corresponding to the target port according to the real-time data volume of the target port; if the target channel number of the target port is different from the enabling channel number, generating a channel adjustment instruction according to the target channel number and the enabling channel number; and issuing a channel adjustment instruction to the target port to adjust the number of enabled channels of the target port. According to the invention, the delay in the link bandwidth switching process can be reduced.

Examples relate to apparatuses, devices, methods, and computer programs for root complexes (RCs) and / or endpoints (EPs) for PCIe (High Speed Serial Computer Extension Bus) systems, to PCIe systems, and to gateway devices including PCIe systems. In one embodiment, a device configured for an RC of a PCIe system includes a memory and one or more processors configured to generate a PCIe VDM (Vendor Definition Message) message for an EP of the PCIe system.

The invention provides a data transmission system, method and device, the data transmission system comprises a photoelectric hybrid cable, a high-speed serial computer extension PCIe host and PCIe equipment, the photoelectric hybrid cable comprises an optical cable part and a cable part, and the optical cable part is used for transmitting a first data signal between the PCIe host and the PCIe equipment; the first data signal comprises an optical signal corresponding to a high-speed data signal of the PCIe bus; the cable part is used for transmitting a second data signal between the PCIe host and the PCIe equipment; the second data signal comprises an electric signal corresponding to the low-speed signal of the PCIe bus. Thus, the data transmission system can transmit high-speed data signals based on the optical cable part and directly transmit low-speed signals based on the cable part, rapid transmission of PCIe data information can be ensured, the low-speed signals do not need to be specially processed, and the transmission cost and the transmission time delay are reduced.

The invention discloses an equipment firmware management method, equipment, a storage medium and a product, and relates to the technical field of firmware management, and the method comprises the steps: determining a main firmware partition corresponding to a target operation mode of bus switch equipment; the main firmware partition is a main firmware partition in preset main and standby firmware partitions; the bus switch equipment is switch equipment of a high-speed serial computer expansion bus; loading the current firmware stored in the main firmware partition, and starting the bus switch equipment to enter a target operation mode; and after entering the target operation mode, if the version information of the current firmware is inconsistent with the version information of the firmware stored in the standby firmware partition, synchronizing the current firmware to the standby firmware partition to complete the firmware management process. In this way, after the device enters the operation mode through the device firmware stored in the main firmware partition, the device firmware of the main firmware partition is synchronized to the standby firmware partition, normal starting is guaranteed, partition firmware synchronization is achieved, and the firmware management efficiency is improved.

The application discloses a kind of control host computer and robot control system.The control host computer includes: mainboard and extension board, the mainboard and the extension board are connected by high-speed serial computer expansion bus standard PCIE extension interface;The extension board integrates AUTBUS module;The control host computer communicates with the node board of robot foot by the AUTBUS module.The above technical solution expands AUTBUS module for control host computer, and the control host computer can control robot using AUTBUS, improves uplink and downlink bandwidth, and improves data transmission efficiency.

The application provides a network card, a bandwidth performance test method and device of a PCIE link and a medium, and belongs to the technical field of computers, wherein the network card comprises a bandwidth loop device, one end of the bandwidth loop device is connected with a sending engine of the network card, and the other end of the bandwidth loop device is connected with a receiving engine of the network card; and the bandwidth loop device is used for, in the case of being enabled, breaking through the internal loop of the network card to form a high-speed serial computer expansion bus standard PCIE bandwidth loop. The bandwidth loop device is arranged in the network card, the bandwidth loop device is enabled, and the internal loop of the network card is broken through, so that the high-speed serial computer expansion bus standard PCIE bandwidth loop is formed in a single network card, and then the bandwidth performance test of the PCIE link can be realized based on the single network card, and external equipment or a jig is no longer needed, and the test efficiency can be improved.

The invention relates to a test fixture, method and device, computer equipment and a storage medium. The test fixture comprises a BMC (Baseboard Management Controller) and an oscilloscope; the BMC is used for outputting an enable signal according to a control operation received by the client, the control operation is used for indicating the type of a signal to be tested, the enable signal is used for controlling and inputting a clock signal of a high-speed serial computer expansion bus standard PCIe device to be tested, and the control operation is used for indicating the type of the signal to be tested. The clock signal input into the PCIe device can trigger the PCIe device to output a PCIe signal; the oscilloscope is connected with the output end of the PCIe device and used for obtaining the waveform of the PCIe signal output by the PCIe device and sending the waveform to the client side, and the waveform is used for determining the test result of the PCIe device. By adopting the test fixture, the remote test of the PCIe equipment can be realized.

The invention provides a bridging module, an interaction method and related equipment. The bridging module is used for bridging PCIe terminal equipment and a high-speed serial computer expansion bus and comprises a converter, a first AXI host and a first AXI slave; the converter is in communication connection with the first AXI host and the first AXI slave, and the converter is also used for being in communication connection with PCIe terminal equipment; the converter is used for converting the PCIe data into the AXI data or converting the AXI data into the PCIe data; the first AXI host is also used for being in communication connection with a second AXI slave of an AXI bridge carried by a high-speed serial computer expansion bus; the first AXI slave machine is further used for being in communication connection with a second AXI host machine of an AXI bridge of the high-speed serial computer expansion bus. According to the converter, the communication protocol format of interaction data can be converted, and then interaction between PCIe terminal equipment and a high-speed serial computer expansion bus carrying an AXI bridge can be achieved through AXI channels of the first AXI host and the second AXI host.

The invention provides an RAID card hard disk control system, method and device based on an expansion capability set and a medium, relates to the technical field of computers and is applied to an RAID card chip, and the RAID card chip is in communication connection with a host and a plurality of under-hanging hard disks based on a high-speed serial computer expansion bus standard PCIe protocol. The system comprises a BAR (Base Address Register) access control module and an expansion capability set, wherein the expansion capability set comprises a downlink control region and an uplink control region. And the BAR access control module is responsible for acquiring hard disk configuration information issued by the host from the downlink control area, and performing operations such as reading, writing or polling stopping on a specified to-be-configured space of the lower-mounted hard disk according to the hard disk configuration information. And after the operation is completed, a result is fed back to the uplink control area for the host to read. According to the technical scheme, the problems that host software and RAID card firmware are large in development environment difference and complex in transplantation are solved, the problem that a hard disk control function is redeveloped in an RAID card is avoided, and restrictions on firmware development and function extension are relieved.

The invention provides a high-speed serial computer expansion bus standard backboard which is characterized in that multiple layers of circuit boards are arranged, a plurality of through silicon vias are formed in the multiple layers of circuit boards, the multiple layers of circuit boards are vertically and electrically connected through the through silicon vias to form a three-dimensional topological structure, and the three-dimensional topological structure comprises a first circuit board layer, a second circuit board layer and a third circuit board layer; the first circuit board layer is provided with a plurality of expansion card slots, the second circuit board layer is used for transmitting and processing serial signals, the third circuit board layer is used for providing a power supply, the multi-layer circuit board is further provided with a chip stacking module and a chip mounting part which are electrically connected with the multi-layer circuit board, and the chip mounting part is used for mounting the chip stacking module. According to the multi-layer circuit board, vertical electric connection of all the circuit board layers of the multi-layer circuit board is achieved through the silicon through holes, the transmission path of serial signals is greatly shortened, delay and attenuation of the serial signals are reduced, and stable and high-speed circulation of the high-speed serial signals is powerfully guaranteed.

The utility model relates to a wireless communication module and a wireless communication system. The wireless communication module comprises a baseband chip, an M.2 connector and a power management unit, the baseband chip comprises a multiplexing function module and an interface type selection pin; wherein the multiplexing function module is used for selecting a level state input by a pin according to the interface type to transmit a high-speed serial computer expansion bus standard PCIe signal or a serial gigabit media independent interface SGMII signal; the M.2 connector comprises an M.2 interface and a selection circuit; the M.2 interface is connected with the multiplexing function module, one end of the selection circuit is connected with the interface type selection pin, and a high level or a low level is output to the interface type selection pin through the connection state of the other end of the selection circuit. Therefore, the wireless communication module is compatible with the SGMII interface besides supporting the PCIe interface defined by the original specification, and the compatibility and the product competitiveness of the wireless communication module are improved.

The embodiment of the present application provides a monitoring system, method, server and product, belonging to the technical field of servers, wherein the monitoring system is applied to a baseboard management controller in a server, and the monitoring system includes a first monitoring subsystem that monitors the monitoring data of components in a first host based on a connection channel of a serial communication bus; a second monitoring subsystem that monitors the monitoring data of components in a second host based on a connection channel of a high-speed serial computer expansion bus; a monitoring switching subsystem that switches the monitoring host of the first monitoring subsystem and the second monitoring subsystem in response to a monitoring switching instruction, and when responding to the monitoring switching instruction, the baseboard management controller disconnects the connection channel based on the high-speed serial computer expansion bus with the second host, and establishes a connection channel based on the high-speed serial computer expansion bus with the first host. The embodiment of the present application aims to improve the efficiency of component monitoring in a dual-HOST-single BMC system.

The invention provides a data encryption transmission chip and method, and relates to the technical field of data transmission, the data encryption transmission chip comprises a high-speed serial computer expansion bus standard PCIE interface module, a data encryption and decryption module, a data transmission module and a medium-dependent interface MDI interface module, the PCIE interface module is respectively connected with a processor and the data encryption and decryption module, and the data encryption and decryption module is connected with the processor. The data transmission module is respectively connected with the data encryption and decryption module and the MDI interface module, and the MDI interface module is connected with network equipment. Data transmission between the PCIE and the Ethernet is realized through the modules in the data encryption transmission chip, so that the hardware cost is reduced by integrating the modules on a hardware chip, and meanwhile, high performance and high security of data transmission are ensured.

The embodiment of the application discloses a data transmission method and device, equipment and a storage medium, the method is applied to a first system on chip, the first system on chip and a second system on chip are connected through a high-speed serial computer expansion bus standard (PCIe bus), and the method comprises the following steps: obtaining target channel corresponding to to-be-transmitted data, wherein the target channel is one of PCIe channels between the first system on chip and the second system on chip, the target channel is configured with corresponding channel resources, the channel resources comprise shared memory resources and direct memory access (DMA) resources; and sending the to-be-transmitted data to the second system on chip through target channel resources of the target channel, wherein the target channel resources are one of the shared memory resources and the DMA resources, the target channel resources are matched with target information corresponding to the to-be-transmitted data, and the target information comprises a service type or a data length. The efficiency of cross-system on chip data transmission based on the PCIe bus can be improved.

The present disclosure relates to a method for determining the bit error rate of an optical module during data transmission, applied to an optical module based on high-speed serial computer expansion bus technology, comprising: initializing the high-speed serial computer expansion bus port of the computing processing unit and detecting the hardware connection state; in the case of completing initialization and normal connection state, resetting the error counter associated with the optical module; sending a control instruction by the central processor to control the computing processing unit or sending a predetermined data packet by the central processor and correspondingly acquiring the error count by the central processor or the computing processing unit; and calculating the bit error rate based on the error count and the predetermined data packet. The method accurately determines the error count of the error counter by means of the high-speed serial computer expansion bus technology data transmission interface, so as to accurately calculate the bit error rate based on the error count and the predetermined data packet, and realize accurate analysis of the transmission performance of the corresponding optical module.

This invention relates to the field of computer technology, specifically disclosing a computing system and its control method, apparatus, device, medium, and switch. A first switch utilizes a high-speed serial computer expansion bus to interconnect accelerator cards located on multiple servers. The first switch obtains the local device address of each accelerator card on the server, configures an address mapping table for each server based on the local device address of each accelerator card, and forwards data between accelerator cards on different servers according to the address mapping table. This effectively solves the problems of limited computing power in a single server and insufficient bandwidth and high latency in interconnecting multiple servers via Ethernet. It realizes cross-server vertical expansion based on a high-speed serial computer expansion bus, improves the bandwidth of cross-server communication, reduces the latency of cross-server communication, and lays the foundation for realizing high-bandwidth domain communication computing clusters with multiple machines and multiple cards.

The present invention discloses a firmware upgrade method, system, program product, and storage medium, relating to the field of server technology. In the present invention, a management controller can be connected to at least two hosts via a high-speed serial computer expansion bus, and the management controller can set a logical bus device based on its own storage space and mount the logical bus device to each host, so that the host can read and write the storage space based on a high-speed serial computer expansion protocol, thereby improving the data transmission efficiency between the host and the management controller. At the same time, during the firmware upgrade process, the host can first request the management controller to set the management controller's bus communication link to remain locked with the target host, and then control the management controller to perform the firmware upgrade after confirming that the lock is successful. This can prevent the management controller from being switched to communicate with other hosts during the upgrade process, thereby ensuring the reliability of the management controller's firmware upgrade.

The embodiment of the present application provides a firmware update method, system and product, belonging to the technical field of computer systems, the method includes: in response to the firmware update operation, the baseboard management controller obtains the firmware to be updated, and based on the high-speed serial computer expansion protocol, sends the update signal of the firmware to be updated to the conversion module; the conversion module converts the received update signal based on the high-speed serial computer expansion protocol into multiple asynchronous communication update signals corresponding to the update signal, and sends them to the asynchronous communication interfaces of the multiple link compensation modules respectively, wherein the conversion module is respectively connected to the asynchronous communication interfaces of the multiple link compensation modules; any link compensation module updates the firmware to be updated in response to the received asynchronous communication update signal. The embodiment of the present application aims to improve the reliability of the firmware upgrade process of the link compensation module.

The invention belongs to the technical field of multi-core heterogeneous processing, and discloses a communication method and system based on a multi-core heterogeneous processing architecture, and the method comprises the steps: carrying out the optimal configuration of parameters of a standard interface of an expansion bus of a high-speed serial computer based on the data transmission demand between a main processor and a coprocessor; a communication line is adopted to establish communication connection of each data interface, a standardized communication protocol is set, and an adaptive flow control algorithm is introduced to avoid data packet loss and retransmission; and respectively creating driving programs and communication software of the main processor and the coprocessor to realize data interaction and communication control between the processors and the coprocessor. By optimizing PCIE interface configuration and a communication protocol, the communication efficiency is remarkably improved, the communication delay is reduced, the overall performance of the system is improved, and meanwhile good compatibility and expandability are achieved; and by introducing an advanced flow control algorithm, the stability and high efficiency of data transmission are ensured.

The invention relates to the technical field of chip design, and discloses a mainboard management controller chip, a control method thereof and a server, and the mainboard management controller chip comprises a bridging module, a mainboard monitoring module and a selection module which are all integrated in the mainboard management controller chip; the bridging module is used for carrying out data conversion and signal adjustment between a high-speed serial computer expansion bus standard interface and a universal serial bus interface of the mainboard management controller chip; the mainboard monitoring module is used for monitoring and managing server hardware; and the selection module is respectively connected with the bridging module and the mainboard monitoring module and is used for selecting the bridging module or the mainboard monitoring module to operate. In this way, the function of converting a high-speed serial computer expansion bus standard to a universal serial bus and the function of monitoring and managing server hardware are combined into a whole, the two functions are achieved only through one mainboard management controller chip, interface redundancy is reduced, the design difficulty of a hardware circuit is lowered, and the area of a circuit board is reduced.

The invention discloses a storage device prototype verification method and device, equipment and a medium, and relates to the field of storage device tests.The method comprises the steps that a target command issued by a user is analyzed, and a target application subprogram is determined according to analyzed command information; sending the analyzed command information to a driving kernel based on a high-speed serial computer extension bus standard on the basis of the target application subprogram, so that the to-be-verified storage device executes corresponding operation after receiving the analyzed command information sent by the driving kernel; and monitoring the issuing and execution process of the analyzed command information, if the analyzed command information has an error in the issuing or execution process, acquiring a corresponding command execution state, and intercepting a corresponding error command test parameter, so as to perform scene reproduction based on the command execution state and the error command test parameter. Therefore, the prototype verification efficiency oriented to the storage device is improved, and the problem that an error scene is not easy to reproduce is solved.

The present disclosure provides a server resource allocation system, method and device, relates to the field of computers, in particular to the field of cloud computing. The specific implementation scheme is: a terminal is installed with a device BMC (baseboard management controller), a device resource allocation system and a PCIE (high-speed serial computer expansion bus) device set, wherein the device BMC is configured to receive a PCIE resource request of a user and forward the PCIE resource request to the device resource allocation system, the device resource allocation system is configured to select a target PCIE device from the PCIE device set according to the PCIE resource request and allocate the target PCIE device to the user, and the device BMC is configured to send a server restart request for loading the target PCIE device to a server; the server is configured to receive a server restart request sent by the device BMC and load the PCIE device indicated in the server restart request. The implementation can simplify the server elasticity scaling process and improve reliability.

This application discloses an in-vehicle domain controller, electrical equipment, data communication method, and computer-readable storage medium. The in-vehicle domain controller includes a field-programmable gate array (FPGA), a first system-on-a-chip (SoC), and at least one second SoC, each SoC being electrically connected to the FPGA. The first SoC is configured to establish a first high-speed serial computer expansion bus standard link with the FPGA. The second SoC is configured to establish a second high-speed serial computer expansion bus standard link with the FPGA if the first high-speed serial computer expansion bus standard link fails to be established. Thus, by switching to the second high-speed serial computer expansion bus standard link in the event of a failure in establishing the first high-speed serial computer expansion bus standard link, uninterrupted data transmission and stable operation of vehicle functions can be ensured.

This invention discloses a high-speed serial computer extended bus standard terminal device and its clock distribution circuit, belonging to the field of integrated circuit design. When the level conversion circuit receives a "dual-port enable signal from the host", it can control the multiplexer to work in dual-port mode, thereby leading the two reference clocks of the host to the first physical medium sublayer and the second physical medium sublayer respectively. When the dual-port enable signal is not received, it can control the multiplexer to work in single-port mode, so that the reference clock provided by the host through the first output terminal can be synchronously output through the two output terminals of the multiplexer, thereby keeping the two reference clocks synchronized and not affecting the collaborative work of the two physical medium sublayers. Moreover, the forwarding processing performed by the multiplexer does not affect the reference clock quality. In addition, the host can accurately control the working mode of the PCIe terminal device through the dual-port enable signal.

The embodiment of the invention provides a PCIe equipment management method and device, equipment and a medium, and is used for solving the problem that in the prior art, when PCIe equipment is introduced, a BMC needs to be adapted and developed, so that time and labor are wasted. The method is applied to a baseboard management controller on a target server, and comprises the following steps: determining each high-speed serial computer expansion bus standard PCIe device accessed to the target server; aiming at each accessed PCIe device, respectively executing the following operations: acquiring configuration information from one PCIe device, and determining a target out-of-band protocol type corresponding to the PCIe device according to the configuration information; based on the mapping relation between the out-of-band protocol types and the out-of-band channels, a target out-of-band channel associated with the target out-of-band protocol type corresponding to one PCIe device is used as a data transmission channel between the substrate management controller and the PCIe device from all the out-of-band channels.

This disclosure provides a storage device and an electronic device. The storage device includes a carrier for carrying and conducting electronic components, a conversion chip disposed on the carrier, and a storage module. The storage device can be detachably connected to an electronic device. The carrier is provided with a first connection interface, through which the storage device can establish a first communication connection with the electronic device. A second communication connection is established between the storage module and the conversion chip. The conversion chip is used to convert first protocol data obtained from the first communication connection into second protocol data and transmit the second protocol data to the storage module through the second communication connection. The storage module can respond to the second protocol data by performing corresponding target read operations and / or target write operations. The first communication connection is a high-speed serial computer expansion bus standard PCIe connection, and the second communication connection is a general-purpose flash memory storage (UFS) connection.