Allocating lanes of a serial computer expansion bus among installed devices

a technology of expansion bus and serial computer, which is applied in the direction of electric digital data processing, instruments, etc., can solve the problem that half of the lanes of the pcie slot will go unused

Inactive Publication Date: 2015-11-12
LENOVO ENTERPRISE SOLUTIONS SINGAPORE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unfortunately, installing an ×8 PCIe expansion card device in an ×16 PCIe slot means that half of the lanes to the PCIe slot will go unused.

Method used

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  • Allocating lanes of a serial computer expansion bus among installed devices
  • Allocating lanes of a serial computer expansion bus among installed devices
  • Allocating lanes of a serial computer expansion bus among installed devices

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0024]In a first embodiment, the BMC 24 may read the VPD 22 of each PCIe device 20 using a separate communication line 28 to each PCIe slot 18. If the VPD obtained from the PCIe devices indicates that there are redundant resources installed in the PCIe slots (i.e., two PCIe device of the same type, such as Ethernet adapters), then the BMC 24 may determine a priority between the PCIe devices 20. For example, if the redundant PCIe device having the higher priority is not already configured with its maximum link width, then the BMC 24 may control the multiplexer 16 to increase the number of serial communication lanes allocated to the redundant PCIe device having the higher priority and reduce the number of serial communication lanes allocated to the redundant PCIe device having the lower priority.

second embodiment

[0025]In a second embodiment, if the BMC 24 determines that one or more the installed PCIe devices 20 is expected to be hotter than the other installed PCIe devices, then the BMC may reallocate lanes to the PCIe device(s) expected to be cooler. For example, a PCIe device is expected to be hotter if it is physically downstream (in an airflow direction) from the processor 12 or other device that generates lots of heat. Alternatively, the BMC may measure the current temperature of the PCIe devices and allocate more / fewer lanes to one PCIe device over another. A PCIe device that is cooler is more likely to make good use of the lanes than a hotter PCIe device, since the cooler PCIe device is unlikely to throttle its performance.

[0026]“Bifurcation” refers to the division of lanes to be assigned to different devices. The processor shown has a ‘generic’ set of PCIe lanes (say 40 lanes) and knows nothing about the PCIe topology before the BIOS runs. The BIOS scans the PCIe tree looking for c...

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PUM

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Abstract

A method includes a supervisory controller within a computer identifying a plurality of PCIe devices installed within the computer and identifying one or more configurable link width for each of the identified PCIe devices, wherein each of the identified PCIe devices is determined to be installed in a particular PCIe slot. The method further includes the supervisory controller granting a higher priority to a first one of the PCIe devices than to a second one of the PCIe devices, and the supervisory controller controlling the allocation of a fixed number of serial communication lanes from a processor to the plurality of PCIe devices, wherein the first PCIe device is allocated the maximum configurable link width identified for the first PCIe device and the second PCIe device is allocated a link width less than the maximum configurable link width identified for the second PCIe device.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation of U.S. patent application Ser. No. 14 / 273,076 filed on May 8, 2014, which application is incorporated by reference herein.BACKGROUND[0002]1. Field of the Invention[0003]The present invention relates to the control and operation of a serial computer exapansion bus within a computer.[0004]2. Background of the Related Art[0005]Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard using a point to point topology. A group of serial communication lanes form a link connecting two devices, such as connecting a processor to one or more compatible expansion devices. A PCIe link may include from one to thirty-two serial communication lanes. Where the PCIe link is more than one lane, data is striped across the lanes of the link. PCIe slots and expansion card edge connectors may have various widths, such ×1, ×2, ×4, ×8, ×16 or ×32. Unfortunately, installing an ×8 PCI...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F13/40G06F13/42
CPCG06F13/4022G06F13/4018G06F13/4221G06F13/362
Inventor JACOBSON, STEVEN C.NGUYEN, LOC X.REMIS, LUKE D.TENNANT, TIMOTHY R.
Owner LENOVO ENTERPRISE SOLUTIONS SINGAPORE
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