Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Methods and apparatus for a multiple master bus protocol

A bus and protocol technology, applied in the field of multi-master bus protocol devices, can solve problems such as incompatibility

Active Publication Date: 2017-02-22
ASCENSIA DIABETES CARE HLDG AG
View PDF4 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] As will be explained in more detail below, I 2 C limits what the bus master can do to the I 2 The amount of control over which the C bus makes decisions, and thus limits which transactions can use the I 2 C bus while being reliably implemented
I 2 C also has other limitations that may make it unsuitable for some applications

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Methods and apparatus for a multiple master bus protocol
  • Methods and apparatus for a multiple master bus protocol
  • Methods and apparatus for a multiple master bus protocol

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0014] Embodiments of the present invention provide the following improved type I 2 C multi-master bus monopoly method and apparatus: the method and apparatus enable, without interfering with slave-related transactions carried out by other masters, 2 Multiple, non-interruptible slave-related transactions are performed on the C bus. Standard I 2 The C specification provides for enabling one of multiple masters to obtain access to the I 2 An arbitration method for control of the C-bus, but does not provide any means for the master to maintain exclusive control, eg, to complete multiple transactions (eg, read-modify-write transactions) without interrupting the sequence. The present invention enables a master (e.g., microcontroller) to retain exclusive access to a slave (e.g., memory) for multiple consecutive transactions in a manner that does not compete with other masters' access to the slave (e.g., memory) . Note that the term "single transaction" used here means a single r...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Embodiments of the invention provide systems, methods, and apparatus for arbitrating a multi-master computer bus. The embodiments include a multi-master serial computer bus; a first master coupled to the bus; a second master coupled to the bus; a slave device coupled to the bus; a first I / O line from the first master going to the second master and the slave device; and a second I / O line from the second master going to the first master and the slave device. A bus arbitration protocol for arbitrating use of the bus restricts the masters to a single transaction each time either master becomes a bus master, and the masters are each adapted to use the I / O lines to signal to each other not to become a bus master. Numerous other aspects are disclosed.

Description

[0001] related application [0002] This application claims the benefit of co-pending U.S. Provisional Patent Application No. 61, entitled "METHODS AND APPARATUS FORA MULTIPLE MASTER BUS PROTOCOL" filed on February 7, 2014 / 937446, and the entire content of that US Provisional Patent Application is hereby incorporated by reference for all purposes. technical field [0003] The present invention relates to bus protocols, and more particularly, to devices, systems and methods for multi-master bus protocols. Background technique [0004] Built-in integrated circuit standard (Inter-Integrated Circuit standard, known as I 2 C, I2C, i2c, IC, I2C, or IIC) specifies a multi-master serial single-ended computer bus invented by the semiconductor division of Philips (today NXP Semiconductors) and are commonly used to attach low-speed peripherals to motherboards, embedded systems, cellular phones, or other digital electronics. Included here I 2 An overview of C provides information o...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/376G06F13/42
CPCG06F13/364G06F13/376G06F13/404G06F13/4282G06F2213/0016
Inventor 克里斯托弗·迪欧尼斯欧托德·T·斯旺泽格雷戈里·R·斯特夫科维奇
Owner ASCENSIA DIABETES CARE HLDG AG
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com