Method and device for testing expansion bus of high-speed serial computer

An extended bus, high-speed serial technology, applied in the field of processors, can solve problems such as unverifiable and difficult to apply scenarios

Active Publication Date: 2021-08-24
HYGON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In the process of realizing the present invention, the inventor found that there are at least the following technical problems in the prior art: Although the protocol stipulates that when the data packets with higher priority continue When the link is oc

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  • Method and device for testing expansion bus of high-speed serial computer
  • Method and device for testing expansion bus of high-speed serial computer
  • Method and device for testing expansion bus of high-speed serial computer

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Embodiment Construction

[0035] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0036] The embodiment of the present invention provides a kind of high-speed serial computer expansion bus testing method, is applied to the controller of high-speed serial computer expansion bus PCIE bus, such as figure 1 shown, including:

[0037] Step 101, sending a notification message to the slave device, so that the slave device closes...

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Abstract

The invention provides a method for testing an expansion bus of a high-speed serial computer, which is applied to a controller of a high-speed serial computer expansion bus PCIE (Peripheral Component Interface Express) bus, and comprises the following steps: sending a notification message to slave equipment, so that the slave equipment closes a response function aiming at a first type of data packet; sending a plurality of first type data packets to the slave device, so that the first type data packets occupy all retransmission caches of the controller; sending a plurality of second type data packets to the slave device; and after waiting for a first preset time, verifying the priority of the second type of data packets. According to the invention, the occupation state of the link can be accurately created, and the change rule of the priority of the data packet is verified.

Description

technical field [0001] The invention relates to the technical field of processors, in particular to a high-speed serial computer expansion bus testing method and device. Background technique [0002] High-speed serial computer expansion bus PCIE bus is a widely used computer bus, which has the characteristics of point-to-point, high bandwidth and reliable transmission. The PCIE bus is generally considered to have a three-layer structure, namely the physical layer, data link layer and transaction layer. During the data transmission process of the PCIE bus, data of different layers are usually transmitted using different types of data packets. For example, the data transmission of the data link layer adopts the data link layer data packet DLLP, and the data transmission of the transaction layer adopts the transaction layer data packet TLP. Different data packets have different priorities. For example, the priority of DLLP is usually lower than that of TLP. When the higher-p...

Claims

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Application Information

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IPC IPC(8): G06F11/22G06F13/40
CPCG06F11/221G06F13/4022G06F2213/0026Y02D10/00
Inventor 李婧倪亚路陈玉龙黄玲叶鹏玉林佳森
Owner HYGON INFORMATION TECH CO LTD
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