Level shift circuit

Abstract

In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W3 and W4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W3 and W4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N5, N6 and two N-type low-voltage transistors N1, N2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This non-provisional application claims priority under 35 U.S.C.§119(a) on Patent Applications No. 2003-421155 filed in Japan on Dec. 18, 2003 and No. 2004-330249 filed in Japan on Nov. 15, 2004, the entire contents of which are hereby incorporated by references. BACKGROUND OF THE INVENTION [0002] The present invention relates to level shift circuits for translating logic levels, and more particularly relates to level shift circuits configured to operate at low voltage with reduced power dissipation. [0003] A conventional level shift circuit disclosed in Japanese Laid-Open Publication No. 4-40798 has been known. FIG. 14 illustrates the configuration of the conventional level shift circuit. [0004] The level shift circuit shown in FIG. 14 includes two N-type transistors N5 and N6, two cross-coupled P-type transistors P1 and P2, and first and second inverters INV1 and INV2. Each P-type transistor P1 or P2 has its gate connected to the drai...

AI Technical Summary

Benefits of technology

[0018] It is therefore an object of the present invention to provide a level shift circuit, in which in a case where the threshold voltage of N-type high-voltage transistors N5 and N6 is set low considering that the power supply voltage of a low-voltage supply VDD is set low, even if the potentials at the sources of those N-type transistors increase beyond the voltage of the low-voltage supply VDD, a current flow into the low-voltage supply VDD is prevented so as to suppress increases in power dissipation.

[0019] In order to achieve the above object, the present invention adopts the following structures. In the inventive level shift circuit, unlike in the conventional level shift circuit, an input signal at a low-voltage supply VDD level is not input to the sources of N-type first and second high-voltage transistors, and instead, the input signal is input to the gates of N-type low-voltage transistors, thereby preventing current flow into the low-voltage supply VDD. Furthermore, in the inventive level shift circuit, a protection circuit is interposed between the N-type low-voltage transistors and the N-type high-voltage transistors. The protection circuit restricts the voltage applied to the drains of the N-type low-voltage transistors to a low voltage, thereby preventing the breakdown of the N-type low-voltage transistors.

[0020] A second object of the present invention is to provide a level shift circuit, in which N-type complementary-input-signal-pair-receiving transistors present in a level shift circuit such as shown in FIG. 23 are replaced with low-voltage devices, and which operates reliably without causing the breakdown of the N-type transistors, even if the voltage of a low-voltage supply is set low.

[0034] As described above, the inventive level shift circuit has the configuration in which the two N-type high-voltage transistors are respectively connected in series with the two N-type complementary-signal-receiving transistors, which receive the low-voltage complementary signals at their respective gates. Therefore, there is no current path going from the source terminals of the N-type high-voltage transistors to inverters for generating the complementary signals. Accordingly, unlike in the conventional circuits, current flow, going from the source terminals of the N-type high-voltage transistors into the low-voltage supply VDD via parasitic diodes in the complementary-signal-generating inverters, is prevented.

[0037] Furthermore, in another embodiment of the inventive level shift circuit, the threshold voltage of the two N-type high-voltage transistors is set low, so that the level shift circuit operates reliably, even if the voltage of the low-voltage supply VDD is set low.

[0051] As described above, the second inventive level shift circuit, the N-type transistors for receiving the complementary signal pair are composed of low-voltage transistors whose threshold voltage is low. Thus, even if the voltage of the low-voltage supply is set to a lower voltage, the low-voltage transistors operate as intended, allowing the level shift circuit to reliably perform the desired level shifting operation. In addition, the protection circuit prevents application, between the two terminals of the N-type complementary-signal-pair-receiving transistors, of a voltage exceeding the withstand voltage of the N-type complementary-signal-pair-receiving transistors, thereby preventing the breakdown of the N-type complementary-signal-receiving transistors.

Problems solved by technology

In that case, a current flows from the node W3 via a parasitic diode within the first inverter INV1 into the low-voltage supply VDD, causing an increase in power dissipation.

Nevertheless, in the conventional level shift circuit shown in FIG. 23, if the voltage of the low-voltage supply VDD is set to a low voltage close to the threshold voltage of the N-type complementary-signal-receiving high-voltage transistors N11 and N12, it becomes difficult for the N-type complementary-signal-receiving transistors N11 and N12 to operate, causing the level shift circuit to have difficulty in performing the intended operation.

Images