A method for dynamic timing adaptive adjustment of NAND Flash controller chips

Abstract

This application provides a dynamic timing adaptive adjustment method for NAND Flash controller chips, relating to the field of data processing. In this method, a calibration context is centrally located within the NAND Flash controller chip. Controlled transaction scheduling drives delay sampling measurements to obtain the true physical timing characteristics between the controller chip and the memory chips. Timing configurations matching the chip states are dynamically generated based on phase distribution statistics, environmental state information, and operational state information. During system operation, hardware-level feedback statistics are performed on error correction intensity, error count, and retry count. The direction of timing margin adjustment is determined online based on phase distribution changes. Uninterrupted switching of timing configurations is completed at transaction boundaries, thereby achieving multi-round adaptive calibration and improving the performance and reliability balance under different process technologies and different lifespan stages of the chips. Implementing the technical solution provided in this application facilitates the resolution of the problem of insufficient timing adaptability of NAND Flash controller chips under complex operating conditions.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and specifically to a dynamic timing adaptive adjustment method for NAND Flash controller chips. Background Technology

[0002] As NAND Flash storage technology develops towards high density and multi-layer stacking, the physical timing characteristics related to commands, addresses, and data transmission of storage chips exhibit obvious dynamic changes during actual operation due to multiple factors such as process fluctuations, operating temperature variations, power supply voltage disturbances, uncertainties in I / O link parasitic parameters, and long-term erase and write aging.

[0003] Currently, existing NAND Flash controller chips typically use fixed timing table configurations or rely on firmware to perform offline calibration during initialization or under abnormal conditions to match the timing requirements of the storage chips. This type of approach makes it difficult to continuously reflect the real-time changes in the timing characteristics of the chips during system operation. It is prone to insufficient sampling margin when the environment fluctuates or aging intensifies, which leads to increased error correction intensity, increased retries, or even data transmission failures. At the same time, the conservative timing configuration adopted to ensure data reliability will cause unnecessary performance loss and increased access latency when the chip state is stable, making it difficult to achieve a dynamic balance between high performance and high reliability.

[0004] Therefore, there is an urgent need for a dynamic timing adaptive adjustment method for NAND Flash control chips to solve the problem of insufficient timing adaptability of existing control methods under complex operating conditions. Summary of the Invention

[0005] This application provides a dynamic timing adaptive adjustment method for NAND Flash controller chips, which helps to solve the problem of insufficient timing adaptability of NAND Flash controller chips under complex operating conditions.

[0006] The first aspect of this application provides a dynamic timing adaptive adjustment method for a NAND Flash controller chip. The method includes: after triggering calibration management to enter a training state, acquiring a calibration context bound to a target NAND Flash chip; driving delayed sampling measurement to perform multiple sets of timing scan operations under controlled transaction scheduling conditions to obtain phase distribution statistics characterizing the actual physical transmission characteristics between the NAND Flash controller chip and the target NAND Flash chip; and writing the phase distribution statistics into the calibration context; based on the phase distribution statistics and combined with environmental state information and operating state information, determining an available sampling window and corresponding safety margin to generate a candidate timing configuration matching the current chip state; and after completing a consistency check, confirming the candidate timing configuration as the current timing configuration and sending it to the programmable timing generation logic; and performing timing adjustments on the target NAND Flash chip according to the current timing configuration. The system schedules read, write, and erase transactions for the Flash memory chips and performs hardware-level statistics on error correction strength, error count, and retry count during transaction execution, forming a feedback statistics window that is associated with the calibration context. Based on changes in the feedback statistics window and the phase distribution statistics, it dynamically determines the direction of timing margin adjustment and completes online switching of the current timing configuration under transaction boundary conditions. During calibration execution, through coordinated control of transaction scheduling and timing switching, measurement and configuration update operations are inserted without interrupting normal access, enabling the NAND Flash control chip to complete multiple rounds of adaptive calibration and optimization during system operation. This achieves dynamic timing matching and performance reliability balance for NAND Flash chips of different processes, batches, and life stages.

[0007] A second aspect of this application provides a dynamic timing adaptive adjustment device for a NAND Flash controller chip. The device includes an acquisition module and a processing module. The acquisition module, after triggering calibration management to enter a training state, acquires a calibration context bound to a target NAND Flash chip. Under controlled transaction scheduling, it drives delayed sampling measurements to perform multiple sets of timing scan operations to acquire phase distribution statistics characterizing the actual physical transmission characteristics between the NAND Flash controller chip and the target NAND Flash chip, and writes the phase distribution statistics into the calibration context. The processing module, based on the phase distribution statistics and combined with environmental and operational status information, determines an available sampling window and corresponding safety margin to generate a candidate timing configuration matching the current chip state. After completing a consistency check, it confirms the candidate timing configuration as the current timing configuration and sends it to the programmable timing generation logic. The processing module is further configured to perform adjustments to the target NAND Flash chip according to the current timing configuration. The processing module schedules read, write, and erase transactions for the Flash chips and performs hardware-level statistics on error correction intensity, error count, and retry count during transaction execution, forming a feedback statistics window that is associated with the calibration context. The processing module also dynamically determines the timing margin adjustment direction based on changes in the feedback statistics window and phase distribution statistics, and completes online switching of the current timing configuration under transaction boundary conditions. Furthermore, during calibration execution, the processing module inserts measurement and configuration update operations without interrupting normal access through coordinated control of transaction scheduling and timing switching, enabling the NAND Flash control chip to complete multiple rounds of adaptive calibration and optimization during system operation. This achieves dynamic timing matching and performance reliability balance for NAND Flash chips of different processes, batches, and lifespan stages.

[0008] A third aspect of this application provides an electronic device including a processor, a memory, a user interface, and a network interface. The memory is used to store instructions, and both the user interface and the network interface are used to communicate with other devices. The processor is used to execute the instructions stored in the memory to cause the electronic device to perform the method described above.

[0009] A fourth aspect of this application provides a non-transitory computer-readable storage medium storing instructions that, when executed, perform the method described above.

[0010] In summary, one or more technical solutions provided in this application have at least the following technical effects or advantages: By constructing a hardware-level closed-loop control mechanism centered on calibration context within the NAND Flash controller chip, the acquisition, generation, adjustment, and activation of timing parameters are all based on real-time observed physical transmission characteristics and operational feedback. This avoids the adaptation lag issues caused by relying on fixed timing tables or static firmware configuration. By performing delay sampling measurements and generating phase distribution statistics under controlled transaction scheduling, the controller chip can directly reflect the available timing space of the current flash memory under real electrical and I / O link conditions, providing a reliable basis for subsequent timing configuration. Combining environmental and operational status information to determine the available sampling window and safety margin enables precise timing configuration. It achieves a dynamic balance between performance and reliability by ensuring sufficient data reliability while avoiding unnecessary conservatism and redundancy. By performing hardware-level statistics on error correction strength, error count, and retry count during transaction execution and forming a feedback statistical window, timing adjustments can respond to short-term fluctuations and medium- to long-term aging trends, demonstrating continuous self-adaptation capabilities. Simultaneously, it achieves online switching of timing configurations based on transaction boundary conditions and completes multiple rounds of measurement and optimization without interrupting normal access through a gap-filling method, effectively reducing the impact on system throughput and access latency. Overall, it improves the controller chip's universal adaptability, operational stability, and long-term performance consistency for NAND Flash chips of different processes, batches, and lifespans. Therefore, it effectively solves the problem of insufficient timing adaptability of NAND Flash controller chips under complex operating conditions. Attached Figure Description

[0011] Figure 1 A flowchart illustrating a dynamic timing adaptive adjustment method for a NAND Flash controller chip provided in an embodiment of this application; Figure 2 A schematic diagram of a dynamic timing adaptive adjustment device for a NAND Flash controller chip provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0012] Explanation of reference numerals in the attached figures: 21. Acquisition module; 22. Processing module; 31. Processor; 32. Communication bus; 33. User interface; 34. Network interface; 35. Memory. Detailed Implementation

[0013] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0014] In the description of the embodiments of this application, the words "for example" or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design that is described as "for example" or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Rather, the use of the words "for example" or "for instance" is intended to present the relevant concepts in a specific manner.

[0015] In the description of the embodiments of this application, the term "multiple" means two or more. For example, multiple systems means two or more systems, and multiple screen terminals means two or more screen terminals. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0016] To address the aforementioned technical problems, this application provides a dynamic timing adaptive adjustment method for NAND Flash controller chips, referring to... Figure 1 , Figure 1 This is a flowchart illustrating a dynamic timing adaptive adjustment method for a NAND Flash controller chip, provided in an embodiment of this application. The method is applied to a NAND Flash controller chip and includes steps S110 to S150, as follows: S110. After triggering calibration management to enter the training state, obtain the calibration context bound to the target NAND Flash chip, drive the delay sampling measurement to perform multiple sets of timing scan operations under the condition of controlled transaction scheduling, so as to obtain the phase distribution statistics characterizing the real physical transmission characteristics between the NAND Flash control chip and the target NAND Flash chip, and write the phase distribution statistics into the calibration context.

[0017] Specifically, after triggering the calibration management to enter the training state, the training state is first written to the calibration state register. Within the same write transaction, the channel identifier, chip select identifier, and operation type identifier corresponding to the target NAND Flash chip are locked. This ensures that all subsequent training and measurement transactions can only take effect on the physical link defined by the channel identifier and chip select identifier, thereby preventing access from other channels or other chip selects from contaminating the measurement results. The channel identifier uniquely indicates a set of independent I / O channel resources connected to the NAND Flash chip within the control chip, and the chip select identifier uniquely indicates the specific NAND selected on the same channel. The Flash chip or chip enable object, operation type identifier is used to distinguish read transactions, write transactions and erase transactions so that different measurement strategies and different protection strategies can be adopted for different operation types; at the same time, the transaction scheduling is switched to training protection mode and training protection parameters are generated. The training protection mode is used to temporarily rearrange the transaction queue to provide a controllable execution window for training transactions. The training protection parameters are used to constrain the bus free window into which training transactions can be inserted, limit the upper limit of parallelism, and prohibit long burst transmissions across windows. The bus free window refers to a continuous time segment in which the command bus and data bus are simultaneously in an unoccupied state. Limiting the upper limit of parallelism is used to avoid phase jitter caused by shared resource contention due to multi-channel parallel access. Prohibiting long burst transmissions across windows is used to avoid long data bursts that continuously occupy the bus during the execution of training transactions, which would destroy measurement consistency.

[0018] In training protection mode, a calibration context bound to the target NAND Flash chip is allocated in the on-chip storage area. Within this calibration context, the target chip identifier, training round identifier, current timing configuration identifier, measurement strategy identifier, and phase distribution statistics buffer are initialized. The on-chip storage area refers to the storage resources within the control chip that can be accessed by hardware logic with low latency. The calibration context refers to structured storage entries used to carry the status of one or more calibration processes. The target chip identifier is used to uniquely assign calibration results in multi-chip scenarios. The training round identifier is used to distinguish measurement batches at different time points and supports cross-round comparisons. The current timing configuration identifier indicates the currently effective timing configuration version to form a traceable chain. The measurement strategy identifier indicates strategy parameters such as scan range, scan granularity, resampling threshold, and robustness rules. The phase distribution statistics buffer records the set of sampling results and their aggregated statistical values ​​under each scan index. By uniformly writing the above fields into the calibration context, subsequent delayed sampling measurements, phase distribution statistics generation, available segment set generation, and environmental snapshot writing can all complete a read-write closed loop within the same calibration context, ensuring consistency between concepts and data.

[0019] Based on the measurement strategy identifier, a scan set containing a command phase scan set and a data phase scan set is generated. The scan set is then mapped to multiple training transaction sequences, ensuring that each training transaction carries a unique scan index and loads the corresponding phase configuration at the transaction boundary. The command phase scan set covers the available area of ​​command / address related signals under different phase offsets, while the data phase scan set covers the available area of ​​read data sampling phase or write data alignment phase under different phase offsets. The scan set refers to a candidate set composed of multiple discrete phase points, and the training transaction sequence refers to a list of transactions organized in the order of the scan index. The scan index is used to uniquely identify the phase configuration corresponding to a particular training transaction. The transaction boundary refers to the point in time when the previous transaction is completed and the next transaction has not yet been transmitted. Loading the phase configuration at the transaction boundary can prevent the signal relationship within the same transaction from being inconsistent due to phase changes during the transaction. In implementation, the scan index is usually written into the training transaction descriptor, and the programmable timing generation logic reads the scan index and retrieves the corresponding command phase offset and data phase offset from the phase configuration table before transmitting the training transaction. This ensures that each scan index corresponds to a unique and definite phase condition, thereby ensuring that the phase distribution statistics have reproducible experimental conditions.

[0020] During the execution of each training transaction, consistency judgment is performed on the training readback results to form sampling result tags. After repeated sampling reaches a preset threshold, the sampling result tags are robustly processed to generate phase distribution statistics. Training readback refers to executing training commands under specified phase conditions and reading the returned data or status to verify whether the phase conditions are usable. Consistency judgment refers to comparing the returned data with the expected pattern or verification rules to determine whether correct transmission is satisfied. The sampling result tag is used to record whether the scan index passed or failed in this repeated sampling. The preset threshold refers to the number of repeated samplings required for the same scan index to reduce the probability of misjudgment caused by occasional noise. Robust processing refers to aggregating multiple sampling result tags into a more stable final judgment. A commonly used robust processing method is to determine the percentage of passes under the same scan index and write the percentage result into the phase distribution statistics buffer. The calculation used can be expressed as follows:

[0021] in, Indicates that the scan index is The percentage of time that passes through a given point ranges from 0 to 1. This indicates the number of repeated samplings performed on the same scan index, and its value is determined by a preset threshold. Indicates the first Repeated sampling during index scanning The consistency judgment result is set to 1 for success and 0 for failure. This formula obtains the success rate by averaging the repeated sampling results, which can statistically smooth out occasional jitter and make the phase distribution statistically reflect the stability and availability of the actual physical transmission characteristics. Then, the final sampling result label is generated based on the success rate and a preset threshold. For example, if the percentage of users is not less than a threshold, the system is considered available; otherwise, it is considered unavailable, thus obtaining the availability distribution along the scan index axis.

[0022] Based on phase distribution statistics, an available segment set is generated, and the start index, end index, and segment confidence state of consecutive available segments are marked. The available segment set refers to a list of segments consisting of several consecutive available scan indices on the scan index axis. The start and end indices describe the segment boundaries, and the segment confidence state characterizes the reliability of the segment's availability. During implementation, a sequence is labeled with the final sampling results. Perform a connectivity scan, grouping adjacent and all available scan indices into the same available segment, and aggregating the pass rate statistics within the segment into the segment confidence state. A common practice is to take the minimum pass rate within the segment as the conservative confidence level to avoid local vulnerabilities in the segment being masked by the average value. Its calculation can be expressed as the following formula:

[0023] in, Indicates the first The segment confidence status of each available segment, with values ​​ranging from 0 to 1. Indicates the first The set of scan indexes contained in each available segment. Indicates that the scan index is The formula takes the pass rate of the weakest point in the segment as the segment confidence state, so that the segment confidence state can reflect the "most error-prone position". This allows the segment edges with low confidence to be avoided first when determining the available sampling window and safety margin, thus improving the stability of the configuration.

[0024] Phase distribution statistics, available segment set, and environmental snapshots corresponding to the sampling process are written into the calibration context for subsequent timing configuration generation and online switching processing. The environmental snapshot refers to the bound records of temperature and voltage information collected during sampling, describing the external operating environment during the generation of this round of phase distribution statistics. In implementation, temperature and voltage information are collected before and after each training transaction sequence, and these, along with the training round identifier, channel identifier, and chip select identifier, are encapsulated into an environmental snapshot entry and written into the calibration context. This allows the calibration context to determine whether the environment corresponding to the phase distribution statistics is consistent with the current environment when generating candidate timing configurations, thereby determining... Should the safety margin be conservatively expanded or its performance reclaimed? Simultaneously, valid window flags and exception flags are written into the calibration context. The valid window flag declares that phase distribution statistics and the available segment set have been generated and are available for use. The exception flag declares whether there are abnormal situations such as excessively low segment confidence, an empty available segment set, or excessive fluctuations in phase distribution statistics. Subsequent timing configuration generation checks the valid window flags and exception flags when reading the calibration context, then determines the available sampling window based on the phase distribution statistics and the available segment set, and generates candidate timing configurations. This allows for online switching under transaction boundary conditions, achieving a closed-loop association of technical features from the training state to the configuration taking effect.

[0025] S120. Based on phase distribution statistics and combined with environmental and operational status information, determine the available sampling window and corresponding safety margin to generate candidate timing configurations that match the current particle state. After completing the consistency check, confirm the candidate timing configuration as the current timing configuration and send it to the programmable timing generation logic.

[0026] Specifically, when generating the timing configuration matching the current particle state based on phase distribution statistics, the phase distribution statistics entries are first located in the calibration context according to the target particle identifier, channel identifier, and chip select identifier. The valid window flag and abnormal flag of the phase distribution statistics entries are verified to confirm that the phase distribution statistics entries are available. At the same time, environmental status information and running status information are collected and read. The phase distribution statistics entries, environmental status information, and running status information are bound into a timing calculation context, so that subsequent calculations are completed under the same data snapshot and are traceable. The phase distribution statistics are used to describe the availability distribution of each phase configuration in the scan index space. The environmental status information is used to describe the values ​​of temperature and voltage information at the current moment. The running status information is used to describe the values ​​of channel load information, queue depth information, access priority information, and feedback statistical window summary. The timing calculation context is used to carry all intermediate variables and constraints in the process of generating candidate timing configurations in this round, thereby ensuring that the candidate timing configurations are strictly bound to the target particle identifier and reflect the current running conditions.

[0027] In the context of time-series computation, when performing continuous available segment extraction and connectivity filtering on phase distribution statistics to determine the main window set, the availability judgment corresponding to each scan index in the phase distribution statistics is first unified to the final available flag. Then, a connectivity scan is performed on the final available flags of adjacent scan indices to merge continuously available scan indices into continuous available segments. Next, connectivity filtering is performed on these continuous available segments to remove isolated short segments and low-confidence segments, retaining the continuous available segments that satisfy the minimum length constraint and minimum confidence constraint to form the main window set. Continuous available segments refer to the segments on the scan index axis... The set of adjacent indexes that simultaneously satisfy availability criteria; connectivity filtering refers to the rules for filtering and retaining segments based on segment length, segment confidence status, and segment interval; the main window set refers to the set of segments selected for generating sampling center parameters and safety margin parameters; subsequently, the sampling center parameters are determined in the main window set. The sampling center parameters are used to indicate the phase position that the subsequent phase control register should align to. A common method is to take the center position of the start and end indices of the target main window and integerize it, thereby mapping the geometric center of the available sampling window to the executable scan index.

[0028] in, This represents the center scan index corresponding to the sampling center parameter, and its value is a non-negative integer. This represents the starting index of the target main window, and its value is a non-negative integer. This represents the ending index of the target main window, and its value is a non-negative integer and not less than... , This indicates a floor operation; the formula obtains the window center position by averaging the window boundaries, and the floor operation makes the center position directly representable by the hardware register, thereby ensuring that the sampling center parameter falls stably inside the main window and reducing the vulnerability caused by being close to the window boundary.

[0029] When determining the basic safety margin based on the sampling center parameter and window boundaries, the distance from the sampling center parameter to the window boundary is first calculated, and the smaller value of the two distances is taken as the basic safety margin. This ensures that the basic safety margin reflects the remaining space that can still maintain availability in the most unfavorable direction. Here, the window boundary refers to the start and end indices of the target main window. The basic safety margin is used to characterize the fault tolerance margin of the phase configuration within the main window. Preferably, the shortest distance from the sampling center parameter to the two side boundaries is selected to ensure that phase drift in any direction will not immediately exceed the limit, as follows:

[0030] in, This represents the basic safety margin, and its value is a non-negative integer. Indicates the sampling center parameter. Indicates the starting index of the target main window. Indicates the ending index of the target main window. This indicates taking the smaller value; the principle of this formula is to use the shortest distance from the sampling center parameter to the left and right boundaries as the worst-case margin, so that the subsequent timing configuration remains within the main window when small environmental fluctuations or link jitter occur.

[0031] When compensating and correcting the basic safety margin based on environmental and operational status information to generate safety margin parameters, the fluctuation levels of temperature and voltage information, as well as the error correction intensity statistics, error count statistics, and retry count statistics in the feedback statistics window summary, are jointly mapped to risk intensity. Safety margin parameters are increased when risk intensity is high and decreased when risk intensity is low and stable over a long period. Simultaneously, the safety margin parameters are constrained not to exceed the basic safety margin to avoid exceeding the main window boundary. Compensation refers to the conservative increment introduced by environmental fluctuations, and correction refers to the conservative increment or performance recovery reduction introduced by operational feedback. The safety margin parameters are used to ultimately control the command phase margin and data phase margin. One feasible generation method is to normalize various risk factors and then perform a weighted sum to obtain the risk intensity. The basic safety margin is then increased or decreased under the drive of risk intensity, while upper and lower limits are set to prevent excessive conservatism or excessive aggressiveness, as follows:

[0032] in, Indicates the level of risk, with a value ranging from 0 to 1. This represents temperature information, with values ​​taken from the temperature sample output by the control chip's sensor interface or its windowed average. This represents voltage information, with values ​​taken from the voltage sample output by the power supply monitoring interface or its window average. This represents the error correction intensity statistics, with values ​​taken as representative values ​​from the error correction intensity distribution in the feedback statistics window summary. This represents the retry count statistics, with values ​​taken from the retry count increment in the feedback statistics window summary or its smoothed value. , , , These represent the normalization functions that map the corresponding factors to the range of 0 to 1. , , , These represent the weight coefficients of the corresponding factors, satisfying non-negativity and a weight sum of 1. This formula converts environmental fluctuations and operational feedback into a unified risk intensity, enabling the safety margin parameter to adaptively adjust with changes in risk intensity. When generating the safety margin parameter based on risk intensity, the basic safety margin can be corrected according to preset maximum recovery and maximum conservative amounts, and upper and lower limits are used to ensure that the safety margin parameter is within a reasonable range, as detailed below:

[0033]

[0034] in, This represents the safety margin parameter, and its value is a non-negative integer. This represents the minimum safety margin lower limit, and its value is a non-negative integer that is preset by reliability constraints. Indicates the basic safety margin. This represents the maximum conservative level, and its value can be a non-negative real number or a non-negative integer. It is used to limit the maximum conservative increase under high-risk conditions. This represents the maximum recovery amount, and its value can be a non-negative real number or a non-negative integer. It is used to limit the maximum amount of redundancy that can be reduced under low-risk conditions. Indicates the intensity of risk. and These represent taking the smaller value and taking the larger value, respectively; the principle of this formula is to allow for higher risk levels. Increase margin, pass when risk is low Recover margin, and use upper bound. To ensure it doesn't go beyond the main window's boundaries, use the lower bound. This ensures that the reliability threshold is not lowered, thereby achieving a controllable dynamic balance between performance and reliability.

[0035] When mapping sampling center parameters and safety margin parameters to candidate timing configurations and encapsulating them into candidate timing configuration descriptors, the sampling center parameters are first mapped to the center index fields of read phase configuration and write phase configuration, and the safety margin parameters are mapped to command phase margin fields and data phase margin fields. Simultaneously, the target granularity identifier, channel identifier, chip select identifier, training round identifier, environment snapshot identifier, and runtime status summary identifier are written into the candidate timing configuration descriptor. This ensures that the candidate timing configuration descriptor can be uniquely identified and traced back to the phase distribution statistics and feedback statistics window summary that generated it. The selected timing configuration refers to a set of timing configurations that have not yet taken effect but have executable content. The candidate timing configuration descriptor refers to a structured entry that carries the candidate timing configuration field and the traceability field. The read phase configuration and write phase configuration are used to control the reading data sampling phase and the writing data alignment phase. The command phase margin and data phase margin are used to limit the allowable range of phase swing or delay compensation. After encapsulation, the candidate timing configuration descriptor is written into the candidate timing configuration field of the calibration context and the candidate generation flag is set, so that subsequent consistency verification and online switching only need to refer to the candidate timing configuration descriptor without repeated calculation.

[0036] When performing protocol consistency checks and handover consistency checks on candidate timing configuration descriptors, the protocol consistency check verifies that the phase configuration and margin configuration in the candidate timing configuration descriptor meet the minimum interval constraint, maximum delay constraint, and minimum hold constraint of the target interface protocol, and verifies that the sampling center parameter and safety margin parameter will not cause the phase configuration to exceed the available range limited by the main window set, thereby avoiding the generation of configurations that are not executable at the protocol layer or physical layer. The handover consistency check verifies that the difference between the candidate timing configuration descriptor and the current timing configuration descriptor does not exceed the preset handover threshold, and verifies that the transaction scheduler can provide sufficient bus free windows at the transaction boundary to complete register loading and atomic activation, thereby avoiding phase inconsistencies across transactions or burst transmission being truncated during the handover process. After the verification passes, the activation flag of the candidate timing configuration descriptor is set and the current timing configuration field in the calibration context is updated to the candidate timing configuration descriptor, so that the current timing configuration and the candidate timing configuration are consistently replaced in the data structure and provide a unique pointer for the issued action.

[0037] When the transaction scheduler sends a handover permission signal to the programmable timing generation logic under transaction boundary conditions, the transaction scheduler generates handover reservation information based on the result of the handover consistency check. At the transaction boundary moment when the previous transaction has completed and the next transaction has not yet been transmitted, and there is no long burst transmission across the boundary and the lower limit of the bus idle window is met, the transaction scheduler sends a handover permission signal carrying the current timing configuration descriptor index. Upon receiving the handover permission signal, the programmable timing generation logic first loads the current timing configuration descriptor into the shadow register and completes the field integrity check. Then, at the same transaction boundary moment, it atomically switches the shadow register to the effective register and updates the phase control register and delay control register accordingly. The transaction boundary index... The transaction-level control state machine transitions from the completed state to the idle state and prepares to receive the next transaction. The switching permission signal refers to the authorization signal issued by the transaction scheduler to allow the programmable timing logic to perform configuration switching at the transaction boundary. The phase control register is used to store phase-related fields such as read phase configuration and write phase configuration, and the delay control register is used to store delay compensation-related fields such as command phase margin and data phase margin. After the register update is completed, the next transaction generates command waveform, address waveform and data waveform under the constraints of the effective register, thereby realizing the online activation of timing configuration without interrupting normal access, and ensuring that the conversion from candidate timing configuration descriptor to the current timing configuration descriptor is strictly aligned with the transaction boundary.

[0038] S130. Based on the current timing configuration, execute read, write and erase transactions for the target NAND Flash chip, and perform hardware-level statistics on error correction strength, error count and retry count during transaction execution to form a feedback statistics window and keep it associated with the calibration context.

[0039] Specifically, when a feedback statistical window is formed when the preset window termination condition is met, the error count increment and retry count increment are no longer obtained solely from the difference between adjacent window boundaries. Instead, an exponential forgetting accumulation is first performed on error events and retry events within the window, driven by transaction completion events. The operation type identifier, error type identifier, and retry reason identifier are all included in the weighting term, enabling the feedback statistical window to simultaneously reflect the event intensity, event structure, and event decay characteristics over time within the window. This reduces the risk of being misled by the "window boundary effect" and "occasional spikes" in the subsequent determination of the timing margin adjustment direction. During windowing encapsulation, the exponential forgetting accumulation value, weighted structure term, and high-order summary of the error correction intensity distribution are all written into the feedback statistical window entry to form a stronger joint evidence chain with the window contraction marker, window drift marker, and confidence reduction marker of the phase distribution statistics.

[0040] The error count increment is generated using a composite cumulative form with event weights, temporal forgetting, and type normalization. The window-level error intensity increment is output when the window terminates. The calculation used can be expressed as follows:

[0041] in, Indicates the first The window-level error intensity increment for each feedback statistics window, taking values ​​that are real numbers not less than 0. Indicates the first The window boundary time corresponding to the termination of a window Indicates the first The window boundary time corresponding to the termination of a window This represents the index of discrete events within the window, and its value range is... , Indicates at time A set of error events captured by error monitoring feedback; the number of elements in the set can be 0 or a positive integer. Indicates the error event index. Indicates an error event The corresponding operation type identifier can take one of three values: read transaction, write transaction, or erase transaction. Indicates an error event The corresponding error type identifiers must include at least three possible values: read verification failure, programming failure, and erase failure. Indicates an error event The corresponding context identifiers must include at least the channel identifier, chip select identifier, and target particle identifier. This represents the weighting coefficient for operation types. Its value is a real number greater than 0 and is preset by the reliability strategy to reflect the differences in the sensitivity of different operation types to reliability risks. This represents the error type weighting coefficient, which is a real number greater than 0 and is used to characterize the difference in the indication strength of different error types to timing mismatch. This represents the context weight coefficient, which is a real number greater than 0 and is used to assign higher weights to critical contexts in multi-channel or multi-chip select parallel environments. Represents an exponential function. This represents the error forgetting constant, which is a real number greater than 0 and is used to control the weighting of error events closer to the end of the window. Indicates time The scalarized result of the corresponding channel load information has a value range of real numbers not less than 0 and can be obtained by mapping queue depth information or busy ratio information. This formula performs hierarchical weighted summation on the set of error events at each moment within the window, uses the exponential forgetting term to emphasize the indicative role of recent events on the current state, and uses the load normalization term to suppress the deviation of "the number of error events being passively amplified with the number of transactions" under high load, making the window-level error intensity increment closer to "the real risk change under unit operating pressure", thus making it more suitable as the triggering basis for the timing margin adjustment direction.

[0042] The retry count increment is generated using a composite metric of "retry link depth", "retry reason structure", and "retry interval jitter", and the window-level retry strength increment is output at the end of the window. The calculation can be expressed as follows:

[0043] in, Indicates the first The window-level retry intensity increment for each feedback statistics window is a real number not less than 0. Indicates at time The set of retry events recorded as retries by the transaction scheduler. Indicates the retry event index. Indicates a retry event The corresponding operation type identifier, Indicates a retry event The corresponding retry reason identifiers should include at least the following values: insufficient timing margin, uncorrectable ECC, abnormal media condition, and bus contention timeout. This represents the retry reason weighting coefficient, which is a real number greater than 0 and is used to emphasize retry reasons that are more likely to be caused by timing mismatches. This represents the retry link depth coefficient, which is a real number not less than 0 and can be obtained by normalizing the cumulative number of retries for the same transaction descriptor. This represents the retry interval jitter coefficient, which is a real number not less than 0 and can be obtained by mapping the degree of variation of adjacent retry intervals of the transaction. This represents the retry forgetting constant, which is a real number greater than 0 and is used to control the emphasis on recent retry events. By simultaneously introducing the retry cause weight, retry link depth, and retry interval jitter, this formula makes the window-level retry intensity increment not only reflect "how many retries have occurred", but also "whether the retries show chain diffusion and whether they are accompanied by abnormal execution rhythm". This makes it easier to distinguish between occasional retries and retry storm precursors caused by systemic timing mismatch when determining the direction of subsequent timing margin adjustment.

[0044] The error correction intensity distribution summary no longer simply records bucket counts, but instead calculates the normalized probability distribution, distribution entropy, and higher-order moments of the error correction intensity bucket distribution, and uses these as fields in the error correction intensity distribution summary of the feedback statistical window to characterize the concentration, dispersion, and tail risk of the error correction intensity. The calculations used can be expressed as follows:

[0045] in, Indicates the first The error correction intensity distribution entropy of each feedback statistical window, taking values ​​that are real numbers not less than 0. This indicates the number of buckets for error correction intensity, and its value is a positive integer greater than 1. Indicates the first The error correction strength within the window falls into the first... The normalized probability of each bucket, ranging from 0 to 1, and satisfying that the summation over all buckets is 1. Represents the natural logarithm function. Represents extremely small positive numbers, used to avoid The resulting numerical problem is that the value range is a real number close to 0 but greater than 0. This formula quantifies whether the error correction intensity has diffused from the "low error correction concentration state" to the "multi-level error correction mixed state" by calculating the entropy of the probability distribution of the error correction intensity bucket. The increase in entropy often corresponds to the increase in error correction uncertainty and the intensification of the differentiation of the medium state, thus providing a more sensitive statistical signal for the conservative adjustment of the time series margin.

[0046] When writing the feedback statistics window along with the current timing configuration corresponding to the generation of the feedback statistics window into the calibration context, not only the current timing configuration descriptor identifier is written, but also the aforementioned... , and Along with the window start timestamp, window end timestamp, channel identifier, chip select identifier, and operation type identifier, the feedback statistics window entries are written to create a traceable link in the calibration context under the same target granularity identifier: "phase distribution statistics round identifier - current timing configuration descriptor identifier - feedback statistics window sequence". The feedback statistics window is used to carry the reliability feedback summary at the window granularity, the current timing configuration descriptor identifier is used to characterize the timing configuration version used by the transaction execution within the window, and the calibration context is used to carry the consistency status record of the target granularity identifier. Through the above writing method, subsequent timing margin adjustments and online switching decisions can complete trend segment construction and risk assessment based on richer window-level statistics, and avoid insufficient sensitivity or false triggering caused by relying solely on simple differences.

[0047] S140. Based on the changes in the feedback statistics window and phase distribution statistics, dynamically determine the direction of timing margin adjustment, and complete the online switching of the current timing configuration under transaction boundary conditions.

[0048] Specifically, when determining the direction of timing margin adjustment based on changes in feedback statistical windows and phase distribution statistics, multiple consecutive feedback statistical windows corresponding to the same target particle identifier are first read in the calibration context. Alignment analysis is then performed on the feedback statistical windows based on the window sequence number and window timestamp to generate feedback trend segments. These trend segments characterize the evolution direction and fluctuation amplitude of the error correction intensity distribution summary, error intensity increment, and retry intensity increment with respect to the window sequence number. The feedback statistical window refers to a window-level summary entry formed by windowing the statistical context under preset window termination conditions. The window sequence number is used to characterize the order of the windows. The feedback trend segment refers to a trend sequence obtained by splicing multiple consecutive window summaries. Simultaneously, the current round entry and the previous round entry of the phase distribution statistics are read, and the two rounds are analyzed... Subphase distribution statistics perform cross-round comparisons to generate window shrinkage markers, window drift markers, and confidence reduction markers. Cross-round comparisons refer to comparing the boundary and center changes of the main window set within the same or comparable scan index space. The window shrinkage marker characterizes a decrease in the effective width of the main window set; the window drift marker characterizes the offset direction of the sampling center parameter; and the confidence reduction marker characterizes an overall decrease in the segment confidence state or a decrease in the minimum value of the available segment set. Window shrinkage can be obtained by subtracting the boundary width of the main window set; window drift can be obtained by subtracting the sampling center parameter; and confidence reduction can be obtained by subtracting the minimum or weighted average of the segment confidence state. In a typical implementation, the window width difference, center difference, and confidence difference are calculated separately, and the corresponding markers are set accordingly, as follows:

[0049] in, This represents the window width difference across rounds in the phase distribution statistics, and its value is an integer. Indicates the first The set of main windows for each round is the window width of the selected target main window, and the value is an integer not less than 0. Indicates the first The round corresponds to the window width of the target main window, and its value is an integer not less than 0; this formula characterizes whether the available sampling window has shrunk by comparing the changes in window width between adjacent rounds. If the value is negative and the magnitude exceeds the preset threshold, the window shrinkage flag is set.

[0050]

[0051] in, This represents the difference in sampling center parameters across rounds in the phase distribution statistics, and its value is an integer. Indicates the first The sampling center parameter for each round takes a non-negative integer value. Indicates the first The sampling center parameter for each round takes a non-negative integer value; this formula characterizes the drift direction of the available sampling window by comparing the changes in the sampling center parameter between adjacent rounds. If the absolute value exceeds the preset threshold, the window drift marker is set and the drift direction is indicated by a symbol.

[0052]

[0053] in, This represents the segment confidence difference across rounds in the phase distribution statistics, and its value is a real number. Indicates the first The set of available segment indices within the main window of each round; the number of elements in the set is a positive integer. Indicates the first Rounds The segment confidence status of each available segment, with values ​​ranging from 0 to 1. Indicates the first The set of available segment indices within the round's main window set. Indicates the first Rounds The confidence status of each available segment; this formula characterizes whether the confidence has decreased by comparing the change in the confidence status of the weakest segment in the main window set of adjacent rounds. If the value is negative and the amplitude exceeds the preset threshold, the position signal will be lowered.

[0054] When generating the timing margin adjustment direction marker based on the feedback trend segment and window contraction marker, window drift marker, and confidence reduction marker, the window-level features in the feedback trend segment are extracted as a trend intensity vector, and the window contraction marker, window drift marker, and confidence reduction marker are extracted as a window structure vector. Subsequently, in the calibration management strategy determination logic, the trend intensity vector and window structure vector are fused to obtain an adjustment risk score, and the timing margin adjustment direction marker is generated based on the adjustment risk score. The timing margin adjustment direction marker indicates whether subsequent candidate timing configurations should increase the safety margin, maintain the safety margin, compress the redundancy margin, or perform recalibration. The trend intensity vector can be composed of changes in error correction intensity distribution entropy, changes in error intensity increment, and changes in retry intensity increment. The window structure vector can be composed of window width difference, center difference, and segment confidence difference. To ensure the comparability of the determination for features of different dimensions, each feature is first normalized and mapped before being weighted and summed to obtain the adjustment risk score, as follows:

[0055] in, This indicates an adjustment to the risk score, with a value ranging from 0 to 1. This represents the change in the error correction intensity distribution entropy within the feedback trend segment. It is a real number and can be obtained by subtracting the error correction intensity distribution entropy of the earliest window from the error correction intensity distribution entropy of the latest window. This represents the change in error intensity increment within the feedback trend segment. It is a real number and can be obtained by subtracting the error intensity increment of the earliest window from the error intensity increment of the latest window. This represents the change in retry intensity increment within the feedback trend segment. It is a real number and can be obtained by subtracting the retry intensity increment of the earliest window from the retry intensity increment of the latest window. Indicates the window width difference. Indicates the difference in sampling center parameters. Indicates the confidence difference of the segment. to This represents the weighting coefficient, which is a real number not less than 0 and has a weight sum of 1. This represents a normalized mapping function that maps any real number input to the range of 0 to 1, and the output increases when the input represents increased risk. This formula maps "feedback deterioration trend" and "window structure degradation" together to an adjustment risk score, enabling the policy decision logic to determine whether to increase the safety margin or trigger recalibration using a single scalar. Subsequently, it generates a timing margin adjustment direction flag based on the adjustment risk score and a preset threshold range. For example, when the adjustment risk score is higher than the high threshold, it generates an increase safety margin or recalibration flag; when the adjustment risk score is lower than the low threshold, it generates a compression redundancy margin flag; and when the adjustment risk score is in the middle range, it generates a maintenance or small-step tracking flag.

[0056] When generating candidate timing configurations based on timing margin adjustment direction markers and encapsulating them into candidate timing configuration descriptors, the current timing configuration descriptor and the sampling center parameters and window boundaries of the latest round phase distribution statistics are first read in the calibration context. Then, an update strategy is selected based on the timing margin adjustment direction markers. When the timing margin adjustment direction markers indicate increasing safety margin, the command phase margin and data phase margin are increased preferentially without changing the sampling center parameters or only backing up towards the window center. When the timing margin adjustment direction markers indicate compressing redundancy margin, the command phase margin and data phase margin are reduced while keeping the sampling center parameters from exceeding the window center. When the timing margin adjustment direction is marked as small-step tracking, the sampling center parameter is offset stepwise according to the window drift mark, and the safety margin parameter is kept no lower than the minimum safety margin limit. The updated sampling center parameter and safety margin parameter are mapped to candidate timing configurations, and the target particle identifier, channel identifier, chip select identifier, phase distribution statistical round identifier, feedback trend segment identifier, and adjustment risk score are encapsulated together as candidate timing configuration descriptors. This makes the candidate timing configuration descriptor contain both executable timing fields and traceable generation basis, thus providing a unique object for subsequent handover consistency verification, online handover, and rollback handover.

[0057] When performing handover consistency checks and generating handover plan entries for candidate timing configuration descriptors under transaction boundary conditions, calibration management reads the candidate timing configuration descriptors and the current timing configuration descriptors, performs differential threshold checks on the phase field difference and margin field difference between the two, and performs boundary checks on whether the candidate timing configuration descriptors meet the boundary constraints of the main window set. At the same time, it queries the transaction scheduler to see if there are long burst transmissions across transaction boundaries and whether there are high-priority transactions that must be executed continuously. If the above checks pass, a handover plan entry is generated and written to the calibration context. The handover consistency check is used to ensure that online handover does not introduce excessive phase jumps that would cause the next transaction to fail to sample. The handover plan entry is used to describe the handover triggering conditions, the handover effective boundary, and the handover rollback conditions. The handover triggering conditions are limited to reaching the transaction boundary and meeting the lower limit of the bus idle window. The handover effective boundary is limited to the boundary point where the previous transaction is completed and the next transaction has not been transmitted. The handover rollback condition is limited to triggering a handover when a sudden increase in retry intensity increment or a significant increase in error correction intensity distribution entropy occurs in several consecutive feedback statistics windows after the handover. This ensures that online handover is constrained to a controllable time and is reversible.

[0058] When the transaction scheduler sends a switching permission signal to the programmable timing generation logic at the transaction boundary constrained by the switching plan entry, the transaction scheduler continuously monitors the transaction state machine during operation. When it detects a transaction boundary that meets the switching triggering conditions of the switching plan entry, it sends a switching permission signal to the programmable timing generation logic, carrying the candidate timing configuration descriptor index. After receiving the switching permission signal, the programmable timing generation logic first loads the candidate timing configuration descriptor into the shadow configuration register and performs field integrity checks and boundary consistency checks. Then, it performs an atomic update at the same transaction boundary, switching the shadow configuration register to the effective configuration register and synchronously updating the phase control register and delay control register, so that the next transaction is constrained by the new current timing configuration from the start time. The atomic update refers to the simultaneous switching of multiple register fields in an indivisible manner in the hardware control state machine, avoiding intermediate states caused by some fields being updated while others are not. After the atomic update is completed, the effective flag of the candidate timing configuration descriptor is set and the current timing configuration field in the calibration context is updated to the candidate timing configuration descriptor, thereby completing the online effective closed loop from the candidate timing configuration to the current timing configuration.

[0059] After the switchover is completed, a switchover effect marker is generated based on the subsequent feedback statistical window. When a rollback switchover is executed when preset rollback conditions are met, the error monitoring feedback generates multiple consecutive subsequent feedback statistical windows after the switchover, with the observation window length specified in the switchover plan entry. These windows are then aligned and compared with the feedback trend segments before the switchover to generate switchover effect markers. These effect markers include at least an error correction improvement marker, a retry improvement marker, and an error stability marker. The error correction improvement marker characterizes whether the error correction intensity distribution entropy has decreased or whether the proportion of high error correction buckets has decreased. The retry improvement marker characterizes whether the retry intensity increment has decreased. The error stability marker characterizes whether the error intensity increment has decreased. Whether the quantity falls back to an acceptable range; when the switching effect flag is not valid and the preset rollback conditions are met, the calibration management writes the rollback switch as a new switching plan entry into the calibration context, and under the transaction boundary conditions, the transaction scheduler sends a switching permission signal to the programmable timing generation logic again, so that the programmable timing generation logic restores the effective configuration register to the current timing configuration descriptor before the switch and completes the atomic update, thereby eliminating the reliability degradation caused by adverse adjustment through rollback switch, and triggering a more conservative timing margin adjustment direction flag or triggering a recalibration flag after rollback switch, so as to realize the closed-loop control of online switching between timing margin adjustment and current timing configuration.

[0060] S150. During the calibration process, through the coordinated control of transaction scheduling and timing switching, measurement and configuration update operations are inserted without interrupting normal access, so that the NAND Flash controller chip can complete multiple rounds of adaptive calibration and optimization during system operation, so as to achieve dynamic timing matching and performance reliability balance for NAND Flash particles of different processes, batches and life stages.

[0061] Specifically, during the calibration execution process, when generating calibration insertion conditions, calibration management continuously reads the channel load status, queue depth status, and transaction type distribution status from the transaction scheduler, and binds them to the calibration context corresponding to the target granularity identifier to form an insertion evaluation snapshot. The channel load status characterizes the busy percentage or effective transmission percentage of the I / O channel corresponding to the channel identifier within the statistical period; the queue depth status characterizes the cumulative number of pending transaction descriptors in the transaction queue; and the transaction type distribution status characterizes the percentage and arrival rate of read, write, and erase transactions in the queue. Calibration insertion conditions define the trigger threshold and resource limit for allowing calibration transactions to be inserted, including at least the minimum idle percentage threshold, the maximum insertion occupancy ratio threshold, the maximum consecutive insertion count threshold, and the high-priority suppression threshold, ensuring that the insertion of calibration transactions does not disrupt the throughput and latency boundaries of normal access. One implementation method maps the channel load status and queue depth status to insertion allowance, and the transaction type distribution status to insertion sensitivity, then uses both to jointly determine whether insertion is allowed and the strength of the allowed insertion, as follows:

[0062] in, Indicates the first The allowable gap for each evaluation period, with a value ranging from 0 to 1. This represents a sigmoid mapping function that maps real numbers to the range of 0 to 1, with the output being closer to 1 as the input increases. to This represents the weighting coefficient, which is a real number and preset by the chip strategy. This is a scalarized result representing the channel load status, ranging from 0 to 1, with larger values ​​indicating busier traffic. The scalar result representing the queue depth state is a real number not less than 0, given by the number of transaction descriptors in the transaction queue or its smoothed value. This represents the proportion of high priority, with a value ranging from 0 to 1, and is obtained by jointly mapping the transaction type distribution status and priority distribution. This formula increases the allowance for insertion when the channel load is low, the queue depth is small, and the proportion of high priority is low, so that insertion behavior occurs first during periods of low system pressure, thereby satisfying the constraint of not interrupting normal access.

[0063] When selecting a transaction gap as an insertion point in the transaction queue based on the calibration insertion conditions, the transaction scheduler calculates the earliest launch time of the next identifiable transaction and the available bus time slots when each transaction completion event arrives. If the insertion allowance is higher than the insertion threshold and the maximum insertion occupancy ratio threshold is met, the available bus time slot is registered as a candidate insertion point. Here, a transaction gap refers to the available time slots between adjacent transactions, an available bus time slot refers to a continuous time segment where the command bus and data bus are not simultaneously occupied, and an insertion point refers to the specific transaction gap selected for inserting the calibration transaction. To suppress jitter caused by frequent insertions, the transaction scheduler also applies minimum interval constraints and maximum consecutive insertion count constraints to the candidate insertion points, ensuring that the insertion points are distributed along the time axis and do not form continuous calibration bursts, thereby avoiding sudden pressure on normal access.

[0064] When a calibration transaction carrying a measurement identifier or configuration update identifier is inserted at the insertion point and the calibration transaction is bound to the calibration context, the transaction scheduler constructs a calibration transaction descriptor with the same format as a normal transaction descriptor. The target particle identifier, channel identifier, chip select identifier, and operation type identifier are written into the calibration transaction descriptor, along with a measurement identifier or configuration update identifier to distinguish the purpose of the calibration transaction. A calibration transaction is a dedicated transaction used to perform delayed sampling measurements or timing configuration updates. The calibration transaction descriptor is a structured entry carrying calibration transaction fields and binding fields. The measurement identifier indicates the delayed sampling measurement path, and the configuration update identifier indicates the online switchover preparation path. The binding method involves writing a calibration context index into the calibration transaction descriptor, enabling delayed sampling measurements, timing calculation logic, and programmable timing generation logic to access the same calibration context through the calibration context index. This ensures that measurement results, candidate timing configurations, and switchover plan entries are all written back to the same calibration context and have traceable consistency.

[0065] When a calibration transaction carrying a measurement identifier triggers a delayed sampling measurement and writes the measurement result to the calibration context while keeping the current timing configuration unchanged, the programmable timing logic keeps the effective configuration register unchanged during the execution of the calibration transaction. It generates command waveforms, address waveforms, and data waveforms according to the current timing configuration. At the same time, it passes the measurement identifier in the calibration transaction descriptor to the delayed sampling measurement to start a lightweight measurement sequence. The lightweight measurement sequence refers to sampling and updating the sensitive section of the phase distribution statistics without expanding the scan range to capture small drifts. After the delayed sampling measurement is completed, it writes the incremental measurement result to the phase distribution statistics field or incremental statistics field of the calibration context and updates the phase distribution statistics round identifier or incremental round identifier. At the same time, it updates the environmental snapshot in the calibration context to record the temperature and voltage information at the measurement time. The key to keeping the current timing configuration unchanged is that the measurement path only updates the statistics field and does not write to the candidate timing configuration field, thereby avoiding the instantaneous timing switching side effect of the measurement transaction on normal access.

[0066] When a calibration transaction carrying a configuration update identifier triggers online handover preparation for candidate timing configurations and completes the current timing configuration update when the transaction boundary conditions are met, the calibration management, upon receiving the configuration update identifier, reads the candidate timing configuration descriptor from the calibration context and performs a handover consistency check on the candidate timing configuration descriptor to generate a handover plan entry. The handover plan entry includes at least the handover trigger condition, the handover effective boundary, and the rollback condition. Subsequently, the transaction scheduler monitors the transaction boundary during operation and determines whether the handover trigger condition is met. The transaction boundary refers to the point in time where the previous transaction is completed and the next transaction has not yet been launched. The handover trigger condition includes at least the lower limit of the bus idle window. The following conditions must be met: no cross-boundary long burst transmissions and high-priority suppression thresholds are satisfied. When the switching trigger condition is met, the transaction scheduler sends a switching permission signal to the programmable timing generation logic, carrying the candidate timing configuration descriptor index. The programmable timing generation logic loads the candidate timing configuration descriptor into the shadow configuration register and performs an atomic update at the transaction boundary, switching the shadow configuration register to the effective configuration register and synchronously updating the phase control register and delay control register. This ensures that the next transaction is constrained by the updated current timing configuration from the start time and takes effect online. At the same time, the effect result is written back to the current timing configuration identifier field of the calibration context to complete the configuration version closure.

[0067] After each calibration round, when updating the calibration context and dynamically adjusting subsequent calibration insertion frequency, measurement range, and margin adjustment strategies, calibration management increments the round identifier and writes it into the calibration context upon completion of the switchover plan item or lightweight measurement sequence. Simultaneously, it updates the current timing configuration identifier to the latest effective timing configuration version and writes the latest feedback statistics window summary and the latest phase distribution statistics round identifier into the calibration context to form a status snapshot. Subsequently, based on the risk intensity, adjustment risk score, and switchover effect flag in the calibration context, it updates the calibration insertion frequency, measurement range, and margin adjustment strategies. The calibration insertion frequency refers to the number of calibration transactions allowed to be inserted per unit of time. The target number of times, the measurement range refers to the set of intervals or the width of the intervals covered by the measurement within the phase distribution statistical scan index space, and the margin adjustment strategy refers to the increase step size, the decrease step size, and the minimum safety margin lower limit adopted for the safety margin parameters when generating candidate timing configurations; one implementation method is to integrate the risk intensity and the adjustment risk score into a calibration intensity factor, and use the calibration intensity factor to drive the adaptive scaling of the insertion frequency and the measurement range, so that when the risk increases, the insertion frequency increases and the measurement range expands, and when the risk decreases, the insertion frequency decreases and the measurement range converges, thereby achieving multiple rounds of adaptive calibration and optimization without interrupting normal access and maintaining a dynamic balance between performance and reliability, as follows:

[0068] in, This represents the calibration intensity factor, with a value ranging from 0 to 1. This represents the risk intensity obtained by fusing environmental and operational status information, with a value ranging from 0 to 1. This represents the adjusted risk score obtained by fusing feedback trend segments and window structure markers, with a value ranging from 0 to 1. to This represents the weight coefficient, which is a real number not less than 0 and is preset by the strategy. This represents a degradation indicator variable, taking a value of 0 or 1. It is set to 1 when the switching effect flag indicates reliability degradation after switching or when the confidence reduction flag is set; otherwise, it is set to 0. and These represent the upper and lower limit operators truncated to the range of 0 to 1, respectively. This formula unifies the current risk, adjusted risk, and degradation indication into a calibration intensity factor, enabling subsequent insertion frequency, measurement range, and margin adjustment step size to adaptively change under the same factor, as detailed below:

[0069] in, This indicates the insertion frequency for subsequent calibration, and its value is a real number not less than 0. This represents the lower limit of the minimum insertion frequency, and its value is a real number not less than 0, preset by performance constraints. This indicates the upper limit of the maximum insertion frequency, and its value is greater than or equal to... The real number is preset by reliability constraints. This represents the calibration intensity factor; the formula dynamically matches calibration overhead with reliability requirements by increasing the insertion frequency when the risk increases and decreasing the insertion frequency when the risk decreases.

[0070]

[0071] in, This indicates the intensity of the subsequent measurement range, taking the value of a real number not less than 0, and can be mapped to the width of the scan index interval or the number of intervals. This represents the lower limit of the minimum measurable intensity range, and its value is a real number not less than 0. This indicates the upper limit of the maximum measurable intensity range, with a value greater than or equal to... real numbers, This represents the calibration intensity factor; the formula balances the phase distribution statistical update with the system load by expanding the measurement range when the risk increases and converging the measurement range when the risk decreases.

[0072] In one possible implementation, when constructing the time-series evolution trajectory during continuous system operation, calibration management uses the target granularity identifier as a unique index to sequentially read the round identifier, historical time-series configuration identifier, and corresponding feedback statistical window sequence from the calibration context. It then writes the current time-series configuration identifier, sampling center parameters, safety margin parameters, switching plan entry summary, switching effect marker, and window-level statistical summary corresponding to each round, aligned with timestamps, into the evolution record table, thereby forming a time-series evolution trajectory for the same target granularity identifier. This time-series evolution trajectory describes the version of the time-series configuration during long-term operation. This replacement path and its causal relationship with reliability feedback, the round identifier is used to distinguish different calibration rounds and ensure that the trajectory can be replayed in chronological order, the historical time-series configuration identifier is used to mark the time-series configuration version that takes effect in each round, and the feedback statistical window sequence is used to characterize the reliability statistical results such as the error correction intensity distribution summary, error intensity increment and retry intensity increment during the effective period of this version; by binding the version information and window-level statistical information to the same evolution record table, it is possible to accurately locate "when, what kind of feedback, and what configuration was switched to" in the future, and avoid mixing statistical results from different versions, which would lead to distortion of evolution judgment.

[0073] When generating evolutionary status markers by correlating the temporal evolution trajectory with current environmental and operational status information, calibration management collects current environmental and operational status information simultaneously with the generation of the evolutionary record table. This information is then correlated and mapped with entries from the most recent rounds of the evolutionary record table. This correlation mapping includes at least the synchronization alignment of temperature and voltage information on the time axis, the synchronization alignment of channel load status and queue depth status on the window axis, and the synchronization alignment of operation type distribution on the transaction axis. Ultimately, evolutionary status markers are output under the same target particle identifier. Environmental status information describes the long-term drift, short-term fluctuations, and fluctuation frequency of temperature and voltage information, while operational status information describes channel load status and queue depth. The evolutionary state label is used to hierarchically express the temporal stability of granular components, including at least a stable trend, a declining trend, and an improving trend, based on the distribution of status, transaction type, and priority. The stable trend indicates that the frequency of temporal configuration version changes is low under similar environmental and load conditions, and the feedback statistical window sequence has not shown continuous deterioration. The declining trend indicates that under similar environmental and load conditions, there are frequent configuration changes that require increasing safety margins or triggering recalibration, and the feedback statistical window sequence shows signs of continuous deterioration. Through this correlation analysis, the evolutionary state label can distinguish between transient changes caused by short-term environmental disturbances and long-term degradation caused by erase and write aging, thus providing a more robust basis for the subsequent scheduling of insertion frequency and scan range.

[0074] When the evolutionary state marker indicates a declining trend in timing stability, the trigger priority of calibration insertion conditions is increased and the scan range of delayed sampling measurements is expanded. In the calibration insertion condition generation logic, calibration management increases the trigger weight related to reliability risk, making it easier to reach the insertion threshold under the same channel load and queue depth conditions. Simultaneously, the maximum consecutive insertion count threshold is raised and the minimum insertion interval constraint is lowered to insert calibration transactions more densely without violating the high-priority suppression threshold. The trigger priority characterizes the scheduling priority of calibration transactions when the insertion condition is met. Expanding the scan range increases the width of the phase interval covered by the scan set or the number of scan indices in delayed sampling measurements, enabling the capture of physical transmission characteristic changes such as main window set shrinkage, increased window drift, or deepened confidence reduction. The expansion of the scan range can be achieved by switching the measurement strategy identifier to enhanced mode. In enhanced mode, not only are sensitive sections sampled and updated, but encrypted scans are also performed near the boundaries of the main window set. When necessary, the command phase scan set and data phase scan set are expanded simultaneously, thereby enhancing the ability to capture changes in physical transmission characteristics and reducing the probability of misjudging them as occasional noise.

[0075] When the evolutionary state marker indicates that the timing stability is in a stable trend, the calibration management reduces the trigger frequency of the calibration insertion condition and narrows the scan range of the delayed sampling measurement. In the calibration insertion condition generation logic, the insertion allowance gain is reduced, making the insertion threshold more difficult to trigger under the same channel load and queue depth. At the same time, the maximum bus occupancy ratio threshold is lowered and the minimum insertion spacing constraint is raised to avoid excessive bus resource consumption by calibration transactions. The trigger frequency is used to characterize the number of insertion points actually triggered per unit time. Narrowing the scan range is used to limit the delayed sampling measurement to a small number of scan indices near the center of the main window set or to update only local segments in the most recent drift direction, thereby reducing the bus occupancy and statistical overhead caused by measurement. At the same time, the measurement strategy identifier is switched to lightweight mode. In lightweight mode, existing phase distribution statistics are reused first and sparse verification is only performed on segments that are sensitive to changes in confidence state, so as to reduce calibration overhead and release access bandwidth when the timing is stable, thereby improving the throughput and latency performance of normal read and write access.

[0076] When dynamically adjusting the timing margin adjustment step size based on evolutionary state markers, calibration management writes the evolutionary state markers as long-term memory variables for the margin adjustment strategy into the calibration context. After generating the timing margin adjustment direction marker, the margin adjustment step size is adaptively tuned. The margin adjustment step size controls the magnitude of single changes in the safety margin parameter during increases or decreases. When the evolutionary state marker shows a downward trend, the margin adjustment step size is set to a more conservative incremental step size and the recovery step size is limited, making the increase in the safety margin parameter more rapid and the compression more cautious, thereby reducing the risk of timing mismatch. To suppress error propagation, when the evolution state is marked as a stable trend, the margin adjustment step size is set to a finer-grained small-step tracking step size, and redundant margin is gradually recovered as the switching effect mark continues to improve, making the performance recovery process smoother and avoiding frequent oscillations. By introducing the evolution state mark into the co-tuning of the insertion conditions, scan range and margin adjustment step size, the dynamic timing adaptive adjustment method forms a self-learning calibration and optimization mechanism for the entire life stage of the particle during long-term operation, enabling the control chip to maintain more consistent timing matching consistency for NAND Flash particles of different processes, batches and life stages and improve the overall reliability of the system.

[0077] This application also provides a dynamic timing adaptive adjustment device for NAND Flash controller chips, referring to... Figure 2 , Figure 2This is a schematic diagram of a dynamic timing adaptive adjustment device for a NAND Flash controller chip provided in an embodiment of this application. The device is the NAND Flash controller chip itself, which includes an acquisition module 21 and a processing module 22. The acquisition module 21 is used to acquire the calibration context bound to the target NAND Flash chip after triggering calibration management to enter the training state, and drive delay sampling measurement to perform multiple sets of timing scan operations under the condition of controlled transaction scheduling, so as to acquire the characteristics of the NAND Flash controller chip and the target NAND Flash chip. The processing module 22 is used to perform phase distribution statistics on the actual physical transmission characteristics between Flash chips and write the phase distribution statistics into the calibration context. The processing module 22 is used to determine the available sampling window and corresponding safety margin based on the phase distribution statistics and combined with environmental and operational status information to generate candidate timing configurations matching the current chip state. After completing consistency verification, the candidate timing configuration is confirmed as the current timing configuration and sent to the programmable timing generation logic. The processing module 22 is also used to schedule read, write, and erase transactions for the target NAND Flash chip according to the current timing configuration, and to perform hardware-level statistics on error correction strength, error count, and retry count during transaction execution, forming a feedback statistics window and maintaining its association with the calibration context. The processing module 22 is also used to dynamically determine the timing margin adjustment direction based on changes in the feedback statistics window and phase distribution statistics, and to complete the online switching of the current timing configuration under transaction boundary conditions. The processing module 22 is also used to insert measurement and configuration update operations during calibration execution without interrupting normal access through coordinated control of transaction scheduling and timing switching, so that the NAND... The Flash controller chip completes multiple rounds of adaptive calibration and optimization during system operation to achieve dynamic timing matching and performance reliability balance for NAND Flash chips of different processes, batches and life stages.

[0078] It should be noted that the above embodiments of the apparatus are only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0079] This application also provides an electronic device, with reference to... Figure 3 , Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device may include: at least one processor 31, at least one network interface 34, a user interface 33, a memory 35, and at least one communication bus 32.

[0080] The communication bus 32 is used to enable communication between these components.

[0081] The user interface 33 may include a display screen and a camera. Optionally, the user interface 33 may also include a standard wired interface and a wireless interface.

[0082] The network interface 34 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0083] The processor 31 may include one or more processing cores. The processor 31 connects to various parts of the server via various interfaces and lines, executing instructions, programs, code sets, or instruction sets stored in the memory 35, and calling data stored in the memory 35 to perform various server functions and process data. Optionally, the processor 31 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 31 may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content to be displayed on the screen; and the modem handles wireless communication. It is understood that the modem may also not be integrated into the processor 31 and may be implemented as a separate chip.

[0084] The memory 35 may include random access memory (RAM) or read-only memory. Optionally, the memory 35 may include a non-transitory computer-readable storage medium. The memory 35 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 35 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 35 may also be at least one storage device located remotely from the aforementioned processor 31. Figure 3 As shown, the memory 35, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and an application program for a dynamic timing adaptive adjustment method for a NAND Flash control chip.

[0085] exist Figure 3 In the electronic device shown, the user interface 33 is mainly used to provide an input interface for the user and to obtain the user input data; while the processor 31 can be used to call an application program stored in the memory 35 for a dynamic timing adaptive adjustment method for a NAND Flash control chip. When executed by one or more processors, the electronic device executes one or more methods as described in the above embodiments.

[0086] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0087] This application also provides a non-transitory computer-readable storage medium storing instructions. When executed by one or more processors, these instructions cause an electronic device to perform one or more of the methods described in the above embodiments.

[0088] The foregoing description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Those skilled in the art will readily conceive of other embodiments of this disclosure upon considering the specification and the disclosure of practical truth. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described in this disclosure. The specification and embodiments are considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

Claims

1. A dynamic timing adaptive adjustment method for NAND Flash controller chips, characterized in that, The method includes: After triggering calibration management to enter the training state, the calibration context bound to the target NAND Flash chip is obtained. Under the condition of controlled transaction scheduling, the delayed sampling measurement is driven to perform multiple sets of timing scan operations to obtain phase distribution statistics characterizing the real physical transmission characteristics between the NAND Flash control chip and the target NAND Flash chip, and the phase distribution statistics are written into the calibration context. Based on the phase distribution statistics and combined with environmental and operational status information, the available sampling window and corresponding safety margin are determined to generate a candidate timing configuration that matches the current particle state. After completing the consistency check, the candidate timing configuration is confirmed as the current timing configuration and sent to the programmable timing generation logic. Based on the current timing configuration, read, write, and erase transactions are scheduled for the target NAND Flash chip. During the transaction execution, hardware-level statistics are performed on the error correction strength, error count, and retry count to form a feedback statistics window and maintain association with the calibration context. Based on the changes in the feedback statistics window and the phase distribution statistics, the direction of timing margin adjustment is dynamically determined, and the online switching of the current timing configuration is completed under transaction boundary conditions; During the calibration process, through the coordinated control of transaction scheduling and timing switching, measurement and configuration update operations are inserted without interrupting normal access, so that the NAND Flash control chip can complete multiple rounds of adaptive calibration and optimization during system operation, so as to achieve dynamic timing matching and performance reliability balance for NAND Flash particles of different processes, batches and life stages.

2. The dynamic timing adaptive adjustment method for NAND Flash controller chips according to claim 1, characterized in that, After the trigger calibration management enters the training state, it acquires the calibration context bound to the target NAND Flash chip. Under the condition of controlled transaction scheduling, it drives the delay sampling measurement to perform multiple sets of timing scan operations to obtain phase distribution statistics characterizing the actual physical transmission characteristics between the NAND Flash control chip and the target NAND Flash chip. The phase distribution statistics are then written into the calibration context, specifically including: After the calibration management is triggered to enter the training state, the training state is written into the calibration state register and the channel identifier, chip select identifier and operation type identifier corresponding to the target NAND Flash chip are locked. This enables the delayed sampling measurement to act on the physical link defined by the channel identifier and the chip select identifier. At the same time, the transaction scheduling is switched to the training protection mode and training protection parameters are generated to limit the bus free window into which training transactions can be inserted, limit the upper limit of parallelism, and prohibit long burst transmissions across windows. In the training protection mode, a calibration context bound to the target NAND Flash particle is allocated in the on-chip storage area, and the target particle identifier, training round identifier, current timing configuration identifier, measurement strategy identifier, and phase distribution statistics buffer are initialized in the calibration context; A scan set containing a command phase scan set and a data phase scan set is generated based on the measurement strategy identifier, and the scan set is mapped to multiple training transaction sequences so that each training transaction carries a unique scan index and loads the corresponding phase configuration at the transaction boundary; During the execution of each training transaction, consistency judgment is performed on the training readback results to form sampling result labels, and after repeated sampling reaches a preset threshold, the sampling result labels are robustly processed to generate phase distribution statistics; Based on the phase distribution statistics, a set of available segments is generated and the start index, end index and segment confidence status of consecutive available segments are marked; The phase distribution statistics, the set of available segments, and the environmental snapshot corresponding to the sampling process are written into the calibration context for subsequent timing configuration generation and online switching processing.

3. The dynamic timing adaptive adjustment method for NAND Flash controller chips according to claim 1, characterized in that, Based on the phase distribution statistics and combined with environmental and operational status information, the available sampling window and corresponding safety margin are determined to generate candidate timing configurations that match the current particle state. After completing the consistency verification, the candidate timing configurations are confirmed as the current timing configurations and sent to the programmable timing generation logic. Specifically, this includes: When generating the timing configuration matching the current particle state based on the phase distribution statistics, the timing calculation context is formed by reading the phase distribution statistics corresponding one-to-one with the target NAND Flash particles in the calibration context and synchronously binding the environmental state information and the running state information. In the time series calculation context, continuous available segment extraction and connectivity filtering are performed on the phase distribution statistics to determine the main window set, and sampling center parameters are determined in the main window set; The basic safety margin is determined based on the sampling center parameters and window boundaries, and the basic safety margin is compensated and corrected according to the environmental state information and the operating state information to generate safety margin parameters. The sampling center parameters and the safety margin parameters are mapped to candidate timing configurations and encapsulated into candidate timing configuration descriptors; Perform protocol consistency verification and handover consistency verification on the candidate timing configuration descriptor. If the verification passes, the candidate timing configuration descriptor is confirmed as the current timing configuration. Under transaction boundary conditions, the transaction scheduler sends a switching permission signal to the programmable timing generation logic, so that the programmable timing generation logic loads the current timing configuration and updates the phase control register and delay control register, so as to complete the online activation of the timing configuration without interrupting normal access.

4. The dynamic timing adaptive adjustment method for NAND Flash controller chips according to claim 1, characterized in that, The process of scheduling read, write, and erase transactions for the target NAND Flash chip according to the current timing configuration, and performing hardware-level statistics on error correction strength, error count, and retry count during transaction execution to form a feedback statistics window that is associated with the calibration context, specifically includes: When executing transaction scheduling based on the current timing configuration, the target granularity identifier, channel identifier, chip select identifier and operation type identifier are bound to the transaction descriptor in the transaction scheduling, and a channel timing mapping relationship is established between the transaction descriptor and the current timing configuration, so that read transactions, write transactions and erase transactions all load the current timing configuration consistent with their operation type identifier when entering the execution phase; During transaction execution, a statistical context corresponding to the channel identifier and the operation type identifier is established on the PHY interface side, and hardware-level sampling and accumulation are performed on the error correction strength, error count and retry count in the statistical context; When the preset window termination condition is met, the statistical context is windowed to form a feedback statistical window, which includes a summary of error correction intensity distribution, error count increment and retry count increment. The feedback statistics window and the current timing configuration corresponding to the generation of the feedback statistics window are written into the calibration context to keep the feedback statistics window consistent with the calibration context for subsequent timing margin adjustment and online switching determination.

5. The dynamic timing adaptive adjustment method for NAND Flash controller chips according to claim 1, characterized in that, The step of dynamically determining the timing margin adjustment direction based on the changes in the feedback statistics window and the phase distribution statistics, and completing the online switching of the current timing configuration under transaction boundary conditions, specifically includes: When determining the direction of timing margin adjustment based on the changes in the feedback statistics window and the phase distribution statistics, the alignment analysis of multiple consecutive feedback statistics windows is performed in the calibration context to generate feedback trend segments, and cross-round comparison is performed on the phase distribution statistics to generate window shrinkage markers, window drift markers and confidence reduction markers. A timing margin adjustment direction marker is generated based on the feedback trend segment, the window contraction marker, the window drift marker, and the confidence reduction marker. Based on the timing margin, adjust the direction marker to generate candidate timing configurations and encapsulate them into candidate timing configuration descriptors; Under transaction boundary conditions, perform a handover consistency check on the candidate timing configuration descriptors and generate handover plan entries; At the transaction boundary constrained by the switching plan entry, the transaction scheduler sends a switching permission signal to the programmable timing generation logic, so that the programmable timing generation logic loads the candidate timing configuration descriptor and atomically updates it to the current timing configuration; After the switch is completed, a switch effect marker is generated based on the subsequent feedback statistics window, and a rollback switch is executed when the preset rollback conditions are met, so as to realize closed-loop control of timing margin adjustment and online switching of the current timing configuration.

6. The dynamic timing adaptive adjustment method for NAND Flash controller chips according to claim 1, characterized in that, During the calibration process, through the coordinated control of transaction scheduling and timing switching, measurement and configuration update operations are inserted without interrupting normal access. This allows the NAND Flash control chip to complete multiple rounds of adaptive calibration and optimization during system operation, achieving dynamic timing matching and performance reliability balance for NAND Flash chips of different processes, batches, and life stages. Specifically, this includes: During the calibration process, the channel load status, queue depth status and transaction type distribution status in the transaction scheduling are monitored by calibration management to generate calibration insertion conditions, and transaction gaps are selected in the transaction queue as insertion points based on the calibration insertion conditions. At the insertion point, a calibration transaction carrying a measurement identifier or a configuration update identifier is inserted by the transaction scheduler, and the calibration transaction is kept bound to the calibration context. When a calibration transaction carrying a measurement identifier is executed, a delayed sampling measurement is triggered and the measurement result is written to the calibration context, while keeping the current timing configuration unchanged; When a calibration transaction carrying a configuration update identifier is executed, online switching preparation for candidate timing configurations is triggered, and the programmable timing generation logic completes the update of the current timing configuration when the transaction boundary conditions are met. After each calibration round is completed, the round identifier, current timing configuration identifier, and feedback statistics window summary in the calibration context are updated. Based on the updated status, the subsequent calibration insertion frequency, measurement range, and margin adjustment strategy are dynamically adjusted to complete multiple rounds of adaptive calibration and optimization without interrupting normal access, thereby achieving a dynamic balance between performance and reliability.

7. The dynamic timing adaptive adjustment method for NAND Flash controller chips according to claim 1, characterized in that, The method further includes: During continuous system operation, the calibration management constructs a time-series evolution trajectory for the same target NAND Flash particle based on the round identifier, historical timing configuration identifier, and corresponding feedback statistical window sequence recorded in the calibration context. The time-series evolution trajectory is then correlated with the current environmental state information and operating state information to generate an evolution state marker characterizing the timing stability of the particle. When the evolutionary state marker characterizes the temporal stability in a downward trend, the triggering priority of subsequent calibration insertion conditions is increased and the scanning range of delayed sampling measurement is expanded to enhance the ability to capture changes in physical transmission characteristics. When the evolutionary state marker characterizes the timing stability as being in a stable trend, the trigger frequency of the calibration insertion condition is reduced and the scan range of the delayed sampling measurement is narrowed to reduce calibration overhead and release access bandwidth. The timing margin adjustment step size is dynamically adjusted based on the evolution state marker, so that the dynamic timing adaptive adjustment method can form a self-learning calibration and optimization mechanism for the entire life cycle of the NAND Flash particles during long-term operation, so as to further improve the timing matching consistency and overall system reliability of NAND Flash particles under different processes, different batches and different life stages.

8. A dynamic timing adaptive adjustment device for a NAND Flash controller chip, characterized in that, The apparatus is used to execute the dynamic timing adaptive adjustment method for NAND Flash controller chips as described in any one of claims 1 to 7, the apparatus comprising an acquisition module and a processing module, wherein, The acquisition module is used to acquire the calibration context bound to the target NAND Flash chip after triggering the calibration management to enter the training state, and drive the delay sampling measurement to perform multiple sets of timing scan operations under the condition of controlled transaction scheduling, so as to acquire the phase distribution statistics characterizing the real physical transmission characteristics between the NAND Flash control chip and the target NAND Flash chip, and write the phase distribution statistics into the calibration context. The processing module is used to determine the available sampling window and corresponding safety margin based on the phase distribution statistics and combined with environmental state information and operating state information, so as to generate a candidate timing configuration that matches the current particle state, and after completing the consistency verification, confirm the candidate timing configuration as the current timing configuration and send it to the programmable timing generation logic. The processing module is also used to schedule read transactions, write transactions and erase transactions for the target NAND Flash chip according to the current timing configuration, and to perform hardware-level statistics on error correction strength, error count and retry count during the transaction execution process, forming a feedback statistics window and keeping it associated with the calibration context; The processing module is also used to dynamically determine the timing margin adjustment direction based on the changes in the feedback statistics window and the phase distribution statistics, and to complete the online switching of the current timing configuration under transaction boundary conditions; The processing module is also used to insert measurement and configuration update operations during the calibration process without interrupting normal access, through the coordinated control of transaction scheduling and timing switching. This enables the NAND Flash control chip to complete multiple rounds of adaptive calibration and optimization during system operation, thereby achieving dynamic timing matching and performance reliability balance for NAND Flash particles of different processes, batches, and life stages.

9. An electronic device, characterized in that, The electronic device includes a processor, a memory, a user interface, and a network interface. The memory is used to store instructions. The user interface and the network interface are both used to communicate with other devices. The processor is used to execute the instructions stored in the memory to cause the electronic device to perform the method as described in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores instructions that, when executed, perform the method as described in any one of claims 1 to 7.

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