Memory testing method, system, device and storage medium

Abstract

The present invention provides a memory testing method, system, device, and storage medium. The method includes: obtaining test input data based on the bit width of the memory to be tested; constructing test elements based on the test input data according to preset timing rules; and sequentially executing each test element on the memory to be tested; the preset timing rules satisfy the following conditions: after reading the previous address, writing the current address, the unit storage value corresponding to the previous address is not equal to the unit storage value corresponding to the current address, and the previous address and the current address are adjacent in both logical address sequence and physical address sequence. By adding test elements with insufficient timing margin, the present invention can prevent missed detection of the memory to be tested, thereby improving the test coverage of the memory testing method, increasing the qualified rate of produced memory, and reducing the user's losses caused by unqualified chips.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit technology, and in particular to a memory testing method, system, device and storage medium. Background Art

[0002] A Field Programmable Gate Array (FPGA) is a semi-customized integrated circuit consisting of programmable input and output units, programmable logic blocks, routing resources, and programmable dedicated memory modules. The dedicated programmable memory modules are used for storage within the chip. In actual applications, program code and related data are stored in the memory. This memory, which includes read-only memory (ROM) and random access memory (RAM), is an indispensable component of the chip in practical applications. Therefore, memory detection technology is one of the most fundamental security technologies to ensure its safety and reliability.

[0003] Currently, the most commonly used memory testing method is the memory built-in self-test (BIST). This method targets the memory and automatically generates a memory test circuit. By executing a specific test algorithm, it detects certain defects in the memory. Different test algorithms can achieve different memory test coverage. In the prior art, implementing the memory BIST method typically requires pre-programming a test algorithm module within the memory BIST circuit. Each algorithm module corresponds to a test algorithm. Upon receiving a test instruction, the memory test circuit generates a corresponding test algorithm based on the background data specified in the test instruction and the pre-stored algorithm module. This algorithm is then executed on the memory to detect defects.

[0004] Figure 1 This is a circuit diagram of a RAM memory test algorithm in a normal read / write mode in the prior art. Figure 1 As shown in the figure, ADDR[13:4] is the upper eight bits of the address, ADDR[3:0] represents the lower four bits of the address, Ckha / b, Cka / b, Pcka / b represent different clock signals, and WEA / B represents the write enable signal. In the design of the storage circuit test algorithm, although it involves testing of storage cells, address decoding, read-write drive circuits, etc., it rarely considers the control signal timing margin problem in the design. Therefore, the storage circuit test algorithm does not actually fully cover the circuit.

[0005] According to the design of the dedicated RAM module, in normal read and write mode, the output data of the port during writing is the storage value of the unit. However, when the timing margin on the control signal path is insufficient, the address increases, and the write enable signal jumps from 0 to 1. The output data of the port during writing is erroneous and becomes the unit storage value of the current address.

[0006] Therefore, insufficient timing margin will lead to write data errors, but existing memory testing algorithms for RAM modules cannot detect this problem of insufficient timing margin, which may cause RAM modules to be missed. When these problematic chips are used, they often cause huge losses to users. Summary of the Invention

[0007] The present invention provides a memory testing method, system, device and storage medium, the main purpose of which is to increase the detection of insufficient memory timing margin and effectively improve the qualified rate of memory products.

[0008] In a first aspect, an embodiment of the present invention provides a memory testing method, comprising:

[0009] Obtain test input data according to the bit width of the memory to be tested;

[0010] Constructing test elements according to the test input data and preset timing rules;

[0011] Executing each test element on the memory to be tested in sequence, and judging whether the memory to be tested is qualified according to the test results;

[0012] The preset timing rules meet the following conditions:

[0013] (1) after reading the previous address, the current address is written, (2) the unit storage value corresponding to the previous address is not equal to the unit storage value corresponding to the current address, (3) the previous address and the current address are adjacent in both logical address sequence and physical address sequence.

[0014] Preferably, constructing the test element according to the test input data and a preset timing rule includes:

[0015] Writing the test input data into the previous address, and after the writing is completed, performing a read operation on the previous address using the test input data as background data;

[0016] Writing opposite test data to the current address, and then performing a read operation on the current address using the opposite test data as background data, wherein the opposite test data is the inverse of the test input data;

[0017] If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified;

[0018] According to the ascending order of the address sequence, the current address is used as the previous address again, and the next address of the current address is used as the current address again. The above process is repeated until all addresses are detected.

[0019] Preferably, constructing the test element according to the test input data and a preset timing rule includes:

[0020] Writing the opposite test data into the previous address, and after the writing is completed, performing a read operation on the previous address using the opposite test data as background data;

[0021] Writing the test input data into the current address, and after the writing is completed, performing a read operation on the current address using the test input data as background data;

[0022] If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified;

[0023] According to the ascending order of the address sequence, the current address is used as the previous address again, and the next address of the current address is used as the current address again. The above process is repeated until all addresses are detected.

[0024] Preferably, constructing the test element according to the test input data and a preset timing rule further includes:

[0025] Writing the test input data into the previous address;

[0026] Writing the opposite test data into the current address;

[0027] If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified;

[0028] According to the ascending order of the address sequence, the current address is used as the previous address again, and the next address of the current address is used as the current address again. The above process is repeated until all addresses are detected.

[0029] Preferably, constructing the test element according to the test input data and a preset timing rule further includes:

[0030] Performing a read operation on the previous address using the test input data as background data;

[0031] performing a read operation on the current address using the opposite test data as background data;

[0032] If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified;

[0033] According to the descending order of the address sequence, the previous address is used as the current address again, and the previous address of the previous address is used as the current address again, and the above process is repeated until all addresses are detected.

[0034] Preferably, constructing the test element according to the test input data and a preset timing rule further includes:

[0035] Writing the opposite test data into the previous address, and after the writing is completed, performing a read operation on the previous address using the opposite test data as background data;

[0036] Writing the test input data into the current address, and after the writing is completed, performing a read operation on the current address using the test input data as background data;

[0037] If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified;

[0038] According to the descending order of the address sequence, the previous address is used as the current address again, and the previous address of the previous address is used as the current address again, and the above process is repeated until all addresses are detected.

[0039] Preferably, constructing the test element according to the test input data and a preset timing rule further includes:

[0040] Writing the test input data into the previous address, and after the writing is completed, performing a read operation on the previous address using the test input data as background data;

[0041] Writing opposite test data to the current address, and after writing is completed, performing a read operation on the current address using the opposite test data as background data;

[0042] If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified;

[0043] According to the descending order of the address sequence, the previous address is used as the current address again, and the previous address of the previous address is used as the current address again, and the above process is repeated until all addresses are detected.

[0044] In a second aspect, an embodiment of the present invention provides a memory testing system, including:

[0045] A calculation module, used for obtaining test input data according to the bit width of the memory to be tested;

[0046] A construction module, configured to construct a test element according to the test input data and a preset timing rule;

[0047] A test module, configured to sequentially execute various test elements on the memory to be tested, and determine whether the memory to be tested is qualified according to the test results;

[0048] The preset timing rules meet the following conditions:

[0049] (1) after reading the previous address, the current address is written, (2) the unit storage value corresponding to the previous address is not equal to the unit storage value corresponding to the current address, (3) the previous address and the current address are adjacent in both logical address sequence and physical address sequence.

[0050] In a third aspect, an embodiment of the present invention provides a computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of a memory testing method provided in the first aspect are implemented.

[0051] In a fourth aspect, an embodiment of the present invention provides a computer storage medium, wherein the computer storage medium stores a computer program, and when the computer program is executed by a processor, the steps of a memory testing method provided in the first aspect are implemented.

[0052] The present invention proposes a memory testing method, system, device and storage medium. Test elements are constructed according to preset timing rules, and the preset timing rules can trigger test situations when the timing margin is insufficient, thereby realizing testing of insufficient timing margin of the memory to be tested. By adding test elements with insufficient timing margin, missed detection of the memory to be tested can be prevented, thereby improving the test coverage of the memory testing method, improving the qualified rate of the produced memory, and reducing the user's losses caused by unqualified chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 This is a circuit diagram of a RAM memory test algorithm in normal read and write mode in the prior art;

[0054] Figure 2 This is a timing diagram in the common read / write mode in the prior art;

[0055] Figure 3 A flowchart of a memory testing method provided by an embodiment of the present invention;

[0056] Figure 4 A schematic structural diagram of a memory test system provided by an embodiment of the present invention;

[0057] Figure 5 The figure is a schematic structural diagram of a computer device provided in an embodiment of the present invention.

[0058] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0059] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0060] Figure 2 This is a timing diagram in the conventional read / write mode, such as Figure 2 As shown in the figure, Pckb and ckb both represent enable signals, ADDR[3:0] represents the lower four bits of the write address, WEB represents the write enable signal, Reb_n represents the read enable signal, and adrb[3:0] represents the lower four bits of the read address. Figure 2 For Figure 1 The timing diagram loaded by the circuit diagram shown in Figure 1 The circuit diagram shown is used for circuit simulation. After testing and simulation analysis, the place marked as ① in the figure represents the timing under correct circumstances. After WEB is pulled high, in write enable mode, the output sense amplifier is always turned off, and Reb_n controls adrb to maintain the previous cycle address, so the output data remains unchanged; the place marked as ② in the figure is the wrong timing. At this time, due to insufficient setup time of the Reb_n signal, the new address is adopted and output to the address first. Therefore, when WEB is high, the decoding circuit outputs the data corresponding to the new address, while under normal circumstances, it should output the data corresponding to the previous cycle address.

[0061] It can be found that the reason for insufficient timing margin is that the setup time from the Reb_n signal to the ckb signal is insufficient.

[0062] Supported by this theory, Figure 3A flow chart of a memory testing method provided by an embodiment of the present invention is as follows: Figure 3 As shown, the method includes:

[0063] S310, obtaining test input data according to the bit width of the memory to be tested;

[0064] S320, constructing a test element according to the test input data and a preset timing rule;

[0065] S330, executing each test element on the memory to be tested in sequence, and determining whether the memory to be tested is qualified according to the test results;

[0066] The preset timing rules meet the following conditions:

[0067] (1) after reading the previous address, the current address is written, (2) the unit storage value corresponding to the previous address is not equal to the unit storage value corresponding to the current address, (3) the previous address and the current address are adjacent in both logical address sequence and physical address sequence.

[0068] First, the bit width of the memory to be tested is obtained. The bit width of the memory refers to the number of bits representing the address. Different bit widths correspond to different test input data. In the specific implementation process, the built-in self-test algorithm of the memory can pre-specify background data. The test input data in the embodiment of the present invention can also be regarded as background data. The value of the background data is related to the bit width of the memory to be tested.

[0069] Then, based on the test input data and the previous result that "the reason for insufficient timing margin is insufficient setup time from the Reb_n signal to the ckb signal", the condition for insufficient excitation timing margin is:

[0070] (1) When accessing from the previous address to the current address, if the write enable signal is high, then the write enable signal jumps from 0 to 1, and the previous address is read first, and then the current address is written; if the write enable signal is low, then the write enable signal jumps from 1 to 0, and the previous address is read first, and then the current address is written;

[0071] (2) The cell storage value at the previous address is not equal to the cell storage value at the current address;

[0072] (3) The previous address and the current address are adjacent in both logical address sequence and physical address sequence.

[0073] Taking the process of accessing from the previous address to the current address as an example, in the specific implementation process, under normal circumstances, the previous address is accessed first. At this time, the write enable signal is in a valid state, then the output value corresponding to the previous address is read, and the read output value is stored in the unit memory corresponding to the previous address. The output value is the unit storage value corresponding to the previous address. Comparing the read value of the previous address with the unit storage value corresponding to the previous address, the two are equal.

[0074] If a timing margin shortage problem occurs, the address increases from the previous address to the current address, and the write enable signal is valid, then the output value of the current address is stored in the unit memory corresponding to the previous address. At this time, the read value of the previous address is compared with the unit storage value corresponding to the previous address. Since the read value of the previous address is the unit storage value corresponding to the current address, as long as the unit storage value corresponding to the current address is not equal to the unit storage value corresponding to the previous address, the timing margin shortage problem can be found.

[0075] Furthermore, in the process of accessing the current address from the previous address, the previous address and the current address are adjacent in the logical address order, so when programming, the previous address can be added or subtracted by 1 to get the current address; in addition, the previous address and the current address are also adjacent in the physical address order because the value of the corresponding address needs to be accessed.

[0076] Therefore, as long as the above three conditions are met, the trigger condition of insufficient timing margin can be triggered, and preset timing rules can be designed based on these three conditions to construct various test elements to detect the memory under test, so as to determine whether the memory under test has defects.

[0077] A memory testing method proposed in the present invention realizes testing of a memory to be tested with insufficient timing margin by constructing test elements according to preset timing rules, and the preset timing rules can stimulate testing situations when the timing margin is insufficient. By adding test elements with insufficient timing margin, missed detection of the memory to be tested can be prevented, thereby improving the test coverage of the memory testing method, improving the qualified rate of produced memories, and reducing the losses of users caused by unqualified chips.

[0078] Based on the above embodiment, preferably, constructing the test element according to the test input data and a preset timing rule includes:

[0079] Writing the test input data into the previous address, and after the writing is completed, performing a read operation on the previous address using the test input data as background data;

[0080] Writing opposite test data to the current address, and then performing a read operation on the current address using the opposite test data as background data, wherein the opposite test data is the inverse of the test input data;

[0081] If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified;

[0082] According to the ascending order of the address sequence, the current address is used as the previous address again, and the next address of the current address is used as the current address again. The above process is repeated until all addresses are detected.

[0083] Specifically, in the embodiment of the present invention, the test input data values ​​are different according to the different bit widths of the memory mode data. D is used to represent the test input data, and D' is used to represent the opposite test data. When the bit width of the memory to be tested is 1 bit, the value of D is 0, and the corresponding value of D' is 1; when the bit width of the memory to be tested is 16 bits, the value of D is 0000, and the corresponding value of D' is FFFF, the value of D is 5555, and the corresponding value of D' is AAAA, the value of D is 3333, and the corresponding value of D' is CCCC, the value of D is 0F0F, and the corresponding value of D' is F0F0, the value of D is 00FF, and the corresponding value of D' is FF00.

[0084] Take A0 as the previous address and A1 as the current address as an example. First, write D to A0. After the write operation is completed, read the previous address with D as the background data.

[0085] Then, the D' operation is written to the A1 address. After the writing is completed, the A1 address is read with D' as the background data. This satisfies the condition (1) of reading the previous address first and then writing the current address. Since the cell storage value of the previous address is D, and the cell storage value of the current address is D', the condition (2) is satisfied, and the condition (3) is also satisfied, which triggers the condition of insufficient timing margin. Based on whether the read value of the previous address and the cell storage value corresponding to the current address are equal, it is determined whether the memory to be tested is defective. In this way, the detection of insufficient timing margin of the A0 address and the A1 address is completed. Then, the values ​​of the previous address and the current address are changed in ascending order of the addresses, and the other addresses are continued to be tested in the same way.

[0086] This test element is the first test of the address. The test elements are:

[0087] For the previous address For the current address Indicates ascending order, w indicates write operation, and r indicates read operation.

[0088] Based on the above embodiment, preferably, constructing the test element according to the test input data and a preset timing rule includes:

[0089] Writing the opposite test data into the previous address, and after the writing is completed, performing a read operation on the previous address using the opposite test data as background data;

[0090] Writing the test input data into the current address, and after the writing is completed, performing a read operation on the current address using the test input data as background data;

[0091] If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified;

[0092] According to the ascending order of the address sequence, the current address is used as the previous address again, and the next address of the current address is used as the current address again. The above process is repeated until all addresses are detected.

[0093] First, write D' to A0. After the write operation is completed, read the previous address with D' as the background data.

[0094] Then, the D operation is written to the A1 address. After the writing is completed, the A1 address is read with D as the background data. Since it is an implementation plan connected to the above implementation process, the above conditions are met, which triggers the condition of insufficient timing margin. Based on whether the read value of the previous address and the unit storage value corresponding to the current address are equal, it is judged whether the memory to be tested is defective. In this way, the detection of insufficient timing margin of the A0 address and the A1 address is completed. Then, the values ​​of the previous address and the current address are changed in ascending order of the addresses, and the other addresses are continued to be tested in the same way.

[0095] This test element is a second test for the address. The test elements are:

[0096] For the previous address For the current address

[0097] Based on the above embodiment, preferably, constructing the test element according to the test input data and a preset timing rule further includes:

[0098] Writing the test input data into the previous address;

[0099] Writing the opposite test data into the current address;

[0100] If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified;

[0101] According to the ascending order of the address sequence, the current address is used as the previous address again, and the next address of the current address is used as the current address again. The above process is repeated until all addresses are detected.

[0102] First, the D operation is written to A0, and then the D' operation is written to the A1 address. Since it is connected on the basis of the above embodiment, the above conditions are met, which triggers the condition of insufficient timing margin. Based on whether the read value of the previous address and the unit storage value corresponding to the current address are equal, it is judged whether the memory to be tested is defective. In this way, the detection of insufficient timing margin of the A0 address and the A1 address is completed. Then, according to the ascending order of the addresses, the values ​​of the previous address and the current address are changed, and the other addresses are continued to be tested in the same way.

[0103] This test element is the third test for the address. The test elements are:

[0104] For the previous address For the current address

[0105] Based on the above embodiment, constructing the test element according to the test input data and the preset timing rule further includes:

[0106] Performing a read operation on the previous address using the test input data as background data;

[0107] performing a read operation on the current address using the opposite test data as background data;

[0108] If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified;

[0109] According to the descending order of the address sequence, the previous address is used as the current address again, and the previous address of the previous address is used as the current address again, and the above process is repeated until all addresses are detected.

[0110] Specifically, the embodiment of the present invention is described with A1 as the previous address and A2 as the current address. A read operation is first performed on A1 with D as the background data, and then a write operation D' is performed on the A2 address. Since it is connected on the basis of the above embodiment, the above conditions are met, thereby stimulating the condition of insufficient timing margin. Based on whether the read value of the previous address and the unit storage value corresponding to the current address are equal, it is determined whether the memory to be tested is defective. In this way, the detection of insufficient timing margin of the A1 address and the A2 address is completed. Then, the values ​​of the previous address and the current address are changed in descending order of the addresses, and the other addresses are continued to be tested in the same way as for the A0 address and the A1 address.

[0111] This test element is the fourth test for the address. The test elements are:

[0112] For the previous address For the current address Indicates descending order.

[0113] Based on the above embodiment, preferably, constructing the test element according to the test input data and a preset timing rule further includes:

[0114] Writing the opposite test data into the previous address, and after the writing is completed, performing a read operation on the previous address using the opposite test data as background data;

[0115] Writing the test input data into the current address, and after the writing is completed, performing a read operation on the current address using the test input data as background data;

[0116] If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory to be tested has a defect of insufficient timing margin;

[0117] According to the descending order of the address sequence, the previous address is used as the current address again, and the previous address of the previous address is used as the current address again, and the above process is repeated until all addresses are detected.

[0118] Specifically, the D' operation is first written to A1. After the write operation is completed, a read operation is performed with D' as the background data. Then, the D operation is written to the A2 address. After the write operation is completed, a read operation is performed with D as the background data. Since it is connected on the basis of the above embodiment, the above conditions are met, which triggers the condition of insufficient timing margin. Based on whether the read value of the previous address and the unit storage value corresponding to the current address are equal, it is determined whether the memory to be tested is defective. In this way, the detection of insufficient timing margin of the A1 address and the A2 address is completed. Then, the values ​​of the previous address and the current address are changed in descending order of the addresses. For the A0 address and the A1 address, the other addresses are continued to be tested in the same way.

[0119] This test element is the fifth test for the address. The test elements are:

[0120] For the previous address For current address

[0121] Based on the above embodiment, preferably, constructing the test element according to the test input data and a preset timing rule further includes:

[0122] Writing the test input data into the previous address, and after the writing is completed, performing a read operation on the previous address using the test input data as background data;

[0123] Writing opposite test data to the current address, and after writing is completed, performing a read operation on the current address using the opposite test data as background data;

[0124] If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified;

[0125] According to the descending order of the address sequence, the previous address is used as the current address again, and the previous address of the previous address is used as the current address again, and the above process is repeated until all addresses are detected.

[0126] Specifically, D is first written to A1. After the write operation is completed, a read operation is performed with D as the background data. Then, D' is written to the A2 address. After the write operation is completed, a read operation is performed with D' as the background data. Since it is connected on the basis of the above embodiment, the above conditions are met, which triggers the condition of insufficient timing margin. Based on whether the read value of the previous address and the unit storage value corresponding to the current address are equal, it is determined whether the memory to be tested is defective. In this way, the detection of insufficient timing margin of the A1 address and the A2 address is completed. Then, the values ​​of the previous address and the current address are changed in descending order of the addresses. For the A0 address and the A1 address, the other addresses are continued to be tested in the same way.

[0127] This test element is the sixth test for the address. The test elements are:

[0128] For the previous address For the current address

[0129] In summary, an embodiment of the present invention provides a memory testing method, which is specifically implemented as follows:

[0130] When L is an even number:

[0131] {

[0132]

[0133]

[0134]

[0135]

[0136]

[0137]

[0138] }

[0139] When L is an odd number,

[0140] {

[0141]

[0142]

[0143]

[0144]

[0145]

[0146]

[0147] }

[0148] Wherein, L represents the address.

[0149] For example, when L is 0, the address A0 is tested, and D is equal to 0 as an example:

[0150] {

[0151]

[0152]

[0153]

[0154]

[0155]

[0156]

[0157] }

[0158] Then L increases, that is, L is 1, and enters the program where L is 1

[0159] {

[0160]

[0161]

[0162]

[0163]

[0164]

[0165]

[0166] }

[0167] For the first line of code, in ascending order, write 0 to address A0 and read 0. For the first line of code when L is equal to 1, write 1 to address A1 and then read 1. This is accessing address A0 to A1. The write enable signal jumps from 0 to 1, and satisfies reading the previous address and writing the current address, satisfying the triggering condition (one); the unit storage value of address A0 is different from the unit storage value of address A1, that is, the read value of address A0 is different from the read value of address A1, satisfying the triggering condition (two); address A0 and address A1 are logically and physically continuous, and the lower four bits of address A0 and address A1 are different, satisfying the triggering condition (three); through these three conditions, the "insufficient timing margin" problem can be tested.

[0168] The embodiments of the present invention can detect the problem of insufficient timing margin in circuit design or manufacturing, and make up for the shortcomings of existing storage circuit testing algorithms.

[0169] Figure 4 A schematic diagram of the structure of a memory test system provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, the system includes a calculation module 410, a construction module 420 and a test module 430, wherein:

[0170] The calculation module 410 is used to obtain test input data according to the bit width of the memory to be tested;

[0171] The construction module 420 is used to construct test elements according to the test input data and preset timing rules;

[0172] The testing module 430 is used to sequentially execute various test elements on the memory to be tested, and determine whether the memory to be tested is qualified according to the test results;

[0173] The preset timing rules meet the following conditions:

[0174] (1) after reading the previous address, the current address is written, (2) the unit storage value corresponding to the previous address is not equal to the unit storage value corresponding to the current address, (3) the previous address and the current address are adjacent in both logical address sequence and physical address sequence.

[0175] This embodiment is a system embodiment corresponding to the above method embodiment. Its specific implementation process is the same as that of the above method embodiment. For details, please refer to the above method embodiment. This system embodiment will not be repeated here.

[0176] Each module in the aforementioned memory test system can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a computer device's memory in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0177] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device may be a server, and its internal structure diagram may be as follows: Figure 5 As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a computer storage medium and an internal memory. The computer storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the computer storage medium. The database of the computer device is used to store data generated or obtained during the execution of the memory testing method, such as test input data and test elements. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a memory testing method is implemented.

[0178] In one embodiment, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the memory testing method described in the above embodiment are implemented. Alternatively, when the processor executes the computer program, the functions of the modules / units described in the memory testing system embodiment are implemented.

[0179] In one embodiment, a computer storage medium is provided, which stores a computer program. When executed by a processor, the computer program implements the steps of the memory testing method described in the above embodiment. Alternatively, when executed by a processor, the computer program implements the functions of the modules / units of the memory testing system described in the above embodiment.

[0180] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0181] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0182] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A memory testing method, characterized in that: include: Obtain test input data according to the bit width of the memory to be tested; Constructing test elements according to the test input data and preset timing rules; Executing each test element on the memory to be tested in sequence, and judging whether the memory to be tested is qualified according to the test results; The preset timing rules meet the following conditions: (1) after reading the previous address, the current address is written; (2) the unit storage value corresponding to the previous address is not equal to the unit storage value corresponding to the current address; (3) the previous address and the current address are adjacent in both logical address sequence and physical address sequence; The step of constructing a test element according to the test input data and a preset timing rule includes: Writing the test input data into the previous address, and after the writing is completed, performing a read operation on the previous address using the test input data as background data; Writing opposite test data to the current address, and then performing a read operation on the current address using the opposite test data as background data, wherein the opposite test data is the inverse of the test input data; If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified; According to the ascending order of the address sequence, the current address is used as the previous address again, and the next address of the current address is used as the current address again. The above process is repeated until all addresses are detected.

2. The memory testing method according to claim 1, wherein: The step of constructing a test element according to the test input data and a preset timing rule includes: Writing the opposite test data into the previous address, and after the writing is completed, performing a read operation on the previous address using the opposite test data as background data; Writing the test input data into the current address, and after the writing is completed, performing a read operation on the current address using the test input data as background data; If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified; According to the ascending order of the address sequence, the current address is used as the previous address again, and the next address of the current address is used as the current address again. The above process is repeated until all addresses are detected.

3. The memory testing method according to claim 1, wherein: The constructing of test elements according to the test input data and preset timing rules further includes: Writing the test input data into the previous address; Writing the opposite test data into the current address; If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified; According to the ascending order of the address sequence, the current address is used as the previous address again, and the next address of the current address is used as the current address again. The above process is repeated until all addresses are detected.

4. The memory testing method according to claim 1, wherein: The constructing of test elements according to the test input data and preset timing rules further includes: Performing a read operation on the previous address using the test input data as background data; performing a read operation on the current address using the opposite test data as background data; If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified; According to the descending order of the address sequence, the previous address is used as the current address again, and the previous address of the previous address is used as the current address again, and the above process is repeated until all addresses are detected.

5. The memory testing method according to claim 1, wherein: The constructing of test elements according to the test input data and preset timing rules further includes: Writing the opposite test data into the previous address, and after the writing is completed, performing a read operation on the previous address using the opposite test data as background data; Writing the test input data into the current address, and after the writing is completed, performing a read operation on the current address using the test input data as background data; If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified; According to the descending order of the address sequence, the previous address is used as the current address again, and the previous address of the previous address is used as the current address again, and the above process is repeated until all addresses are detected.

6. The memory testing method according to claim 1, wherein: The constructing of test elements according to the test input data and preset timing rules further includes: Writing the test input data into the previous address, and after the writing is completed, performing a read operation on the previous address using the test input data as background data; Writing opposite test data to the current address, and after writing is completed, performing a read operation on the current address using the opposite test data as background data; If the read value of the previous address is equal to the unit storage value corresponding to the current address, it is determined that the memory under test has a defect of insufficient timing margin; otherwise, it is determined that the memory under test is qualified; According to the descending order of the address sequence, the previous address is used as the current address again, and the previous address of the previous address is used as the current address again, and the above process is repeated until all addresses are detected.

7. A memory testing system, the system being used to implement the memory testing method according to any one of claims 1 to 6, characterized in that: include: A calculation module, used for obtaining test input data according to the bit width of the memory to be tested; A construction module, configured to construct a test element according to the test input data and a preset timing rule; A test module, configured to sequentially execute various test elements on the memory to be tested, and determine whether the memory to be tested is qualified according to the test results; The preset timing rules meet the following conditions: (1) After reading the previous address, the current address is written, (2) the unit storage value corresponding to the previous address is not equal to the unit storage value corresponding to the current address, and (3) the previous address and the current address are adjacent in both logical address sequence and physical address sequence.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the memory testing method according to any one of claims 1 to 6 are implemented.

9. A computer storage medium storing a computer program, wherein: When the computer program is executed by a processor, the steps of the memory testing method according to any one of claims 1 to 6 are implemented.

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