Local interleaving time domain analog-to-digital converter adopting passive transmission technology

Abstract

The invention relates to a local interleaving time domain analog-to-digital converter adopting a passive transmission technology, which comprises a first-stage coarse quantization module and a second-stage coarse quantization module, wherein the first-stage coarse quantization module comprises a four-channel parallel 3bit Flash time-to-digital converter and is used for carrying out sampling and coarse quantization on an input signal to obtain a high bit code; the inter-stage time margin generation module is correspondingly connected with the four-channel parallel 3bit Flash time-to-digital converter and is switched to a lower pole plate of the capacitor array according to a high-order code so as to switch reference voltage, and an upper pole plate outputs a voltage margin signal; the voltage margin signal enters a second-stage VTC module and is converted into a time margin signal; the second-stage fine quantization module comprises a 6bit passive transmission line type time-to-digital converter, and performs fine quantization according to the time margin signal to obtain a low-order code; the digital decoder converts the high-order code and the low-order code into binary digital codes and outputs the binary digital codes. The invention provides a passive transmission technology, and the linearity of the VTC under a large-swing input signal is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of time-domain ADC, and particularly relates to a local interleaving time-domain analog-to-digital converter adopting a passive transmission technology. BACKGROUND

[0002] Medium-resolution (6-8 bits) high-speed analog-to-digital converters are the core part of high-speed data transmission systems. Due to excellent energy efficiency, time-interleaved successive approximation register analog-to-digital converters (TI SAR ADC) are generally considered as the first choice for design. However, due to the limitation of the sampling rate of sub-channel ADCs, a large number of channels are often interleaved, which brings a large amount of input capacitance and limits the input bandwidth. With the continuous progress of technology, time-domain ADCs that convert voltage-domain signals into time-domain signals through a voltage-to-time converter (VTC) and quantize the time-domain signals through a time-to-digital converter (TDC) are widely studied due to their highly digital circuit structure, which can better adapt to advanced processes. However, they still face the challenges of PVT (Process, Voltage, and Temperature) sensitivity and complex calibration techniques.

[0003] In recent years, voltage-time hybrid-domain ADCs have been proposed to combine the advantages of high robustness of voltage-domain ADCs and high sampling rate of time-domain ADCs. Although some recent works have demonstrated that they have better energy efficiency, they still face the challenge of input bandwidth limitation due to the large input capacitance of the SAR ADC front-end architecture. At the same time, the inherent problems of time-domain ADCs have not been solved in the above architecture, and the time quantization step is still very sensitive to PVT changes, so the demand for calibration schemes has not decreased. In addition, all voltage-domain ADCs face the challenge of reduced voltage swing margin with the continuous reduction of process feature size. SUMMARY

[0004] To solve the above problems in the prior art, the application provides a local interleaving time-domain analog-to-digital converter adopting a passive transmission technology. The technical problem to be solved by the application is solved through the following technical scheme: The application provides a local interwoven time domain analog-digital converter using passive transmission technology, comprising: a first-stage coarse quantization module, comprising four-channel parallel 3bit Flash time-digital converters, which are alternately controlled by four-phase non-overlapping sampling clocks to sample and coarsely quantize input signals to obtain high-bit codes; an inter-stage time margin generation module, which is connected to the four-channel parallel 3bit Flash time-digital converters and switches to the lower plate of a capacitor array to switch reference voltages according to the high-bit codes, and the upper plate outputs a voltage margin signal; the voltage margin signal enters a second-stage VTC module to convert the voltage margin signal into a time margin signal; a second-stage fine quantization module, comprising a 6bit passive transmission line time-digital converter, which is used to finely quantize the time margin signal to obtain low-bit codes; and a digital decoder, which is used to convert the high-bit codes and the low-bit codes into binary digital codes and output.

[0005] In an embodiment of the application, the first-stage quantization module adopts a local time domain interwoven architecture, and four-channel parallel 3bit Flash time-digital converters are alternately controlled by four-phase non-overlapping 4 GHz clocks to sample and quantize, and the sampling rate of each channel is 4 GS / s.

[0006] In an embodiment of the application, each 3bit Flash time-digital converter is connected with a passive transmission module, and two first-stage VTC modules are arranged between each passive transmission module and the 3bit Flash time-digital converter; the first-stage VTC modules are used to convert voltage signals into time signals; the passive transmission modules are used to reduce the swing of input signals of the first-stage VTC modules to improve the linearity thereof, and the swing of the inter-stage time margin generation module is kept unchanged.

[0007] In one embodiment of the present application, each passive transmission module comprises: a sampling switch tube M2, a sampling switch tube M4, a transmission switch tube M3, a transmission switch tube M6, a sampling capacitor C1, a sampling capacitor C3, a sharing capacitor C2 and a sharing capacitor C4, wherein the source of the sampling switch tube M2 is connected to the positive input end, the drain is connected to the upper plate of the sampling capacitor C1 and the source of the transmission switch tube M3 respectively; the source of the sampling switch tube M4 is connected to the negative input end, the drain is connected to the lower plate of the sampling capacitor C3 and the source of the transmission switch tube M6 respectively; the gates of the sampling switch tube M2 and the sampling switch tube M4 are connected to the first clock signal; the lower plates of the sampling capacitor C1 and the sampling capacitor C3 are connected to the ground; the drain of the transmission switch tube M3 is connected to the upper plate of the sharing capacitor C2 and the first input end of one of the first-stage VTC modules, and the second input end is connected to the reference level; the drain of the transmission switch tube M6 is connected to the lower plate of the sharing capacitor C4 and the first input end of the other first-stage VTC module, and the second input end is connected to the reference level; the gates of the transmission switch tube M3 and the transmission switch tube M6 are connected to the second clock signal; the lower plates of the sharing capacitor C2 and the sharing capacitor C4 are connected to the ground.

[0008] In one embodiment of the present application, the inter-stage time margin generation module comprises a CDAC capacitor array, which cascades the second-stage VTC module.

[0009] In one embodiment of the present application, the CDAC capacitor array adopts split capacitor array timing, and half of the capacitors are switched in each quantization period.

[0010] In one embodiment of the present application, the inter-stage time margin generation module further comprises a sampling capacitor, and a switch controlled by a clock is arranged between the CDAC capacitor array and the sampling capacitor, so that the signal sampled in the next period is kept on the sampling capacitor before the rising edge of the clock arrives, thereby prolonging the time for the first-stage coarse quantization module to perform quantization and the second-stage VTC module to perform conversion.

[0011] In one embodiment of the present application, the quantization process of the second-stage quantization module contains 1-bit redundant bit, which is used to correct the error of the previous stage.

[0012] Compared with the prior art, the present application has the following beneficial effects: The local interweaving time domain analog-digital converter of the application adopts a two-step TDC architecture, the first stage adopts local four-channel time domain interweaving, a single channel is a 3 bit 4 GS / s Flash interpolation type TDC, the second stage 6 bit passive transmission line TDC is multiplexed, and the voltage residual signal generated by the CDAC is amplified and converted into a time signal through VTC between stages, compared with the traditional architecture, no additional interstage amplifier is needed, which greatly saves the area, power consumption and design difficulty.

[0013] The application adopts a passive transmission line as a time quantization unit, compared with the traditional time domain ADC which depends on an active time quantization unit, the time quantization precision is only related to the characteristic parameters of the transmission line, the PVT robustness is greatly improved, and no additional calibration loop is needed.

[0014] The passive transmission technology proposed in the application is based on the principle of charge sharing, under the premise of not affecting the quantization of the subsequent stage, only the passive transmission between capacitors can realize the reduction of the VTC input signal swing, greatly improving the linearity of VTC under large swing input signal, and the swing finally reached can be controlled according to the size ratio of the sampling capacitor and the sharing capacitor, further increasing the degree of freedom in the design process, without increasing additional power consumption and design difficulty.

[0015] The above description is only a summary of the technical scheme of the application, in order to more clearly understand the technical means of the application, the content of the specification can be implemented, and in order to make the above and other purposes, characteristics and advantages of the application more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a structure diagram of a local interweaving time domain analog-digital converter adopting a passive transmission technology provided by the embodiment of the application; Figure 2 is a timing diagram of a local interweaving time domain analog-digital converter adopting a passive transmission technology provided by the embodiment of the application; Figure 3 is a structure diagram of a passive transmission technology provided by the embodiment of the application; Figure 4 is a working principle diagram of a voltage time converter provided by the embodiment of the application. DETAILED DESCRIPTION

[0017] In order to further illustrate the technical means and effects adopted by the application to achieve the predetermined invention purpose, the following combines the drawings and specific embodiments to specifically describe a local interweaving time domain analog-digital converter adopting a passive transmission technology according to the application.

[0018] The foregoing and other technical contents, features and effects of the present application can be clearly presented in the following detailed description of the embodiments with reference to the accompanying drawings. Through the description of the embodiments, the technical means and effects adopted by the present application to achieve the predetermined purposes can be more deeply and specifically understood. However, the accompanying drawings are provided for reference and illustration only, and are not intended to limit the technical solutions of the present application.

[0019] Embodiment one As Figure 1 shown, Figure 1 is a local interleaved time domain analog-to-digital converter architecture provided by an embodiment of the present application using passive transmission technology.

[0020] In the embodiment, a local interleaved time domain analog-to-digital converter using passive transmission technology comprises: a first-stage coarse quantization module including four-channel parallel 3bit Flash time-to-digital converters alternately controlled by four-phase non-overlapping sampling clocks to sample and coarsely quantize an input signal to obtain high-bit codes; an inter-stage time margin generation module corresponding to the four-channel parallel 3bit Flash time-to-digital converters, which switches the reference voltage by switching the lower plate of a capacitor array according to the high-bit codes, and outputs a voltage margin signal from the upper plate; the voltage margin signal enters a second-stage VTC module to convert the voltage margin signal into a time margin signal; a second-stage fine quantization module including a 6bit passive transmission line time-to-digital converter for fine quantization according to the time margin signal to obtain low-bit codes; and a digital decoder for converting the high-bit codes and the low-bit codes into binary digital codes and outputting the binary digital codes.

[0021] In an optional embodiment, the quantization process of the second-stage quantization module includes 1-bit redundant bits for correcting errors of the previous stage.

[0022] In an optional embodiment, the first-stage quantization module adopts a local time domain interleaved architecture, and four-channel parallel 3bit Flash time-to-digital converters are alternately controlled by four-phase non-overlapping 4 GHz clocks to sample and quantize, and the sampling rate of each channel is 4 GS / s.

[0023] For example, each 3bit Flash time-to-digital converter is connected with a passive transmission module, and two first-stage VTC modules are further arranged between each passive transmission module and the 3bit Flash time-to-digital converter; the first-stage VTC module is used to convert a voltage signal into a time signal; the passive transmission module is used to reduce the swing of the input signal of the first-stage VTC module to improve the linearity thereof, and the swing of the inter-stage time margin generation module remains unchanged.

[0024] Further, each passive transmission module comprises: a sampling switch tube M2, a sampling switch tube M4, a transmission switch tube M3, a transmission switch tube M6, a sampling capacitor C1, a sampling capacitor C3, a sharing capacitor C2 and a sharing capacitor C4, wherein the source of the sampling switch tube M2 is connected to the positive input end, the drain is connected to the upper plate of the sampling capacitor C1 and the source of the transmission switch tube M3 respectively; the source of the sampling switch tube M4 is connected to the negative input end, the drain is connected to the lower plate of the sampling capacitor C3 and the source of the transmission switch tube M6 respectively; the gates of the sampling switch tube M2 and the sampling switch tube M4 are connected to the first clock signal; the lower plates of the sampling capacitor C1 and the sampling capacitor C3 are grounded; the drain of the transmission switch tube M3 is connected to the upper plate of the sharing capacitor C2 and the first input end of one of the first-stage VTC modules, and the second input end is connected to the reference level; the drain of the transmission switch tube M6 is connected to the lower plate of the sharing capacitor C4 and the first input end of the other first-stage VTC module, and the second input end is connected to the reference level; the gates of the transmission switch tube M3 and the transmission switch tube M6 are connected to the second clock signal; and the lower plates of the sharing capacitor C2 and the sharing capacitor C4 are grounded.

[0025] In an optional embodiment, the inter-stage time margin generation module comprises a CDAC capacitor array cascaded with the second-stage VTC module, wherein the CDAC capacitor array adopts split capacitor array timing, and half of the capacitors are switched in each quantization period.

[0026] In an optional embodiment, the inter-stage time margin generation module further comprises a sampling capacitor, and a switch controlled by a clock is arranged between the CDAC capacitor array and the sampling capacitor, so that the signal sampled in the next period is maintained on the sampling capacitor before the rising edge of the clock arrives, so as to prolong the time for the first-stage coarse quantization module to quantize and the second-stage VTC module to convert.

[0027] The principle of the local interleaved time domain analog-to-digital converter of the embodiment adopting the passive transmission technology is that a two-step TDC architecture is adopted, and a fully differential structure is adopted to avoid the generation of even harmonics, improve the common mode noise suppression capability, and add a buffer to the input module to solve the problem of insufficient driving. The first-stage quantization module adopts time domain interleaving technology to improve the sampling rate, and the passive transmission line TDC of the second-stage quantization module is multiplexed to improve the resource utilization rate.

[0028] Specifically, the first-stage single-channel is divided into two paths. The quantization process is controlled by timing, with coarse quantization performed by a 3-bit Flash interpolation TDC to obtain the high-order digital code. This high-order digital code also serves as the input code for the other thermometer code capacitor array. By switching the corresponding analog signal on the lower plate of the capacitor, the margin voltage of the first stage can be obtained. To meet speed requirements, the first stage adopts a local time-domain interleaving architecture. A four-phase non-overlapping 4 GHz clock controls the four-channel Flash TDC to alternately sample and quantize. Each channel has a sampling rate of 4 GS / s, providing sufficient time for the single-channel time-domain ADC to complete quantization and switch the lower plate of the CDAC (Capacitor Digital-to-Analog Converter) to switch the reference voltage. The upper plate outputs the voltage margin. Here, the CDAC uses a split capacitor array timing, switching only half of the capacitors in each cycle, further improving speed. To minimize PVT stability, noise, and power consumption, and to avoid introducing gain errors and common-mode offset during op-amp design, no margin amplifiers are used between stages. Instead, the voltage margin is directly converted to a time margin via a high-linearity VTC. The time margin signal is then fed into a second-stage 6-bit TDC for low-order code value output. The passive transmission line-based TDC architecture enables fast quantization, resulting in a minimum quantization step size of less than 500 fs. Therefore, multiplexing the second stage with a first-stage four-channel TDC suffices, and the PVT of the delay unit exhibits high robustness due to the advantages of passive components. Finally, coarse and fine quantization are performed using the two TDC stages respectively to generate the corresponding thermometer code. This code is then converted to binary code by a digital decoder, ultimately yielding an 8-bit digital code.

[0029] It is worth noting that this invention uses TDC cascades to achieve performance requirements. A high-linearity VTC module converts the voltage margin into a time margin, which is then fed into the passive transmission line of the subsequent stage. Since no margin amplifier is used between stages, power consumption and area are reduced. Furthermore, a 1-bit redundancy is used in the second stage to correct for the effects of non-ideal factors such as offset, noise, and DAC setup errors in the preceding stage circuit, increasing additional fault tolerance and thus avoiding data overflow due to errors.

[0030] like Figure 2 As shown, Figure 2 This is a timing diagram of a partially interleaved time-domain analog-to-digital converter (ADC) using passive transmission technology provided in an embodiment of the present invention. For a single-channel sampling rate of 4 GS / s, 62.5 ps is allocated to sampling on the upper plate, and the remaining 187.5 ps is used for quantization. However, because the present invention adds a transmission gate switch in the first stage and divides the operation into upper and lower paths, and adds a clock signal between the CDAC and the sampling capacitor... The controlled switch makes the signal sampled in the next cycle arrive at the clock The rising edge arrives before the capacitor The rising edge arrives before the capacitor The rising edge arrives before the capacitor

[0031] As Figure 3 shown, Figure 3 is the architecture diagram of the passive transmission technology provided by the embodiment of the application.

[0032] VINP and VINN are large-amplitude differential input signals of an ADC system, M2 and M4 are sampling switch tubes, the on state of which is controlled by a clock CLKS, and a plurality of sampling switch tubes are connected to the upper plate of a P-end sampling capacitor C1 and the upper plate of an N-end sampling capacitor C3. For the N-end sampling capacitor C3, the upper plate thereof is also connected to VINP, VINN and the latter stage of the overall ADC system, and the lower plate is connected to an externally given reference voltage VREFH and VREFL (as actual and passive transmission technology are irrelevant, the figure does not show them). The upper plates of the capacitors C1 and C3 are also connected to the source end of a transmission tube M3 and a transmission tube M6, the on state of which is controlled by a CLKG, and the drain end thereof is connected to the upper plate of a sharing capacitor C2 and a sharing capacitor C4, and is also connected to one input end of a VTC, while the other input end of the VTC is connected to an externally input fixed reference voltage VREF, and the working state thereof is controlled by a CLKV. Through the architecture, the signal swing of the input end of the VTC can be reduced under the premise that the differential input signals VINN and VINP of the system are large-amplitude, so as to improve the linearity of the VTC.

[0033] As Figure 4 shown, Figure 4 is the working principle diagram of the voltage time converter provided by the embodiment of the application.

[0034] The specific working process of the passive transmission technology of the application is as follows: from Figure 3 the timing diagram, the waveform divided by the dashed line is one cycle, and from the timing diagram, it can be known that at the beginning of the cycle, CLKS jumps to high level first, at this time, CLKG and CLKV are low level, then M2 and M4 are turned on, M3 and M6 are turned off, M7 and M8 are turned on, and the sampling capacitor C1 and the sampling capacitor C3 are charged to the voltage of the input signal VINN and VINP respectively. Figure 4) turn off, at this time, the input signal VINP and the input signal VINN are transmitted to the upper plates of the sampling capacitors C1 and C3 through M2 and M4 respectively, and are transmitted to the upper plates of the capacitor arrays CDACP and CDACN at the PN end, at this time, the input signals on the capacitor arrays and the sampling capacitors are large swing. The second stage is when CLKS becomes low, CLKG becomes high, and CLKV remains low, M2 and M4 turn off, M3 and M6 turn on, M7 and M8 remain off, and VTC does not work. At this time, the input signals VINP and VINN transmitted to the upper plates of the capacitor arrays CDACP and CDACN in the last stage remain unchanged, and because M3 and M6 are turned on, the upper plates of the sampling capacitors C1, C3 and the sharing capacitors C2, C4 are connected through M3 and M6, and then charge sharing occurs, that is, part of the charges on the sampling capacitors C1 and C3 will be shared to the sharing capacitors C2 and C4, according to the relationship between charge and voltage, the voltage on the upper plates of the sampling capacitors C1 and C3 will be the same as that on the upper plates of the sharing capacitors C2 and C4, and lower than the voltage transmitted by M2 and M4 in the last stage, the specific value is determined by the capacitance ratio of the sampling capacitors C1, C3 and the sharing capacitors C2, C4. The third stage is that CLKV jumps to high, CLKS and CLKG become low, at this time, M2, M3, M4 and M6 turn off, M7 and M8 turn on, and VTC starts to work.

[0035] Please also refer to Figure 4 VINP_VTC and VINN_VTC in Figure 3 are the upper plates of the sharing capacitors C2 and C4 in , which are the VTC input signals with reduced swing after charge sharing in the last stage, when CLKV is high, M7 and M8 are turned on, VINP_VTC and VINN_VTC are discharged, which causes the voltage values on them to continuously decrease, when the decrease is below VREF, the rising edges of the outputs of the threshold detectors I1 and I2 from low to high are generated, and after passing through the buffers B1 and B2, the time signals TOUTP and TOUTN of the VTC output are obtained, and the working process of the entire architecture is completed. In this architecture, the turn-on of M3 and M6 causes the sampling capacitors and the sharing capacitors to share charges, which can reduce the swing of the VTC input signals VINP_VTC and VINN_VTC relative to VINP and VINN, so as to improve the linearity of VTC, but will not change the swing maintained on CDACP and CDACN, that is, will not affect the subsequent quantization of the later stage.

[0036] The local interweaving time domain analog-digital converter of the application employing passive transmission technology adopts two-step TDC architecture as a whole, the first stage adopts local four-channel time domain interweaving, the single channel is 3 bit 4 GS / s Flash interpolation type TDC, the second stage 6 bit passive transmission line TDC is multiplexed, and the voltage residual signal generated by CDAC is amplified and converted into a time signal through VTC directly between stages, compared with the traditional architecture, no additional interstage amplifier is needed, which greatly saves the area, power consumption and design difficulty.

[0037] The application adopts passive transmission line as a time quantization unit, compared with the traditional time domain ADC relying on active time quantization unit, the time quantization accuracy is only related to the characteristic parameters of the transmission line, which greatly improves the PVT robustness, and no additional calibration loop is needed.

[0038] The passive transmission technology proposed in the application is based on the principle of charge sharing, which can reduce the VTC input signal swing without affecting the quantization of the subsequent stage, greatly improve the linearity of VTC under large swing input signal, and the swing finally reached can be controlled according to the size ratio of sampling capacitor and sharing capacitor, further increase the degree of freedom in the design process, without increasing additional power consumption and design difficulty.

[0039] It should be noted that in this paper, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variant are intended to cover non-exclusive inclusion, so that the article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed. Without more limitation, the element defined by the statement "including a" does not exclude the presence of another identical element in the article or device including the element. The terms "connected" or "connected" and the like are not limited to physical or mechanical connection, but can include electrical connection, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right" and the like is based on the orientation or position relationship shown in the drawings, only for the convenience of describing the application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation to the application.

[0040] The above is further detailed description of the present application in combination with specific preferred embodiments, and cannot be deemed as limitation of the specific implementation of the present application to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, and all should be deemed as falling within the protection scope of the present application.

Claims

1. A partially interleaved time-domain analog-to-digital converter employing passive transmission technology, characterized in that, include: The first-stage coarse quantization module includes a four-channel parallel 3-bit Flash time-to-digital converter, which is controlled by four non-overlapping sampling clocks to sample and coarsely quantize the input signal to obtain the high-bit code. The interstage time margin generation module is connected to the four-channel parallel 3-bit Flash time-to-digital converter. It switches to the lower plate of the capacitor array according to the high-order code to switch the reference voltage, and the upper plate outputs a voltage margin signal. The voltage margin signal enters the second-stage VTC module, which converts the voltage margin signal into a time margin signal. The second-level fine quantization module includes a 6-bit passive transmission line time-to-digital converter, which is used to fine quantize the time margin signal to obtain the low-bit code. A digital decoder is used to convert the high-order bits and the low-order bits into binary digital codes and output them.

2. The partially interleaved time-domain analog-to-digital converter using passive transmission technology according to claim 1, characterized in that, The first-stage quantization module adopts a local time-domain interleaving architecture, which uses a four-phase non-overlapping 4 GHz clock to control four parallel 3-bit Flash time-to-digital converters to alternately sample and quantize, with each channel having a sampling rate of 4 GS / s.

3. The partially interleaved time-domain analog-to-digital converter using passive transmission technology according to claim 1, characterized in that, Each of the 3-bit Flash time-to-digital converters is connected to a passive transmission module, and two parallel first-stage VTC modules are also provided between each passive transmission module and the 3-bit Flash time-to-digital converter. The first-stage VTC module is used to convert the voltage signal into a time signal; the passive transmission module is used to reduce the swing of the input signal of the first-stage VTC module to improve its linearity, while keeping the swing of the inter-stage time margin generation module unchanged.

4. The partially interleaved time-domain analog-to-digital converter using passive transmission technology according to claim 3, characterized in that, Each of the passive transmission modules includes: sampling switch M2, sampling switch M4, transmission switch M3, transmission switch M6, sampling capacitor C1, sampling capacitor C3, sharing capacitor C2, and sharing capacitor C4, wherein, The source of the sampling switch M2 is connected to the non-inverting input terminal, and its drain is connected to the upper plate of the sampling capacitor C1 and the source of the transmission switch M3, respectively; the source of the sampling switch M4 is connected to the inverting input terminal, and its drain is connected to the lower plate of the sampling capacitor C3 and the source of the transmission switch M6, respectively; the gates of both the sampling switch M2 and the sampling switch M4 are connected to the first clock signal; the lower plates of both the sampling capacitor C1 and the sampling capacitor C3 are grounded; The drain of the transmission switch M3 is connected to the upper plate of the sharing capacitor C2 and to the first input terminal of one of the first-stage VTC modules, and its second input terminal is connected to a reference level; the drain of the transmission switch M6 is connected to the lower plate of the sharing capacitor C4 and to the first input terminal of another first-stage VTC module, and its second input terminal is connected to a reference level; the gates of both the transmission switch M3 and the transmission switch M6 are connected to a second clock signal; the lower plates of the sharing capacitor C2 and the sharing capacitor C4 are both grounded.

5. The partially interleaved time-domain analog-to-digital converter using passive transmission technology according to claim 1, characterized in that, The interstage time margin generation module includes a CDAC capacitor array, which is cascaded with a second-stage VTC module.

6. The partially interleaved time-domain analog-to-digital converter employing passive transmission technology according to claim 5, characterized in that, The CDAC capacitor array uses a split capacitor array timing, switching half of the capacitors in each quantization cycle.

7. The partially interleaved time-domain analog-to-digital converter using passive transmission technology according to claim 5, characterized in that, The inter-stage time margin generation module also includes a sampling capacitor, and a clock-controlled switch is provided between the CDAC capacitor array and the sampling capacitor. The signal sampled in the next cycle will be held on the sampling capacitor before the rising edge of the clock arrives, so as to extend the time for the first-stage coarse quantization module to perform quantization and the second-stage VTC module to perform conversion.

8. The partially interleaved time-domain analog-to-digital converter using passive transmission technology according to claim 1, characterized in that, The quantization process of the second-stage quantization module includes one redundant bit, which is used to correct the error of the previous stage.

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