A high-precision time-to-digital converter chip

Abstract

The application relates to the technical field of time measurement counting, and discloses a high-precision time-to-digital converter core, which comprises a delay phase-locked loop, a clock signal is input into the delay phase-locked loop to obtain a plurality of phase-split clock signals; an arbitrator, a to-be-measured signal and the phase-split clock signals are input into the arbitrator to perform first-stage time measurement and obtain first-stage quantization data; a time margin extraction circuit, the first-stage quantization data and the phase-split clock signals are input into the time margin extraction circuit, a time remaining part which cannot be measured in the first-stage time measurement is extracted, and a time start signal required by second-stage time measurement is obtained; a vernier chain, the time start signal and a time end signal are input into the vernier chain to perform second-stage time measurement, and second-stage quantization data obtained is quantization data output by the time-to-digital converter core. The high precision is achieved by breaking through the process limit, and the wide range characteristic is maintained; through later calibration, the linearity and the precision of the TDC can be further improved.

Description

Technical Field

[0001] This invention relates to the field of time measurement and counting technology, and specifically to a high-precision time-to-digital converter chip. Background Technology

[0002] A time-to-digital converter (TDC) is a device that converts the time information of a signal into digital information and outputs it. It can accurately measure time-related parameters such as time difference, pulse width, and phase difference between events, and is suitable for various applications requiring precise measurement of time events, including particle physics experiments, radar detection, and biomedical imaging. In particle physics experiments, a single particle generates an effective pulse after being captured by a detector in the detection area. By using multiple detectors and a time converter to measure the interval between these pulses, the particle's emission frequency and distribution data can be obtained. In the biomedical field, time-to-digital converters are widely used in time-of-flight detection. Time-of-flight technology uses a single-modulated infrared light source to illuminate a target object and acquires the required data by capturing the reflected light. A time-to-digital converter can accurately measure the time difference from the emission of the light source to the reception of the reflected light, ultimately generating a highly reliable distance image.

[0003] There are two main approaches to time-to-digital converters (TD-to-time converters): one is based on a Field-Programmable Gate Array (FPGA), and the other is a full-custom TD-to-time converter chip. The former relies on high-performance FPGAs and features low R&D costs, repeatable design, and short development cycles. Full-custom TD-to-time converter chips, on the other hand, require building the entire circuit from the transistor level, continuously verifying functionality and evaluating performance using simulation tools, and finally considering a tight and reasonable layout design. Although the manufacturing cycle is longer, it can achieve lower power consumption, lighter size, and higher accuracy. Currently, China lacks experience in designing full-custom TD-to-time converter chips, and there is still room for improvement in terms of accuracy, power consumption, and range.

[0004] Common design methods for full-custom time-to-digital converter (TD-DC) chips can be divided into time-to-digital converters based on delay chains and time-to-digital converters based on ring oscillators. The basic principle of a time-to-digital converter based on a delay chain is to let the start signal enter a chain circuit composed of multiple delay units, converting it into several signals with delay gradients. Then, the stop signal passes through an arbiter chain to time-discriminate these signals. Finally, the data output by the D flip-flop can express the phase information of the stop signal relative to the start signal, thus completing the conversion of time information to digital information. To overcome the limitations of process size, time-to-digital converters based on delay chains often employ a vernier structure, where the stop signal is also fed into the delay chain. This creates a situation where the two sets of signals from the two delay chains chase each other, achieving a higher precision measurement. However, the vernier chain structure increases power consumption, is extremely sensitive to power supply and other forms of noise, and significantly limits the measurement range. Therefore, how to develop a high-precision, wide-range full-custom time-to-digital converter chip is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a high-precision time-to-digital converter (TDC) chip that not only overcomes process limitations to achieve high precision but also maintains a wide measurement range. Furthermore, through subsequent calibration, the linearity and accuracy of the TDC can be further improved.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0007] A high-precision time-to-digital converter chip is used to quantize and calibrate the signal under test and output quantized data; it includes:

[0008] A time-delay phase-locked loop (PDL) is used to input a clock signal to obtain multiple phase clocks.

[0009] Arbitrator: The signal to be measured and the phase clock are input into the arbitrator to perform the first time period measurement and obtain the first quantized data;

[0010] The time margin extraction circuit inputs the first quantization data and the phase clock into the time margin extraction circuit, extracts the remaining time that could not be measured in the first period of measurement, and obtains the start signal required for the second period of measurement.

[0011] The vernier chain takes the signal under test and delays it by a fixed amount to obtain the stop signal, which is required for the second time measurement. The start signal and the stop signal are input into the vernier chain for the second time measurement. The start signal and the stop signal are input into two delay chains with different delays. The mismatch between the different delay chains is processed by the calibration module. The resulting second quantized data is the quantized data output by the time-to-digital converter chip.

[0012] Furthermore, the vernier chain is a 2-D vernier chain.

[0013] Furthermore, the delay phase-locked loop includes a frequency and phase detector, a charge pump, a linear filter, a bias module, and a first delay chain;

[0014] The clock signal is input to the frequency and phase detector and the first delay chain respectively; the output of the frequency and phase detector is connected to the input of the charge pump, the output of the charge pump is connected to the input of the linear filter, and the output of the linear filter is connected to the input of the bias module; the first delay chain includes N delay units; the output of the bias module is connected to the bias input of each delay unit; each delay unit outputs a clock signal, resulting in N phase clocks; the output of the end of the first delay chain is input to the frequency and phase detector.

[0015] Furthermore, there are N phase-split clocks; the arbiter includes two D flip-flop chains, namely a first D flip-flop chain and a second D flip-flop chain; the first D flip-flop chain includes N first D flip-flops, and the second D flip-flop chain includes N second D flip-flops; the N phase-split clocks are respectively input to the data input ports of the N first D flip-flops, and the signal under test is input to the clock signal input port of each first D flip-flop; the data output ports of the N first D flip-flops are respectively connected to the data input ports of the N second D flip-flops, and the signal under test is input to the clock signal input port of each second D flip-flop after a fixed delay. The first quantized data is output from the data output port of the second D flip-flops. The first quantized data is N bits of data, denoted as DFF. <n:1>.

[0016] Furthermore, the time margin extraction circuit includes N three-input NAND gates, and A level 1 AND-NOT gate, A level 2 or NOT gate, A level 3 AND-NOT gate, A level 4 or NOT gate, ... 2n-1 level NAND gates, A 2n-level NOR gate; n≥3, and 2 2n =N;

[0017] Alternatively, the time margin extraction circuit includes N three-input NAND gates, and A level 1 AND-NOT gate, A level 2 or NOT gate, A level 3 AND-NOT gate, A level 4 or NOT gate, ... 2n-1 level NAND gates, A 2n-level OR NOT gate, 2n+1 level NAND gates; n≥3, and 2 2n+1 =N;

[0018] The outputs of N three-input NAND gates are combined pairwise as... The input of each NAND gate is a level 1 NAND gate; the outputs of the previous NAND gate are combined in pairs to serve as the input of the next NOR gate, and the outputs of the previous NOR gate are combined in pairs to serve as the input of the next NAND gate, until only one output remains, which serves as the output of the entire time margin extraction circuit.

[0019] The inputs of the three-input NAND gate include the i-th phase clock CLK. The first quantized data DFF of the (i-1)th bit <i-1>and the first quantized data DFF of the i-th bit. The data obtained after passing through the inverter.

[0020] The above N can also be changed to M. N and M can be equal or not equal. M is the square of 2, and N must satisfy N<=M.

[0021] Furthermore, the vernier chain includes two delay chains with different delays and two calibration modules; the two delay chains are respectively referred to as the first delay chain and the second delay chain, and the two calibration modules are respectively referred to as the first calibration module and the second calibration module; the time start signal start enters the second delay chain, and the time stop signal stop enters the first delay chain; the input of the first calibration module is connected to the first control voltage VCtrl1, and the output is connected to the bias input terminal of each delay unit in the first delay chain; the input of the second calibration module is connected to the second control voltage VCtrl2, and the output is connected to the bias input terminal of each delay unit in the second delay chain.

[0022] Furthermore, the calibration module includes a bias section and a calibration section;

[0023] The first control voltage VCtrl1 and the second control voltage VCtrl2 are collectively referred to as the control voltage VCtrl;

[0024] The bias section includes PMOS transistors PM1, PM2, PM3 and PM4, and NMOS transistors NM1, NM2, NM3 and NM4;

[0025] The source of PMOS transistor PM1 is connected to the operating voltage VDD, the gate input bias voltage BiasN is connected to the gate of NMOS transistor NM4, and the drain is connected to the source of PMOS transistor PM2.

[0026] The gate of PMOS transistor PM2 is connected to the ground voltage VSS, and the drain is connected to the drain of NMOS transistor NM1.

[0027] The source of PMOS transistor PM3 is connected to the operating voltage VDD, the gate input bias voltage BiasP, and the drain is connected to the source of PMOS transistor PM4.

[0028] The gate of PMOS transistor PM4 is connected to the ground voltage VSS, and the drain is connected to the drain of NMOS transistor NM3.

[0029] The gate of NMOS transistor NM1 is connected to the operating voltage VDD, and the source is connected to the drain of NMOS transistor NM2; the gate of NMOS transistor NM2 is connected to the control voltage VCtrl, and the source is connected to the ground voltage VSS.

[0030] The gate of NMOS transistor NM3 is connected to the operating voltage VDD, and the source is connected to the drain of NMOS transistor NM4; the source of NMOS transistor NM4 is connected to the ground voltage VSS.

[0031] The calibration section includes PMOS transistors PM5, PM6, PM7, PM8 and PM9, and NMOS transistors NM5, NM6, NM7, NM8 and NM9;

[0032] The sources of PMOS transistors PM5, PM6, PM7, PM8, and PM9 are all connected to the operating voltage VDD, and their gates are connected to the first PMOS transistor digital control word DCW. <1> The second PMOS transistor digital control word DCW <2> The third PMOS transistor digital control word DCW <3> The fourth PMOS transistor digital control word DCW <5> The fifth PMOS transistor digital control word DCW <5> The drain is connected to the bias voltage BiasP; the width of PMOS transistors PM5, PM6, PM7, PM8 and PM9 is Wp, and the lengths are 16Lp, 8Lp, 4Lp, 2Lp and Lp, respectively.

[0033] The sources of NMOS transistors NM5, NM6, NM7, NM8, and NM9 are all connected to the ground voltage VSS, and their gates are connected to the first bit of the NMOS transistor digital control word N_DCW. <1> The second NMOS transistor digital control word N_DCW <2> The third NMOS transistor digital control word N_DCW <3> The fourth NMOS transistor digital control word N_DCW <5> The fifth NMOS transistor digital control word N_DCW <5> The drain is connected to the bias voltage BiasP; the width of NMOS transistors NM5, NM6, NM7, NM8 and NM9 is Wn, and the lengths are 16Ln, 8Ln, 4Ln, 2Ln and Ln, respectively.

[0034] Compared with the prior art, the beneficial technical effects of the present invention are:

[0035] This invention is a general-purpose time-to-digital converter that employs a two-stage quantization method, which effectively combines the advantages of each quantization stage. It maintains a high dynamic measurement range while achieving high precision, and also reduces design complexity.

[0036] This invention uses a 2-D vernier-type time-to-digital converter, which can expand the dynamic range of the second quantization stage without increasing the delay chain, reducing power consumption and area, and at the same time mitigating the impact of metastability problems in the first quantization stage to a certain extent.

[0037] The time margin extraction circuit used in this invention can accurately transfer the remaining time information of the first quantization to the next quantization. Furthermore, it employs a skip-level extraction method to alleviate the timing tension caused by path delay and setup time.

[0038] This invention introduces an additional calibration module into the delay chain of the vernier chain, which effectively solves the problem of delay chain mismatch caused by layout error. It can make minor adjustments to the delay chain externally, and then deduce the parameters that need to be adjusted through the measurement results, so that the time-to-digital converter can achieve better accuracy. Attached Figure Description

[0039] Figure 1 This is a block diagram of the quantization technology of the present invention;

[0040] Figure 2 This is a schematic diagram of the first quantization structure of the present invention;

[0041] Figure 3 This is a schematic diagram of the time margin extraction circuit of the present invention;

[0042] Figure 4 This is a timing diagram of the first stage of quantization and time margin extraction in this invention;

[0043] Figure 5 This is a schematic diagram of the second quantization structure (vernier chain) of the present invention;

[0044] Figure 6 This is a schematic diagram of the calibration module structure of the present invention;

[0045] Figure 7 This is a schematic diagram of the second quantization timing of the present invention. Detailed Implementation

[0046] A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

[0047] The high-precision 2-D vernier-type TDC chip with calibration function proposed in this invention includes an input module, a delay phase-locked loop, a calibration module, an arbitrator, a time margin extraction circuit, a vernier chain, and a post-processing digital module. All these units are integrated into an application-specific integrated circuit (ASIC) chip. From the perspective of signal transmission, the signal under test will undergo two measurement processes.

[0048] The first measurement period is completed using a time-delay chain tapping method. The clock signal forms a split-phase clock under the action of the time-delay phase-locked loop. After these clocks and the signal under test are arbitrated by the arbitrator, the quantized digital code of the first measurement period can be obtained, which is called the first quantization data.

[0049] After obtaining the first quantized data, these phase-split clocks and the first quantized data enter the time margin extraction circuit to extract the remaining time not measured in the first time period, obtaining the start signal (Start) required for the second time period measurement. The second time period measurement uses a 2-D vernier chain structure, consisting of two delay chains and three sets of arbitrators. The output of the arbitrators is the result of the second quantization. After the measurement is completed, the data from both quantizations are encoded and buffered in the post-processing digital module before being output to the outside of the chip.

[0050] During the time margin extraction process, the extraction circuit selects a clock offset by several sequence numbers from the current clock as the output result to mitigate the metastability of the previous measurement and to allow sufficient buffer time before the next measurement.

[0051] The calibration function is implemented in the delay chain during the second time interval measurement. This invention adds pull-up and pull-down transistor groups to the bias module of the delay chain; these transistors can be controlled by digital signals. By setting transistors with exponentially increasing sizes, the delay can be adjusted approximately linearly under digital signal control. This allows users to manually adjust the digital signal externally during later testing, resulting in better measurement accuracy.

[0052] Example

[0053] like Figure 1 As shown, the time-to-digital converter chip of this invention mainly includes an input module, a delay phase-locked loop (PLL), an arbitrator, a time margin extraction circuit, a 2-D vernier chain, and a post-processing digital module. The input module is a low-voltage differential signal (LVDS) receiver that converts externally input differential signals into single-ended signals. First, the clock signal CLK enters the PLL, where it is delayed to generate multiple phase-separated clocks with phase gradients. Then, the phase-separated clocks and the signal under test are time-discriminated by the arbitrator to obtain the first quantized data. After the first quantization, the first quantized data, along with the phase-separated clocks, enters the time margin extraction circuit to generate the start signal (Start) required by the 2-D vernier chain. The signal under test passes through a fixed delay circuit to generate the stop signal (Stop) required by the 2-D vernier chain. The start signal (Start) and the stop signal (Stop) carry the time margin from the first quantization and enter the 2-D vernier chain for the second quantization. The final quantization result is the effective output of the entire time-to-digital converter chip.

[0054] The time-delayed phase-locked loop used in the first stage of quantization, such as Figure 2 As shown. The delay-locked loop (PLL) consists of a phase detector (PFD), a charge pump (CP), a linear filter (LPF), a bias module, and a delay chain. By forming a feedback loop, it compares the phase of the input clock signal CLK with the clock returned from the delay chain, ultimately forming equally spaced phase clocks. After phase locking is completed, the delay between adjacent clocks is T. clk / N, where T clk CLK is the period of the clock signal, and N is the number of stages in the delay chain.

[0055] The arbitrator of this invention adopts the form of a D flip-flop (DFF). Figure 2 This design demonstrates a cascaded two flip-flops designed to circumvent the metastability issue of the first D flip-flop. By using a fixed-delayed test signal as the clock input to the second D flip-flop, it is ensured that the quantized data input to the time margin extraction circuit does not contain metastable signals.

[0056] The complete design of the time margin extraction circuit is as follows: Figure 3 As shown, its input consists of 32 phase clocks and 32 DFF data. The structure comprises multiple inverters, NAND gates, and NOR gates. By identifying the first quantized data of the input, it finds the position where the data transitions from 1 to 0, thus selecting the corresponding clock from the phase clocks. In the actual implementation, the time margin extraction circuit employs a skip-stage selection mechanism, that is, offsetting the sequence of the phase clocks by a fixed value at the input, thereby achieving the purpose of giving the output clock a fixed delay.

[0057] In the time margin extraction circuit, apart from the three-input NAND gate, all other NAND gates have two inputs and one output.

[0058] Figure 4 This demonstrates the digital timing sequence of the first quantization and time margin extraction. The CLK with sequence number i is shown. It is the phase clock that is ahead of and closest to the signal Hit being measured, meaning the delay between the two is Δ0, and Δ0 ≤ T. clk After the signal to be tested, Hit, arrives, the first D flip-flop chain generates quantized data DFF1. <n:1>The data bits above i are 0, and the rest are 1. The signal to be tested, Hit, reaches the second D flip-flop chain after a delay, generating quantized data DFF2. <n:1>Its data is similar to DFF1 <n:1>Same. DFF2 <n:1>After generation, the data enters the time margin extraction circuit. This circuit captures the position where 10 is generated in the input data (i.e., i), adds an offset k, and finally outputs the result along with CLK.<i+k> Clocks in phase. CLK<i+k> and CLK The time interval is T d_clk =k*T clk / N, to ensure that this value is greater than the sum of the setup time and path delay of the D trigger, the value of k needs to be chosen appropriately.

[0059] The second quantization structure adopts a 2-D vernier chain structure, such as... Figure 5 As shown, the Start signal and Stop signal enter two delay chains with different delays. The unit delay of the delay chain corresponding to Start is 11τ, while the unit delay of the delay chain corresponding to Stop is 10τ. These two 11-stage delay chains, under the discrimination of three interleaved DFF chains, form... Figure 5 The dynamic range is from -9τ to 21τ. The control voltages for these two delay chains are provided by two separate time-locked loops. To address the mismatch issue between different delay chains, this invention introduces an original calibration module, the structure of which is as follows: Figure 6 As shown. The basic function of the calibration module is the same as that of the bias module, both converting the control voltage Vctrl into bias voltages BiasN and BiasP. The difference is that the calibration module introduces incrementally sized PMOS and NMOS transistors for pull-up and pull-down at the BiasP terminal. This allows for fine-tuning of the BiasP value by adjusting the current through the BiasP terminal via digital signals, thereby achieving micro-adjustment of the delay time of the delay unit.

[0060] The left half of the calibration module is the bias section, which uses a diode-connected PMOS and NMOS transistor in series to form a bias structure. These two bias structures generate two bias signals, BiasN and BiasP, via Vctrl. The right half is the calibration section, integrating incrementally sized (W / L) PMOS and NMOS transistors to implement pull-up and pull-down operations at the BiasP terminal. This design allows for precise adjustment of the current flowing through the BiasP terminal via a Digital Control Word (DCW).

[0061] The timing sequence of the second quantization is as follows: Figure 7 As shown, Start and Stop are input to a w-stage delay chain, and the output of each delay unit is extracted to form Start_dl. <w:1>and Stop_dl <w:1>These are two separate-phase clock groups. In the design, Start_dl <1> Leading Stop_dl <1> However, because the unit delay of the Stop delay chain is less than the unit delay of the Start delay chain, the final Start_dl... <w>Lagging behind Stop_dl <w>This means that Start has been successfully caught up with Stop. During the catch-up process, the two phase clock groups are input to the arbitrator, and the measurement result of the vernier can be obtained. Figure 7 Medium, Data_A <w-1:1>It is Start_dl <w-1:1>and Stop_dl <w:2>The arbitration result, after encoding, corresponds to a quantization time of τ*(Data_A-w); Data_B <w:1>It is Start_dl <w:1>and Stop <w:1>The arbitration result, after encoding, corresponds to a quantization time of τ*Data_B; Data_C <w-1:1>It is Start_dl <w:2>and Stop <w-1:1>The arbitration result, after encoding, corresponds to a quantization time of τ*(Data_C+w). These three quantized data cover different measurement ranges and together constitute the effective output of the 2-D vernier chain, achieving effective coverage of the dynamic range and high-precision measurement.

[0062] The post-processing digital module encodes and buffers the data from the two quantizations before outputting it to the outside of the chip.

[0063] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention, and no reference numerals in the claims should be construed as limiting the scope of the claims.

[0064] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art. < / w> < / w>

Claims

1. A high-precision time-to-digital converter chip for quantizing and calibrating a signal to be measured and outputting quantized data; characterized in that, include: A time-delay phase-locked loop (PDL) is used to input a clock signal to obtain multiple phase clocks. The arbiter takes the signal under test and the phase clock as inputs to the arbiter for the first time period measurement to obtain the first quantized data; there are N phase clocks; the arbiter includes two D flip-flop chains, namely the first D flip-flop chain and the second D flip-flop chain. The first D flip-flop chain comprises N first D flip-flops, and the second D flip-flop chain comprises N second D flip-flops; N phase-splitting clocks are input to data input ports of the N first D flip-flops respectively, and the signal to be measured is input to clock signal input ports of the first D flip-flops; data output ports of the N first D flip-flops are connected with data input ports of the N second D flip-flops respectively, the signal to be measured is input to clock signal input ports of the second D flip-flops after fixed delay, and the first quantized data is output from data output ports of the second D flip-flops, wherein the first quantized data is N-bit data, denoted as ; The time margin extraction circuit receives the first quantization data and the phase-split clock input, extracts the remaining time that was not measured during the first measurement period, and obtains the start signal ("start") required for the second measurement period. The time margin extraction circuit includes N three-input NAND gates, and... A level 1 AND-NOT gate, A level 2 or NOT gate, A level 3 AND-NOT gate, A level 4 or NOT gate, ... 2n-1 level NAND gates, A 2n-level NOR gate; ,and ; Alternatively, the time margin extraction circuit includes N three-input NAND gates, and A level 1 AND-NOT gate, A level 2 or NOT gate, A level 3 AND-NOT gate, A level 4 or NOT gate, ... 2n-1 level NAND gates, A 2n-level OR NOT gate, 2n+1 level NAND gates; ,and The outputs of N three-input NAND gates are combined pairwise as... The three-input NAND gate has one input; the outputs of the previous NAND gate are combined in pairs as the inputs of the next NOR gate, and so on, until only one output remains, which serves as the output of the entire time margin extraction circuit; the inputs of the three-input NAND gate include the i-th phase clock. The first quantization data of the (i-1)th bit and the first quantized data of the i-th bit. The data obtained after passing through the inverter; The vernier chain takes the signal under test and delays it by a fixed amount to obtain the stop signal required for the second time measurement. The start signal and the stop signal are input into the vernier chain to perform the second time measurement. The start signal and the stop signal are input into two delay chains with different delays, and the mismatch between the different delay chains is processed by the calibration module. The resulting second quantized data is the quantized data output by the time-to-digital converter chip.

2. The high-precision time-to-digital converter chip according to claim 1, characterized in that, The vernier chain is a 2-D vernier chain.

3. The high-precision time-to-digital converter chip according to claim 1, characterized in that, The delay phase-locked loop includes a frequency and phase detector, a charge pump, a linear filter, a bias module, and a first delay chain; The clock signal is input to the frequency and phase detector and the first delay chain respectively; the output of the frequency and phase detector is connected to the input of the charge pump, the output of the charge pump is connected to the input of the linear filter, and the output of the linear filter is connected to the input of the bias module; the first delay chain includes N delay units; The output of the bias module is connected to the bias input of each delay unit; each delay unit outputs a clock signal to obtain N phase clocks; the output of the end of the first delay chain is input to the frequency and phase detector.

4. The high-precision time-to-digital converter chip according to claim 1, characterized in that, The vernier chain includes two delay chains with different delays and two calibration modules; the two delay chains are denoted as the first delay chain and the second delay chain, respectively, and the two calibration modules are denoted as the first calibration module and the second calibration module, respectively; the start signal (start) enters the second delay chain, and the stop signal (Stop) enters the first delay chain; the input of the first calibration module is connected to the first control voltage VCtrl1, and the output is connected to the bias input terminal of each delay unit in the first delay chain; the input of the second calibration module is connected to the second control voltage VCtrl2, and the output is connected to the bias input terminal of each delay unit in the second delay chain.

5. The high-precision time-to-digital converter chip according to claim 4, characterized in that, The calibration module includes a bias section and a calibration section; The first control voltage VCtrl1 and the second control voltage VCtrl2 are collectively referred to as the control voltage VCtrl; The bias section includes PMOS transistors PM1, PM2, PM3 and PM4, and NMOS transistors NM1, NM2, NM3 and NM4; The source of PMOS transistor PM1 is connected to the operating voltage VDD, the gate input bias voltage BiasN is connected to the gate of NMOS transistor NM4, and the drain is connected to the source of PMOS transistor PM2. The gate of PMOS transistor PM2 is connected to the ground voltage VSS, and the drain is connected to the drain of NMOS transistor NM1. The source of PMOS transistor PM3 is connected to the operating voltage VDD, the gate input bias voltage BiasP, and the drain is connected to the source of PMOS transistor PM4. The gate of PMOS transistor PM4 is connected to the ground voltage VSS, and the drain is connected to the drain of NMOS transistor NM3. The gate of NMOS transistor NM1 is connected to the operating voltage VDD, and the source is connected to the drain of NMOS transistor NM2. The gate of NMOS transistor NM2 is connected to the control voltage VCtrl, and the source is connected to the ground voltage VSS. The gate of NMOS transistor NM3 is connected to the operating voltage VDD, and the source is connected to the drain of NMOS transistor NM4. The source of NMOS transistor NM4 is connected to the ground voltage VSS. The calibration section includes PMOS transistors PM5, PM6, PM7, PM8 and PM9, and NMOS transistors NM5, NM6, NM7, NM8 and NM9; The sources of PMOS transistors PM5, PM6, PM7, PM8, and PM9 are all connected to the operating voltage VDD, and their gates are connected to the first PMOS transistor digital control word DCW. <1> The second PMOS transistor digital control word DCW <2> The third PMOS transistor digital control word DCW <3> The fourth PMOS transistor digital control word DCW <5> The fifth PMOS transistor digital control word DCW <5> The drain is connected to the bias voltage BiasP; the width of PMOS transistors PM5, PM6, PM7, PM8 and PM9 is Wp, and the lengths are 16Lp, 8Lp, 4Lp, 2Lp and Lp, respectively. The sources of NMOS transistors NM5, NM6, NM7, NM8, and NM9 are all connected to the ground voltage VSS, and their gates are connected to the first bit of the NMOS transistor digital control word N_DCW. <1> The second NMOS transistor digital control word N_DCW <2> The third NMOS transistor digital control word N_DCW <3> The fourth NMOS transistor digital control word N_DCW <5> The fifth NMOS transistor digital control word N_DCW <5> The drain is connected to the bias voltage BiasP; the width of NMOS transistors NM5, NM6, NM7, NM8 and NM9 is Wn, and the lengths are 16Ln, 8Ln, 4Ln, 2Ln and Ln, respectively.

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