High speed time-to-digital converter based on nested time amplification and auto-calibration technique

Abstract

The application relates to a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology, which comprises an N-stage TDC module, a pulse generator and a digital decoding module; two adjacent TDC modules are connected through the pulse generator to form an N-stage pipeline architecture; the quantization of each TDC module generates a temperature code which is input to the digital decoding module; the digital decoding module obtains a digital code Dout after decoding and processing the temperature code and outputs the digital code Dout; the first N-1 TDC modules are the same in structure and each comprises two low-bit sub-TDC modules connected in cascade; the Nth TDC module comprises two high-bit sub-TDC modules connected in cascade. The application uses an N-stage pipeline architecture, each stage of which comprises two-stage sub-TDC modules, avoids the use of a time margin amplifier, the two-stage sub-TDC modules automatically calibrate the aperture error, higher linearity is achieved, and the noise performance remains unchanged.

Description

Technical Field

[0001] The present invention belongs to the field of time-to-digital converters, and in particular relates to a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology. Background Art

[0002] Analog-to-digital converters (ADCs), the bridge between the analog and digital worlds, limit overall system performance. Time-domain ADCs (TDCs) are particularly well-suited for process adaptability, low power consumption, and a compact footprint. Continuous advancements in technology have led to improvements in the resolution and quantization range of time-to-digital converters (TDCs), enabling their successful application in a wide range of fields. This, in turn, places higher demands on TDC quantization speed, accuracy, and linearity. On-chip mismatch and in-band noise have become critical factors limiting TDC performance, and they cannot be ignored.

[0003] Because pipelined time-to-digital converters (TDCs) can quantize in parallel, they can operate in a multi-stage sub-TDC pipeline, achieving high quantization speeds. However, they typically use a time margin amplifier (TMA) between stages to transfer margin. As integrated circuit (IC) process nodes evolve to the nanometer level, issues such as intrinsic gain degradation of MOS transistors (MOS transistors) have led to the TMA gain becoming sensitive to variations in process, voltage, and temperature parameters. The introduction of TMA increases circuit complexity and power consumption. Furthermore, on-chip mismatch, manifested as aperture error in the gated delay chain formed by delay cells, has not been effectively limited. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, the present invention provides a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology. The technical problems to be solved by the present invention are achieved through the following technical solutions:

[0005] The present invention provides a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology, characterized in that it includes: an N-level TDC module, a pulse generator and a digital decoding module;

[0006] Two adjacent stages of the TDC modules are connected via the pulse generator to form an N-stage pipeline architecture, and the quantization output end of each stage of the TDC module is connected to the digital decoding module;

[0007] The first N-1 levels of TDC modules have the same structure, each including two cascaded low-order sub-TDC modules; the Nth level of TDC module includes two cascaded high-order sub-TDC modules; the low-order sub-TDC modules and the high-order sub-TDC modules have different quantization bits;

[0008] Each level of the TDC module quantizes the input time signal to generate a corresponding temperature code and a FULL signal. The pulse generator connected to it generates a time margin signal based on the difference between the FULL signal and the external trigger signal. The first-level TDC module receives the external time signal TIN and the external trigger signal at its input. The time margin signal generated by the previous-level pulse generator serves as the time signal input to the next-level TDC module. The temperature code generated by each level of the TDC module is input to the digital decoding module, which decodes the temperature code to obtain and output the digital code Dout.

[0009] In one embodiment of the present invention, the upper sub-TDC module and the lower sub-TDC module have the same structure, and the number of quantization bits of the upper sub-TDC module is 1 LSB higher than that of the lower sub-TDC module.

[0010] In one embodiment of the present invention, the low-order sub-TDC module includes: an OR gate R1, a switch S1, a switch S2, a switch S3, a D flip-flop DFF1, a D flip-flop DFF2, a delay unit t Q1 , delay unit t Q2 , delay unit t Q3 , delay unit t Q4 , delay unit t Q5 , delay unit t Q6 , delay unit t Q7 and delay unit t Q8 ;

[0011] The first input terminal of the OR gate R1 inputs the external trigger signal, the second input terminal inputs the time signal, and the output terminal of the OR gate R1 outputs the enable signal EN;

[0012] The delay unit t Q1 The delay unit t Q2 The delay unit t Q3 The delay unit t Q4 The delay unit t Q5 The delay unit t Q6 The delay unit t Q7 and the delay unit t Q8 The delay chains are connected in series in sequence, and the control terminals of the delay chains are connected to the output terminal of the OR gate R1;

[0013] The delay unit t Q1 Input the reset SET signal at the input terminal;

[0014] The first end of the switch S1 is connected to the delay unit t Q4 The output terminal and the delay unit tQ5 The first end of the switch S2 is connected to the input end of the delay unit t Q6 The output terminal and the delay unit t Q7 The first end of the switch S3 is connected to the delay unit t Q8 The output terminal;

[0015] The second end of the switch S1, the second end of the switch S2, and the second end of the switch S3 are connected and serve as the output end of the FULL signal;

[0016] The first input terminal of the D flip-flop DFF1 is connected to the delay unit t Q3 The output terminal and the delay unit t Q4 The first input terminal of the D flip-flop DFF2 is connected to the delay unit t Q5 The output terminal and the delay unit t Q6 The second input terminal of the D flip-flop DFF1 and the second input terminal of the D flip-flop DFF2 both input the clock signal CLK;

[0017] The output terminal of the D flip-flop DFF1 outputs a first temperature code D0 , and the output terminal of the D flip-flop DFF2 outputs a second temperature code D1 .

[0018] In one embodiment of the present invention, the time signal includes: a primary time signal T1 and a secondary time signal T2, and satisfies:

[0019] T2 = T1 + ΔT;

[0020] in, t Q is the delay time of a delay unit.

[0021] In one embodiment of the present invention, in the first N-1 stage TDC modules,

[0022] The first low-order sub-TDC module quantizes the input first-level time signal T1 and the external trigger signal to generate a first-level FULL signal;

[0023] The second low-order sub-TDC module quantizes the input secondary time signal T2 and the primary FULL signal to generate a secondary FULL signal, and inputs the secondary FULL signal as the FULL signal generated by the TDC module to the pulse generator.

[0024] In one embodiment of the present invention, the time margin signal includes: margin information of the first lower-order sub-TDC module and margin information of the second lower-order sub-TDC module;

[0025] The margin information of the first low-order sub-TDC module includes a first aperture error, and the margin information of the second low-order sub-TDC module includes a second aperture error;

[0026] The first aperture error and the second aperture error have opposite values ​​in sign.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The high-speed time-to-digital converter (TDC) based on nested time amplification and automatic calibration technology employs an N-stage pipeline architecture, with each stage comprising two sub-TDC modules. The output time margin signal carries margin information from both sub-TDC stages, eliminating the need for a time margin amplifier and effectively reducing circuit complexity and power consumption. Furthermore, using split calibration technology, the two sub-TDC modules automatically calibrate aperture error, achieving higher linearity while maintaining noise performance.

[0029] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 1 is a circuit block diagram of a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology provided by an embodiment of the present invention;

[0031] Figure 2 1.5-bit sub-TDC circuit diagram provided by an embodiment of the present invention;

[0032] Figure 3 is an equivalent schematic diagram of a delay unit in a holding phase according to an embodiment of the present invention;

[0033] Figure 4 1 is a potential schematic diagram of the positive and negative charge transition of the delay unit in the holding phase according to an embodiment of the present invention;

[0034] Figure 5 is a schematic diagram of aperture error according to an embodiment of the present invention;

[0035] Figure 6 2 is a schematic structural diagram of a TDC module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology proposed in accordance with the present invention, in conjunction with the accompanying drawings and specific embodiments.

[0037] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0038] Example 1

[0039] See Figure 1 , Figure 1 This is a circuit structure block diagram of a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology provided by an embodiment of the present invention.

[0040] As shown in the figure, the high-speed time-to-digital converter based on nested time amplification and automatic calibration technology of the present invention is characterized by including: N-stage TDC modules, pulse generators and digital decoding modules; two adjacent stages of TDC modules are connected through the pulse generator to form an N-stage pipeline architecture, and the quantization output end of each stage of the TDC module is connected to the digital decoding module.

[0041] In this embodiment, the first N-1 levels of TDC modules have the same structure, both including two cascaded low-order sub-TDC modules; the Nth level TDC module includes two cascaded high-order sub-TDC modules; the low-order sub-TDC modules and the high-order sub-TDC modules have different quantization bit numbers.

[0042] In this embodiment, each TDC module quantizes the input time signal to generate a corresponding temperature code and FULL signal. The pulse generator connected to it generates a time margin signal based on the difference between the FULL signal and the external trigger signal. The first-stage TDC module receives the external time signal TIN and the external trigger signal at its input. The time margin signal generated by the previous-stage pulse generator serves as the time signal input to the next-stage TDC module. The temperature code generated by each TDC module is input to a digital decoding module, which decodes the temperature code to obtain a digital code Dout and outputs it.

[0043] In an optional embodiment, the high-order sub-TDC module and the low-order sub-TDC module have the same structure, and the number of quantization bits of the high-order sub-TDC module is 1 LSB higher than that of the low-order sub-TDC module.

[0044] In an optional implementation, to achieve redundancy and avoid over-range of the output digital code, the first N-1 stages adopt a 1.5-bit cascade TDC structure, and the Nth stage TDC module adopts a 2-bit cascade TDC structure.

[0045] See Figure 2 , Figure 2 This is a circuit structure diagram of a 1.5-bit sub-TDC provided in an embodiment of the present invention.

[0046] As shown in the figure, taking the first-level 1.5-bit sub-TDC module as an example, it includes: OR gate R1, switch S1, switch S2, switch S3, D flip-flop DFF1, D flip-flop DFF2, delay unit t Q1 , delay unit t Q2 , delay unit t Q3 , delay unit t Q4 , delay unit t Q5 , delay unit t Q6 , delay unit t Q7 and delay unit t Q8 .

[0047] In an optional embodiment, the first input terminal of the OR gate R1 inputs an external trigger signal, the second input terminal inputs a time signal, and the output terminal of the OR gate R1 outputs an enable signal EN.

[0048] In an optional embodiment, the delay unit t Q1 , delay unit t Q2 , delay unit t Q3 , delay unit t Q4 , delay unit t Q5 , delay unit t Q6 , delay unit t Q7 and delay unit t Q8 The delay chains are connected in series in sequence, and their control terminals are connected to the output terminal of the OR gate R1; the delay unit t Q1 The input terminal inputs the reset SET signal.

[0049] In an optional embodiment, the first end of the switch S1 is connected to the delay unit t Q4 The output of the delay unit t Q5 The first end of the switch S2 is connected to the input end of the delay unit t Q6 The output of the delay unit t Q7 The first end of the switch S3 is connected to the delay unit t Q8 a second end of the switch S1, a second end of the switch S2 and a second end of the switch S3 are connected and serve as the output end of the FULL signal.

[0050] In an optional embodiment, the first input terminal of the D flip-flop DFF1 is connected to the delay unit t Q3 The output of the delay unit t Q4 The first input terminal of the D flip-flop DFF2 is connected to the delay unit t Q5 The output of the delay unit t Q6 The second input terminal of the D flip-flop DFF1 and the second input terminal of the D flip-flop DFF2 both input the clock signal CLK; the output terminal of the D flip-flop DFF1 outputs the first temperature code D0, and the output terminal of the D flip-flop DFF2 outputs the second temperature code D1. The digital decoding module decodes the temperature code to obtain a digital code Dout and outputs it.

[0051] In an optional embodiment, the corresponding output relationship between the temperature code and the digital code of this level is shown in Table 1, wherein, according to the first temperature code D0 and the second temperature code D1, a digital code of up to 10 is generated in the digital decoding module to meet the quantization range requirements.

[0052] Table 1 Correspondence between temperature code and digital code of this level

[0053] D1 D0 Dout L L 00 L H 01 H H 10

[0054] Please refer to Figure 3 and Figure 4 , Figure 3 is an equivalent schematic diagram of a delay unit in a holding phase according to an embodiment of the present invention; Figure 4 3 is a potential schematic diagram of the positive and negative charge transition of the delay unit in the holding phase according to an embodiment of the present invention.

[0055] As shown in the figure, when the enable signal EN is low, the delay chain is in the hold stage, that is, the delay unit keeps the current information unchanged; the switch S0 is equivalent to a resistor, and the resistor R inv The current on the resistor R is zero. inv The potential difference across the capacitor is zero; this means that the p and capacitor C d The charge flows through the resistor R inv redistribute to ensure that the resistance R inv The potentials at both ends are equal. Depending on the direction of charge transition, the capacitance C p and capacitor C d The level on the electrode increases or decreases accordingly, that is, the charge transition is positive or negative.

[0056] Furthermore, since the delay chain is affected by the clock signal CLK feedthrough during the hold phase, the clock signal CLK feeds through the parasitic capacitance to the output end, causing the held potential to be unstable, and charge transitions will also occur at the output end of the delay unit, causing the output voltage to change. The charge transition varies with the held potential, and this error is called aperture error.

[0057] See Figure 5 , Figure 5 Schematic diagram of aperture error according to an embodiment of the present invention.

[0058] As shown in the figure, the solid line represents the output of the delay unit under ideal conditions (Original FULL), and the dotted line represents the output of the delay unit under actual conditions due to the existence of charge transitions (Actual FULL). After the enable signal EN becomes high, the switch tube is turned on, but the charge that has already transitioned will not return to the position before the transition occurs. This causes the phase information to change, resulting in an error in the time required for the potential to drop to GND. Moreover, this error is nonlinear. The voltage change caused by the transition is related to the phase during the hold period, that is, it is related to the input. It is not a fixed value and cannot be calibrated as a static offset. The direction and number of charge transitions in the hold phase are related to the phase of the hold phase. If the influence of noise is not considered, each phase corresponds to an aperture error. Therefore, this is a nonlinear error related to the input and is difficult to adjust through a simple first-order calibration. The aperture error causes a time error T between Actual FULL and Original FULL, which can be positive or negative. skew , after the error is introduced, the output time margin can be given by the following formula:

[0059] T IDEA res =(T Actual FULL -T Trigger )-T skew ; (1)

[0060] Among them, T IDEA res is the time margin signal under ideal conditions; T Actual FULL is the FULL signal in actual situation; T Trigger is the external Trigger signal in actual situation; (T Actual FULL -T Trigger ) is the time margin signal in actual situation, that is, T Actual res ;T skew is the time error.

[0061] See Figure 6 , Figure 6 2 is a schematic structural diagram of a TDC module according to an embodiment of the present invention.

[0062] Due to T skew It is related to the input and is not a fixed value. It is a nonlinear error. IDEA res This produces a complex effect, and therefore needs to be calibrated using the split TDC of this embodiment, that is, using two cascaded sub-TDC modules.

[0063] In this embodiment, the time signals input to the TDC module include: a primary time signal T1 and a secondary time signal T2, and satisfy:

[0064] T2=T1+ΔT; (2)

[0065] in, t Q is the delay time of a delay unit.

[0066] As shown in the figure, taking the first N-1-level TDC module as an example, the first low-order sub-TDC module quantizes the input primary time signal T1 and the external trigger signal to generate a primary FULL signal; the second low-order sub-TDC module quantizes the input secondary time signal T2 and the primary FULL signal to generate a secondary FULL signal, and inputs the secondary FULL signal as the FULL signal generated by the TDC module into the pulse generator.

[0067] In one optional embodiment, the time margin signal includes margin information for a first low-order sub-TDC module and margin information for a second low-order sub-TDC module; the margin information for the first low-order sub-TDC module includes a first aperture error, and the margin information for the second low-order sub-TDC module includes a second aperture error. After quantization, the delay chains in the two low-order sub-TDC modules maintain phase states uniformly distributed within a delay unit. The first and second aperture errors have opposite sign and similar absolute values, meaning that the effects of the control error are partially offset, weakening the impact of the aperture error and achieving higher linearity while maintaining noise performance.

[0068] It is worth noting that since the time margin signal Tout already includes the margin information of the first low-order sub-TDC module and the margin information of the second low-order sub-TDC module, there is no need to use a time margin amplifier to transfer margins between stages, reducing circuit complexity and power consumption.

[0069] The high-speed time-to-digital converter (TDC) based on nested time amplification and automatic calibration technology in this embodiment of the present invention utilizes an N-stage pipeline architecture, with each stage comprising two sub-TDC modules. The output time margin signal carries margin information from both sub-TDC stages, eliminating the need for a time margin amplifier and effectively reducing circuit complexity and power consumption. Furthermore, using split calibration technology, the two sub-TDC modules automatically calibrate aperture error, achieving higher linearity while maintaining noise performance.

[0070] It should be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device comprising the element. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. References to orientations or positional relationships, such as "upper," "lower," "left," and "right," are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the description of the present invention. They do not indicate or imply that the device or element referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present invention.

[0071] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A high-speed time-to-digital converter based on nested time amplification and automatic calibration technology, characterized in that: include: N-level TDC module, pulse generator and digital decoding module; Two adjacent stages of the TDC modules are connected via the pulse generator to form an N-stage pipeline architecture, and the quantization output end of each stage of the TDC module is connected to the digital decoding module; The first N-1 levels of TDC modules have the same structure, each including two cascaded low-order sub-TDC modules; the Nth level of TDC module includes two cascaded high-order sub-TDC modules; the low-order sub-TDC modules and the high-order sub-TDC modules have different quantization bits; Each level of the TDC module quantizes the input time signal to generate a corresponding temperature code and a FULL signal. The pulse generator connected to it generates a time margin signal based on the difference between the FULL signal and the external trigger signal. The first-level TDC module receives the external time signal TIN and the external trigger signal at its input. The time margin signal generated by the previous-level pulse generator serves as the time signal input to the next-level TDC module. The temperature code generated by each level of the TDC module is input to the digital decoding module, which decodes the temperature code to obtain and output the digital code Dout.

2. The high-speed time-to-digital converter based on nested time amplification and automatic calibration technology according to claim 1, characterized in that: The high-order sub-TDC module and the low-order sub-TDC module have the same structure, and the number of quantization bits of the high-order sub-TDC module is 1 LSB higher than that of the low-order sub-TDC module.

3. The high-speed time-to-digital converter based on nested time amplification and automatic calibration technology according to claim 1, characterized in that: The low-order sub-TDC module includes: an OR gate R1, a switch S1, a switch S2, a switch S3, a D flip-flop DFF1, a D flip-flop DFF2, a delay unit t Q1 , delay unit t Q2 , delay unit t Q3 , delay unit t Q4 , delay unit t Q5 , delay unit t Q6 , delay unit t Q7 and delay unit t Q8 ; The first input terminal of the OR gate R1 inputs the external trigger signal, and the second input terminal inputs the time signal. For the first-stage TDC module, the time signal is the external time signal. For the first N-1-stage TDC modules except the first-stage TDC module, the time signal is the time margin signal generated by the previous-stage pulse generator. The output end of the OR gate R1 outputs an enable signal EN; The delay unit t Q1 The delay unit t Q2 The delay unit t Q3 The delay unit t Q4 The delay unit t Q5 The delay unit t Q6 The delay unit t Q7 and the delay unit t Q8 The delay chains are connected in series in sequence, and the control terminals of the delay chains are connected to the output terminal of the OR gate R1; The delay unit t Q1 Input the reset SET signal at the input terminal; The first end of the switch S1 is connected to the delay unit t Q4 The output terminal and the delay unit t Q5 The first end of the switch S2 is connected to the input end of the delay unit t Q6 The output terminal and the delay unit t Q7 The first end of the switch S3 is connected to the delay unit t Q8 The output terminal; The second end of the switch S1, the second end of the switch S2, and the second end of the switch S3 are connected and serve as the output end of the FULL signal; The first input terminal of the D flip-flop DFF1 is connected to the delay unit t Q3 The output terminal and the delay unit t Q4 The first input terminal of the D flip-flop DFF2 is connected to the delay unit t Q5 The output terminal and the delay unit t Q6 The second input terminal of the D flip-flop DFF1 and the second input terminal of the D flip-flop DFF2 both input the clock signal CLK; The output terminal of the D flip-flop DFF1 outputs a first temperature code D0 , and the output terminal of the D flip-flop DFF2 outputs a second temperature code D1 .

4. The high-speed time-to-digital converter based on nested time amplification and automatic calibration technology according to claim 3, characterized in that: The time signal includes: a first-level time signal and secondary time signals , and satisfy: ； in, , is the delay time of a delay unit; the first-level time signal is the time signal input to the first low-order sub-TDC module; the secondary time signal It is the time signal input to the second low-order sub-TDC module.

5. The high-speed time-to-digital converter based on nested time amplification and automatic calibration technology according to claim 4, characterized in that: In the first N-1 level TDC modules, The first low-order sub-TDC module receives the first-level time signal and the external Trigger signal, quantizing to generate a first-level FULL signal; The second low-order sub-TDC module receives the secondary time signal The first-level FULL signal is quantized to generate a second-level FULL signal, and the second-level FULL signal is input to the pulse generator as the FULL signal generated by the TDC module.

6. The high-speed time-to-digital converter based on nested time amplification and automatic calibration technology according to claim 5, characterized in that: The time margin signal includes: margin information of the first lower sub-TDC module and margin information of the second lower sub-TDC module; The margin information of the first low-order sub-TDC module includes a first aperture error, and the margin information of the second low-order sub-TDC module includes a second aperture error; The first aperture error and the second aperture error have opposite values ​​in sign.

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