Half-cycle time sequence repairing method and system of circuit delay locked storage device

Abstract

The invention discloses a half-cycle time sequence repairing method and system of a circuit delay locked storage device. The method comprises the following steps: detecting whether installation time violation or holding time violation exists in the digital circuit design or not; when the time sequence violation exists and cannot be conventionally repaired, verifying whether the time sequence margin of the violation path meets a calling condition or not; if yes, part of clock cycle time is called through the barrier-free passing characteristic of the circuit delay lock storage device in the high-level stationary circuit period, and half-cycle cycle time calling repair based on the circuit delay lock storage device is carried out on a violation path, specifically, for installation time violation, an end device is replaced; for holding time violation, a reverse trigger device is inserted. Through the half-cycle period time calling and differentiation strategy, the technical bottleneck of a traditional method is broken through, and a final solution is provided for time sequence violation which cannot be repaired by a conventional method in an extreme design environment.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more specifically to a method and system for half-cycle timing repair of circuit delay-locked memory devices. Background Technology

[0002] In the field of digital integrated circuit design, timing convergence is a key technical challenge to ensure the correct functioning of chips. As semiconductor process nodes continue to shrink to the nanometer scale, circuit operating frequencies increase significantly, leading to a dramatic increase in the number and complexity of timing violation paths. Signal transmission is affected by multiple physical effects, including interconnect delays, clock skew, and process variations, making it highly susceptible to installation timing violations and hold-time violations. Traditional timing repair methods primarily rely on engineering change instructions, such as inserting delay buffers to adjust path delays, or enhancing the driving capability of preceding cells to improve signal transmission characteristics.

[0003] However, in complex scenarios such as high-frequency circuit design and multi-clock domain interaction, these conventional techniques exhibit significant limitations. Buffer insertion incurs additional overhead in terms of area and power consumption; drive capability adjustment is limited by the inherent specifications of the standard cell library; and clock signal deviations in asynchronous timing violation paths are difficult to completely eliminate using conventional placement and routing methods. Especially when the violation path contains multiple logic gates or long interconnects, the time window for the data signal to reach the flip-flop input port may not meet the installation time requirements, i.e., the data signal needs to remain stable before the clock's effective edge, or the holding time requirement, i.e., the data signal needs to be maintained for a sufficient duration after the clock's effective edge.

[0004] While existing technologies, such as patent CN109583103B, attempt to alleviate timing issues through various structural optimization schemes, they still lack efficient and non-intrusive repair methods for extreme violation paths. In extreme design environments, when the original design cannot guarantee that the transmitted data signal meets the installation or holding time requirements under various conditions, unexpected anomalies may occur in the signal response speed and functionality of the entire design. Specifically, due to the presence of signal buffering devices, inverted signal output devices, and other signal interaction devices, the data signal to be transmitted may not meet the installation or holding time requirements at the input port of the trigger (circuit timing signal capture device) at the end of the timing path during propagation. Summary of the Invention

[0005] This invention provides a half-cycle timing repair method for circuit delay-locked memory devices, which solves the problem that conventional engineering change instructions cannot repair installation time or holding time violations in extreme scenarios, resulting in chip timing non-convergence.

[0006] This invention is achieved through the following technical solution:

[0007] In a first aspect, this application provides a half-cycle timing repair method for a circuit delay-locked memory device, comprising the following steps:

[0008] Detect whether there are timing violations in digital circuit design, wherein the timing violations are installation time violations or holding time violations that violate the constraints of the digital circuit standard cell library;

[0009] When the timing violation exists and cannot be repaired by regular engineering change instructions, verify whether the timing margin of the violation path meets the calling conditions.

[0010] If satisfied, the circuit is invoked to delay and lock a portion of the clock cycle time of the storage device, and the violation path is repaired according to the timing violation type:

[0011] For installation time violations, the circuit timing signal capture device at the end of the violation path is replaced with the circuit delay lock storage device.

[0012] For holding time violations, the circuit delay lock storage device triggered by the reverse signal drive is inserted into the violation path.

[0013] A further optimization scheme is that whether the timing margin of the verification violation path meets the calling conditions includes:

[0014] For installation time violations, verify whether the installation time margin of the timing signal triggering device of the subsequent path is sufficient to cover the installation time violation amount of the current path.

[0015] For holding time violations, verify whether the installation time margin of the circuit timing signal capture device for the violation path is greater than or equal to the holding time violation amount.

[0016] A further optimization is to reduce the maximum call time of the partial clock cycle to approximately half a clock cycle.

[0017] A further optimization is that the method further includes:

[0018] After completing the violation path reconstruction, verify whether the installation time and holding time of the circuit delay lock storage device itself meet the constraint requirements of the digital circuit standard cell library.

[0019] A further optimization scheme is that the routine engineering change instructions include at least one of the following: unit drive capability adjustment, buffer insertion, and logic optimization.

[0020] A further optimization is that the method is preferentially applicable to asynchronous clock domain circuit designs.

[0021] Secondly, this application provides a circuit delay-locked memory device for implementing the half-cycle timing repair method of the circuit delay-locked memory device as described above, comprising:

[0022] The signal detection module is used to identify unobstructed passage time windows during high-level smooth circuits;

[0023] The time call module is used to calculate and call a portion of the clock cycle time;

[0024] The path reconstruction module is used to perform device replacement or insertion operations based on the timing violation type.

[0025] A further optimization is that the maximum number of time calls for the time call module is limited by the device's own installation time and holding time requirements.

[0026] Thirdly, this application provides a half-cycle timing repair system for a circuit delay-locked memory device, comprising:

[0027] The timing analysis unit is used to detect whether there are installation timing violations or holding time violations in digital circuit designs that violate the constraints of the digital circuit standard cell library;

[0028] The routine repair unit is communicatively connected to the timing analysis unit and is used to prioritize the execution of routine engineering change instructions for detected timing violations;

[0029] The circuit-delayed latching storage device as described above;

[0030] The control unit is communicatively connected to the conventional repair unit and is used to activate the circuit delay lock storage device to perform a half-cycle time call repair for timing violations when the conventional repair unit fails to meet the timing constraint requirements.

[0031] Further optimizations include:

[0032] The verification unit is used to perform formal and temporal verification on the repaired violation paths.

[0033] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0034] By leveraging the unobstructed passage characteristics of memory devices during high-level stable circuitry, a portion of the clock cycle time is allocated to specifically repair violation paths of timing violations that cannot be conventionally corrected: for mounting timing violations, a device replacement strategy is employed; for holding timing violations, a device triggered by a reverse-signal driven device is inserted. This semi-cyclic cycle time call mechanism overcomes the technical bottlenecks of traditional methods, satisfying the timing constraints of the digital circuit standard cell library without large-scale circuit modifications. It significantly improves the timing convergence success rate in complex scenarios such as high-frequency and asynchronous clock domains, providing key technical support for chip back-end design. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0036] In the attached diagram:

[0037] Figure 1 Schematic diagram for circuit delay locking of storage device half-cycle time call;

[0038] Figure 2 A flowchart of a half-cycle timing repair method for a circuit delay-locked memory device provided in an embodiment of this application;

[0039] Figure 3 Another flowchart of the half-cycle timing repair method for the circuit delay-locked storage device provided in the embodiments of this application;

[0040] Figure 4 A flowchart illustrating the half-cycle time call of the circuit delay-locked storage device provided in this application embodiment. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0042] In digital integrated circuit design, data signals need to remain stable for a period of time before the effective clock edge (installation time) and then for a period of time afterward (holding time) to meet timing constraints. However, the interaction of buffers, inverters, and other logic units along the signal transmission path introduces delays, which may cause the data signal to fail to meet the timing requirements of the flip-flop within the given time window, thus triggering timing violations. Under extreme design conditions, conventional engineering change instructions (such as buffer insertion, cell size adjustment, etc.) may not be effective in correcting such violations. Especially in asynchronous clock domain circuit design, when the clock signals of the timing signal triggering device and the timing signal capturing device are asynchronous, the clock deviation between the two is difficult to control, resulting in a large delay difference between the flip-flop clock signal and the capturing device clock signal. This makes it very easy for the holding time constraint of the data signal at the capturing device to be unmet.

[0043] The core of this application lies in utilizing the unobstructed passage characteristic during the high-level smooth circuitry unique to circuit delay-locked memory devices. This device provides a unique unobstructed signal passage window during the duration of the high-level smooth circuitry. This characteristic allows it to call up a portion of the clock cycle time (the maximum call is less than half a clock cycle) to grant additional setup or hold time margin for data signals; this mechanism is called half-cycle time calling. The circuit delay-locked memory device itself is also constrained by setup and hold times. Therefore, when calling up time to correct violations on other paths, it is essential to ensure that the device's own timing requirements are met.

[0044] like Figure 1 The diagram shows the principle of half-cycle time recall for the circuit delay-locked storage device. This diagram intuitively illustrates the relationship between the unobstructed passage time window (② actual recall time) and its theoretical maximum value (① maximum recall time) during a high-level smooth circuit.

[0045] Based on this principle, this method aims to utilize a high-level stable circuit window to provide a stable transmission channel for data signals, and by allocating a portion of the clock cycle time, to gain additional timing margin for the data signals in order to correct violation paths. For example... Figure 2 and Figure 3 As shown, this application provides a half-cycle timing repair method for a circuit delay-locked memory device, comprising the following steps:

[0046] Step S1: Detect whether there are timing violations in the digital circuit design. The timing violations are installation time violations or holding time violations that violate the constraints of the digital circuit standard cell library. More specifically, the digital circuit design is comprehensively detected by timing analysis tools to identify installation time violations or holding time violations that violate the constraints of the digital circuit standard cell library and generate a detailed violation analysis report.

[0047] Step S2: Based on the violation analysis report, when the timing violation is detected, conventional engineering change instructions are used to repair the violation first; if conventional repair can make the circuit design with timing violation meet the timing constraints, the entire repair process ends.

[0048] Step S3: When the timing violation exists and cannot be repaired by regular engineering change instructions, verify whether the timing margin of the violation path meets the calling conditions; wherein, the violation path is the path where the timing violation exists;

[0049] Step S4: If satisfied, the circuit is invoked to delay and lock a portion of the clock cycle time of the storage device, and the violation path is repaired according to the timing violation type;

[0050] Step S5: After completing the special repair, run the timing analysis again to verify the timing constraints. If the verification is successful, the repair process ends successfully; if the requirements are still not met, the circuit design or specifications need to be substantially modified.

[0051] This embodiment effectively controls chip area and power consumption by prioritizing routine repair of timing violations with high efficiency and low overhead. When faced with extreme timing violations that cannot be resolved by conventional methods, the process enters a special repair phase. Utilizing the unique physical characteristics of circuit delay-locked memory devices, it achieves fine-grained clock cycle timing, providing a new technical means to solve timing bottlenecks in complex scenarios such as high-frequency circuits and asynchronous clock domains. Finally, through verification and iterative closed-loop processing, the reliability of the repair results is ensured, forming a complete technical chain from detection and graded repair to final verification. This provides a highly reliable and successful timing convergence solution for high-end chip design, improving circuit design efficiency and reducing subsequent risks.

[0052] In one embodiment, step S1: detecting whether there are timing violations in the digital circuit design, wherein the timing violation is an installation time violation or a holding time violation that violates the constraints of the digital circuit standard cell library, specifically implemented as follows:

[0053] A comprehensive inspection of digital circuit design is performed using timing analysis tools. All signal paths are scanned in depth to identify those with installation time violations or holding time violations. In other words, it is confirmed that the delay results of the violation paths do not meet the installation time or holding time constraints in the standard cell library of digital circuits.

[0054] After completing the path scanning and identification, a detailed violation analysis report is generated. The report must clearly indicate the specific type of each violation path, whether it is an installation time violation or a holding time violation, and accurately quantify the severity of each violation, i.e., the number of violations, to provide a data foundation for the subsequent implementation of a graded repair strategy.

[0055] In one embodiment, step S2: Based on the violation analysis report, when a timing violation is detected, conventional engineering change instructions are preferentially used to repair the violation; if conventional repair can make the circuit design with the timing violation meet the timing constraints, the entire repair process ends, specifically implemented as follows:

[0056] When a timing violation is detected through step S1, timing repair is first performed using conventional engineering change instructions. Specific methods include, but are not limited to: cell drive capability adjustment (such as the size_cell command), buffer insertion (such as the insert_buf command), logic reorganization and optimization.

[0057] If conventional repair methods can enable the circuit design with timing violations to meet the timing constraints of the digital circuit standard cell library, the entire hierarchical repair strategy can be executed at this stage without needing to use subsequent, more complex special repair methods for circuit delay-locked memory devices.

[0058] In one embodiment, step S3, when a timing violation exists and cannot be repaired by conventional engineering change instructions, verifies whether the timing margin of the violation path meets the calling conditions, specifically includes the following steps:

[0059] Step S31: Locate the circuit timing signal capture device in the violation path based on the timing violation report;

[0060] Step S32A: For installation time violations, based on the verification results of the installation time margin of the circuit timing signal triggering device of the subsequent path, different timing repair strategies are executed;

[0061] Step S32B: For holding time violations, based on the verification results of the installation time margin of the circuit timing signal triggering device of the violation path, different timing repair strategies are executed.

[0062] This embodiment establishes a screening and decision-making mechanism through violation path localization and targeted verification strategies. This ensures that subsequent calls to the circuit delay-locked memory device are safe and effective, fundamentally avoiding secondary timing risks caused by blind repairs. By strictly distinguishing the verification conditions for installation time violations and holding time violations, and associating them with the margin of subsequent paths and the margin of the current device, guidance for repair behavior is achieved. This provides a crucial prerequisite for the successful implementation of the critical operation of half-cycle time calls, improving the success rate of extreme timing violation repairs and circuit reliability.

[0063] In one embodiment, when using a circuit delay-locked storage device to repair installation time violations, the installation time window of the subsequent triggering device is reduced. Therefore, it is necessary to ensure that the installation time margin of the subsequent path is sufficient to offset the call time. Step S32A: For installation time violations, based on the verification result of the installation time margin of the circuit timing signal triggering device of the subsequent path, different timing repair strategies are executed, specifically including the following steps:

[0064] Confirm whether the installation time margin of the circuit timing signal triggering device in the subsequent path originating from the circuit timing signal capture device is sufficient;

[0065] If sufficient, i.e., the installation time margin of the subsequent trigger is greater than or equal to the installation time violation of the current path, then the subsequent half-cycle time call method using the circuit delay to lock the storage device is executed.

[0066] If insufficient, the subsequent use of circuit delay to lock the storage device half-cycle time call method will not be executed, and the design or pattern will be modified to meet the installation time constraints in the digital circuit standard unit library.

[0067] This embodiment ensures that the installation time margin of the subsequent paths is sufficient to accommodate the time offset that may be introduced due to the delay in locking the storage device by calling the circuit before repairing the current path. This ensures that the repair of the current violation will not come at the expense of the timing integrity of the downstream paths, fundamentally guaranteeing the feasibility of the semi-cyclic time call operation and the overall timing stability of the system, and avoiding the blindness of the repair behavior.

[0068] The principle behind this embodiment of using circuit delay to lock the storage device's half-cycle time to recall and repair the installation time is as follows:

[0069] When the installation time of a circuit timing signal capture device cannot meet the installation time constraints of the digital circuit standard unit library, and it cannot be achieved through normal means, sufficient redundancy must be ensured in the installation time of the next-level circuit timing signal capture device. This redundancy must be at least equal to the required time. Only in this way can the circuit timing signal capture device with installation time violations be replaced with a circuit delay-locked storage device. Utilizing the characteristic of the circuit delay-locked storage device to pass through high-level stable circuits without obstacles, at most half a cycle time can be called from the circuit trigger signal to ensure that the installation time meets the constraints of the digital circuit standard unit library. If the installation time redundancy of the next-level circuit timing signal capture device is less than the required time, when using this patent to repair the installation time, the next-level circuit timing signal capture device will not meet the installation time constraints because the previous-level circuit timing signal capture device has called up part of the time, and the next-level circuit timing signal capture device does not have enough redundancy to meet the current circuit timing signal capture device's constraints of the digital circuit standard unit library.

[0070] In one embodiment, step S32B: For holding time violations, based on the verification result of the installation time margin of the circuit timing signal triggering device of the violation path, different timing repair strategies are executed, specifically including the following steps:

[0071] Confirm whether the installation time margin of the circuit timing signal triggering device for the violation path is sufficient;

[0072] If sufficient, i.e., the current hold time margin of the trigger is greater than or equal to the hold time violation amount, the half-cycle time call method of the circuit delay locking memory device can be used.

[0073] If this is insufficient, the design or style needs to be modified to meet the holding time constraints in the digital circuit standard cell library.

[0074] The principle behind this embodiment of using circuit delay to lock the storage device's half-cycle time to repair the holding time is as follows:

[0075] When the hold time of a circuit timing signal capture device cannot meet the hold time constraints in the digital circuit standard unit library, especially when the signals of the circuit timing signal capture device and the capture device are asynchronous trigger signals, the delay deviation between the trigger signal and the capture signal is difficult to reduce, resulting in a large delay difference between the trigger signal and the capture signal. This makes it easy for the hold time of the circuit timing signal capture device to fail to meet the hold time constraints in the digital circuit standard unit library. When this happens and conventional engineering change instructions cannot make it meet the hold time constraints in the digital circuit standard unit library, provided that there is sufficient margin in the installation time of the circuit timing signal capture device, a circuit delay lock storage device triggered by a reverse signal drive device can be inserted in the middle of the path that does not meet the hold time constraints in the digital circuit standard unit library. Taking advantage of the characteristic of the circuit delay lock storage device to pass through high-level stable circuits without obstacles, up to half a cycle time can be called from the circuit trigger signal to ensure that the hold time constraints in the digital circuit standard unit library are met.

[0076] Similar to the prerequisite of meeting the installation time requirement, if the installation time redundancy of the circuit timing signal capture device is less than the required time, when using this patent to repair the holding time, because the circuit timing signal capture device allocates a portion of the circuit trigger signal time to the holding time to meet the requirements of the digital circuit standard unit library, the circuit trigger signal time required for the installation time on the corresponding circuit timing signal capture device is reduced. Theoretically, the reduction in circuit trigger signal time during installation should equal the non-compliance of the holding time with the digital circuit standard unit library; otherwise, even if the holding time meets the constraints of the digital circuit standard unit library, it will still result in the current circuit timing signal capture device not meeting the constraints of the digital circuit standard unit library regarding installation time.

[0077] In one embodiment, such as Figure 4 As shown, step S4: If satisfied, the circuit delays and locks a portion of the clock cycle time of the storage device, and repairs the violation path according to the timing violation type, specifically including the following steps:

[0078] When the timing margin of the violation path meets the calling conditions, the unobstructed passage characteristic of the circuit delay-locked memory during high-level smooth circuits is utilized to call a portion of the clock cycle time to repair the violation path based on a half-cycle time call using the circuit delay-locked memory. Specifically, this includes the following steps:

[0079] For installation time violations, the circuit timing signal capture device at the end of the violation path is replaced with a circuit delay lock storage device;

[0080] For holding time violations, a circuit-delayed latching memory device driven by a reverse clock signal is inserted into the violation path.

[0081] The two timing violation repair strategies provided in this embodiment both utilize the unobstructed passage characteristics of circuit delay-locked storage devices during high-level stable circuits. By calling up a portion of the clock cycle time, they respectively compensate for the installation time gap or extend the effective data holding time, thereby resolving timing violations that cannot be repaired by conventional methods under the premise of meeting strict verification conditions.

[0082] In one embodiment, step S5 requires substantial modifications to the circuit design or specifications, specifically implemented as follows:

[0083] When all the above-mentioned repair methods (including conventional and special repairs) fail to meet timing requirements, it indicates that the problem may stem from a deeper design flaw. In this case, substantial modifications to the circuit design or specifications are required, including but not limited to: reallocating the timing budget, optimizing the clock network structure to reduce skew, and adjusting the circuit topology of the critical path, in order to ultimately ensure that the timing violation repairs achieve final convergence.

[0084] The verification process and precautions for this application are as follows:

[0085] After completing any of the above-mentioned routine repairs, special repairs, or substantial modification repairs, a comprehensive timing analysis (formal verification and timing verification) must be performed on the timing violations to form a closed-loop process of "detection-repair-verification". This iterative process needs to be continued until all timing violations are completely eliminated, ensuring that the circuit design ultimately meets all the constraints of the digital circuit standard cell library.

[0086] It is important to note that the following two points require special attention:

[0087] Device Constraints: Theoretically, if the limitations imposed by the digital circuit standard cell library on the installation and holding times of the circuit delay-locked memory (CDLMC) are disregarded, the method described in this patent can call up half a cycle time. However, the CDLMC itself also has installation and holding times, so the maximum call time is theoretically slightly less than half a cycle time. Therefore, when using the half-cycle time calling method for the CDLMC described in this patent, it is also necessary to consider whether the limitations imposed by the digital circuit standard cell library on the installation and holding times of the CDLMC can be met.

[0088] Formal Verification: It's also important to note that the method of calling the circuit with a half-cycle time delay to lock the memory device alters the circuit structure in the design, potentially causing formal verification to fail. Therefore, during the timing repair phase, this special repair method should only be used if conventional engineering change instructions fail to meet timing constraints, and formal verification has confirmed the circuit's functional equivalence.

[0089] This solution offers a novel approach and method for meeting the installation and hold-up time requirements of digital circuit standard cell libraries under extreme conditions. It is particularly suitable for large-scale designs and asynchronous data trigger signal designs where meeting the constraints of digital circuit standard cell libraries via exception paths is extremely challenging. This method allows for meeting the installation and hold-up time constraints of digital circuit standard cell libraries at the last minute, thereby shortening the digital back-end design cycle, saving costs, and allowing more time for later production testing.

[0090] Secondly, this application provides a circuit delay-locked memory device for implementing the half-cycle timing repair method of the circuit delay-locked memory device as described above, comprising:

[0091] The signal detection module is used to identify unobstructed passage time windows during high-level smooth circuits;

[0092] The time call module is used to calculate and call a portion of the clock cycle time; the maximum time call amount of the time call module is limited by the installation time and holding time requirements of the device itself.

[0093] The path reconstruction module is used to perform device replacement or insertion operations based on the timing violation type.

[0094] Thirdly, this application provides a half-cycle timing repair system for a circuit delay-locked memory device, comprising:

[0095] The timing analysis unit is used to detect whether there are installation timing violations or holding time violations in digital circuit designs that violate the constraints of the digital circuit standard cell library;

[0096] The routine repair unit is communicatively connected to the timing analysis unit and is used to prioritize the execution of routine engineering change instructions for detected timing violations;

[0097] The circuit-delayed latching storage device as described above;

[0098] The control unit is communicatively connected to the conventional repair unit and is used to activate the circuit delay lock storage device to perform a half-cycle time call repair for timing violations when the conventional repair unit fails to meet the timing constraint requirements.

[0099] In one embodiment, it further includes:

[0100] The verification unit is used to perform formal and temporal verification on the repaired violation paths.

[0101] The functions of each module in the half-cycle timing repair system of the circuit delay lock storage device correspond to the steps in the embodiment of the half-cycle timing repair method of the circuit delay lock storage device. Their functions and implementation processes will not be described in detail here.

[0102] Thirdly, embodiments of this application provide a half-cycle timing repair device based on a circuit delay-locked storage device. The half-cycle timing repair device based on a circuit delay-locked storage device can be a device with data processing capabilities, such as a personal computer (PC), a laptop, or a server.

[0103] In this embodiment, the half-cycle timing repair device based on the circuit delay-locked storage device may include a processor, a memory, a communication interface, and a communication bus.

[0104] The communication bus can be of any type and is used to interconnect the processor, memory, and communication interface.

[0105] The communication interface includes input / output (I / O) interfaces, physical interfaces, and logical interfaces used for interconnecting devices within the half-cycle timing repair device based on circuit delay-locked memory, as well as interfaces used for interconnecting the half-cycle timing repair device with other devices (such as other computing devices or user equipment). Physical interfaces can be Ethernet interfaces, fiber optic interfaces, ATM interfaces, etc.; user equipment can be displays, keyboards, etc.

[0106] Memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0107] The processor can be a general-purpose processor, which can call a half-cycle timing repair program based on a circuit delay-locked memory device stored in memory and execute the half-cycle timing repair method for the circuit delay-locked memory device provided in the embodiments of this application. For example, the general-purpose processor can be a central processing unit (CPU). The method executed when the half-cycle timing repair program based on the circuit delay-locked memory device is called can refer to the various embodiments of the half-cycle timing repair method for the circuit delay-locked memory device in this application, and will not be repeated here.

[0108] Fourthly, embodiments of this application also provide a readable storage medium.

[0109] The present application stores a half-cycle timing repair program based on a circuit delay-locked memory device on a readable storage medium, wherein when the half-cycle timing repair program based on a circuit delay-locked memory device is executed by a processor, it implements the steps of the half-cycle timing repair method of the circuit delay-locked memory device as described above.

[0110] The method implemented when the half-cycle timing repair procedure based on the circuit delay-locked memory device is executed can be referred to in various embodiments of the half-cycle timing repair method of the circuit delay-locked memory device of this application, and will not be repeated here.

[0111] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for half-cycle timing recovery of a delay-locked storage device, comprising: The method comprises the following steps: detecting whether there is a timing violation in a digital circuit design, the timing violation being a setup time violation or a hold time violation that violates a constraint of a digital circuit standard cell library; when the timing violation exists and cannot be repaired by a conventional engineering change instruction, verifying whether a timing margin of a violation path meets a calling condition; if yes, calling a partial clock cycle time of the circuit delay lock storage device and repairing the violation path according to a type of the timing violation, comprising: for the setup time violation, replacing a circuit timing signal capture device at an end of the violation path with the circuit delay lock storage device; for the hold time violation, inserting the circuit delay lock storage device triggered by a reverse signal driving device in the violation path.

2. The method of claim 1, wherein the half-cycle timing repair of a circuit delay-locked storage device is characterized by, The verifying whether the timing margin of the violation path meets the calling condition comprises: for the setup time violation, verifying whether a setup time margin of a circuit timing signal trigger device of a subsequent path is sufficient to cover a setup time violation amount of a current path; for the hold time violation, verifying whether a setup time margin of a circuit timing signal capture device of the violation path is greater than or equal to the hold time violation amount.

3. The method of claim 1, wherein the half-cycle timing repair of a circuit delay-locked storage device is characterized by, The maximum calling time of the calling partial clock cycle time is close to half a clock cycle.

4. The method of claim 1, wherein the half-cycle timing repair of a circuit delay-locked storage device is characterized by, The method further comprises: after completing reconstruction of the violation path, verifying whether a setup time and a hold time of the circuit delay lock storage device itself meet a constraint requirement of the digital circuit standard cell library.

5. The method of claim 1, wherein the half-cycle timing repair of a circuit delay locked storage device is characterized by, The conventional engineering change instruction comprises at least one of cell driving capability adjustment, buffer insertion and logic optimization.

6. The method of claim 1, wherein the half-cycle timing repair of a circuit delay locked storage device is characterized by, The method is applicable to asynchronous clock domain circuit design.

7. A circuit delay-locked storage device for use in the half-cycle timing recovery method of any one of claims 1-6, wherein, Comprise: a signal detection module for identifying an unobstructed passing time window during a high-level stable circuit; a time calling module for calculating and calling partial clock cycle time; a path reconstruction module for performing device replacement or insertion operation according to a type of the timing violation.

8. The circuit delay-locked storage device of claim 7, wherein, The maximum time calling amount of the time calling module is limited by the setup time and the hold time requirements of the device itself.

9. A circuit for half-cycle timing recovery of a delay-locked storage device, comprising: Comprise: a timing analysis unit for detecting whether there is a setup time violation or a hold time violation that violates a constraint of a digital circuit standard cell library in a digital circuit design; a conventional repair unit in communication connection with the timing analysis unit, for preferentially performing a conventional engineering change instruction on the detected timing violation; The circuit delay lock storage device of claim 7; a control unit in communication connection with the conventional repair unit, for activating the circuit delay lock storage device to perform a half cycle time calling repair on the timing violation when the conventional repair unit cannot meet the timing constraint requirement.

10. The system for half-cycle timing recovery of a delay-locked storage device of a circuit according to claim 9, wherein, Further comprise: a verification unit for performing formal verification and timing verification on the repaired violation path.

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