Split-plate type multi-path server system, method and device

Abstract

The embodiment of the invention provides a split-board multi-path server system, method and device, the system comprises N mainboards, an adapter board and a management board, the mainboards are in communication connection with one another, the mainboards are in communication connection with the adapter board, and the adapter board is in communication connection with the management board; the mainboard sends an in-place signal to the adapter plate for representing the working state of the mainboard; the adapter board sends identification signals to the mainboards and the management board according to the number of the in-place signals to indicate the number of the mainboards in the current working state, and the management board monitors and manages the mainboards according to the identification signals; and the pre-configured first mainboard CPU opens an ultra-high-speed path interconnection UPI channel corresponding to the identification signal. By means of the technical scheme, the technical problems that in the prior art, a multi-channel server system is high in hardware cost, large in software complexity and inflexible in mainboard layout can be effectively solved.

Description

Technical Field

[0001] This application relates to the field of server architecture technology, and more specifically, to a multi-channel server system, method, and apparatus with a split-board configuration. Background Technology

[0002] With the development of servers, customers have increasingly higher requirements for critical applications such as high-performance computing and in-memory computing. To support this design, major server manufacturers have designed multi-processor server systems based on various platforms.

[0003] The current mainstream system architecture for multi-processor servers is a 2-processor or 4-processor configuration. These servers use independent motherboards, each integrating a Baseboard Management Controller (BMC) and a Complex Programmable Logic Device (CPLD). While this design can meet the performance requirements of multi-processor server systems to a certain extent, it also introduces significant problems, as follows:

[0004] 1. High hardware costs: Each motherboard requires a dedicated management controller and programmable logic device, which increases hardware costs.

[0005] 2. High software complexity: When a server system consists of multiple motherboards, if the BMC on each motherboard needs to participate in the management of the entire server, a complex software mechanism is required to coordinate the work of each BMC and avoid conflicts. This further increases the difficulty of software development and maintenance.

[0006] 3. Poor motherboard layout flexibility: Traditional 2-way or 4-way server motherboards typically have fixed designs, meaning different numbers of CPUs require different PCB layouts, thus limiting the motherboard's layout flexibility and space utilization efficiency. For example, 2-way and 4-way motherboards cannot share the same PCB, resulting in a lack of adaptability in server internal layout.

[0007] 4. Low maintainability: The design of multiple independent motherboards makes it difficult to quickly locate the faulty motherboard when the server fails, increasing the complexity and time cost of maintenance. Summary of the Invention

[0008] This application provides a multi-processor server system, method, and apparatus with a split-board architecture to at least solve the problems existing in the current multi-processor server system architecture in the related art.

[0009] According to one embodiment of this application, a multi-processor server system with multiple boards is provided, including: N motherboards, adapter boards, and management boards, wherein each motherboard is communicatively connected to the others, each motherboard is communicatively connected to the adapter board, and the adapter board is communicatively connected to the management board;

[0010] Each of the motherboards sends an presence signal to the adapter board; the presence signal indicates that the motherboard is currently in normal working condition.

[0011] The adapter board sends an identification signal to the motherboard and the management board according to the number of received presence signals, so that the management board can monitor and manage the motherboard corresponding to the identification signal; wherein, the identification signal is used to represent the number of motherboards currently in normal working condition;

[0012] The first motherboard CPU in the pre-configured motherboard enables the Ultra-High Speed ​​Path Interconnect (UPI) channel corresponding to the identification signal.

[0013] In one exemplary embodiment, the motherboard includes: a CPU, a first complex programmable logic device, a plurality of first connectors, and a second connector;

[0014] The adapter board includes: a clock generator, N motherboard connectors, a second complex programmable logic device, a management board connector, and multiple integrated circuit bus I2C conversion chips.

[0015] In one exemplary embodiment, the motherboards are interconnected via the first connector to transmit UPI signals, and the motherboards are interconnected with the adapter board via the second connector; the adapter board is interconnected with the management board via the management board connector.

[0016] In one exemplary embodiment, the motherboard also communicates with the adapter board via a first signal, the first signal including at least one of the following: motherboard key signal, motherboard clock signal, motherboard general input / output signal, motherboard I2C signal, LTPI signal, and enhanced serial peripheral interface (ESPI) signal.

[0017] In one exemplary embodiment, the key signals of the motherboard are transmitted to other motherboards via the motherboard connector in the adapter board.

[0018] In one exemplary embodiment, the motherboard clock signal, the motherboard general purpose input / output signal, the motherboard I2C signal, the LTPI signal, and the ESPI signal are transmitted to other motherboards or the management board via the second complex programmable logic device.

[0019] In one exemplary embodiment, the system further includes: a pre-configuration module, configured to configure the CPUs in each motherboard according to a motherboard identification signal pre-set on the motherboard connector via a hardware configuration signal to determine the first motherboard CPU; the motherboard identification signal is used to characterize the position of the motherboard.

[0020] In one exemplary embodiment, the pre-configuration module is further configured to enable the EPSI function on the first motherboard CPU and disable the EPSI function on the other motherboard CPUs.

[0021] In one exemplary embodiment, the clock generator generates multiple sets of clocks, which are sent to the CPUs of each motherboard through the N motherboard connectors.

[0022] In one exemplary embodiment, the management board includes a management board connector and a baseboard management controller.

[0023] In one exemplary embodiment, the adapter board also communicates with the management board via a second signal, the second signal including at least one of the following: the EPSI signal, the substrate management controller LTPI signal, the adapter board I2C signal, and the motherboard I2C signal.

[0024] In one exemplary embodiment, the management board is further configured to enable the I2C channel corresponding to the identification signal to monitor and manage each motherboard.

[0025] In one exemplary embodiment, the management board is further configured to monitor and manage the adapter board via an I2C channel between the management board and the adapter board.

[0026] In one exemplary embodiment, the first motherboard CPU communicates with the baseboard management controller of the management board via the EPSI bus to complete the power-on process.

[0027] In one exemplary embodiment, the second complex programmable logic device is provided with an LTPI module, which is used to coordinate the power-on timing between motherboards.

[0028] According to another embodiment of this application, a communication method for a multi-channel server system is provided, comprising:

[0029] Acquire an in-situ signal, which is used to indicate that the motherboard is currently in normal working condition;

[0030] An identification signal is generated based on the number of in-situ signals, and the identification signal is used to characterize the number of motherboards currently in normal working condition;

[0031] The corresponding UPI channel is activated based on the identification signal, and the motherboard corresponding to the identification signal is monitored and managed.

[0032] In one exemplary embodiment, the method further includes:

[0033] The CPU of each motherboard is configured via a hardware configuration signal based on a pre-set motherboard identification signal; the motherboard identification signal is used to indicate the location of the motherboard.

[0034] In one exemplary embodiment, the method further includes:

[0035] Coordinate the power-on sequence between motherboards.

[0036] According to another embodiment of this application, a communication device for a multi-channel server system is provided, comprising:

[0037] The signal acquisition module is used to acquire the presence signal, which is used to indicate that the motherboard is currently in normal working condition.

[0038] A signal generation module is used to generate an identification signal based on the number of in-situ signals, the identification signal being used to characterize the number of motherboards currently in normal working condition;

[0039] The monitoring module is used to activate the corresponding UPI channel based on the identification signal and to monitor and manage the motherboard corresponding to the identification signal.

[0040] In one exemplary embodiment, the apparatus further includes:

[0041] The pre-configuration module is used to configure the CPU of each motherboard according to a pre-set motherboard identification signal via a hardware configuration signal; the motherboard identification signal is used to indicate the position of the motherboard.

[0042] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0043] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0044] This application significantly reduces server hardware and software development costs, while improving server maintainability and flexibility. By sharing adapter boards and management boards, server systems with varying numbers of motherboards can share the same PCB design, reducing costs and simplifying management and maintenance. Furthermore, the pluggable nature of the motherboards allows users to flexibly adjust server configurations according to their needs. Flexible layout through installation location selection improves space utilization, meeting the demands of high-performance computing, in-memory computing, and other critical applications, thereby enhancing the overall performance and efficiency of the server system. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of a multi-channel server system based on an embodiment of this application;

[0046] Figure 2 This is a schematic diagram of a motherboard in a multi-processor server system according to an embodiment of this application;

[0047] Figure 3 This is a schematic diagram of a switchboard in a split-board multi-channel server system according to an embodiment of this application;

[0048] Figure 4 This is a schematic diagram of a management board in a multi-channel server system according to an embodiment of this application;

[0049] Figure 5 This is a hardware structure block diagram of a mobile terminal for a communication method of a split-board multi-channel server system according to an embodiment of this application.

[0050] Figure 6 This is a flowchart of a communication method for a multi-channel server system based on an embodiment of this application;

[0051] Figure 7 This is an example diagram of a communication method for a multi-channel server system based on an embodiment of this application;

[0052] Figure 8 This is a structural block diagram of the communication device of a multi-channel server system based on an embodiment of this application. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0054] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0055] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] This embodiment provides a multi-processor server system with multiple servers on a separate board. Figure 1 This is a schematic diagram of a multi-channel server system based on an embodiment of this application, as shown below. Figure 1 As shown, the multi-processor server system includes: N motherboards 101, adapter boards 102, and management boards 103. The motherboards are interconnected, each motherboard is connected to the adapter board, and the adapter board is connected to the management board.

[0057] Each motherboard sends an presence signal to the adapter board 102; the presence signal is used to indicate that the current motherboard is in normal working condition.

[0058] The adapter board 102 sends an identification signal to the motherboard and management board 103 according to the number of received presence signals, so that the management board 103 can monitor and manage the motherboard corresponding to the identification signal; wherein, the identification signal is used to represent the number of motherboards currently in normal working condition;

[0059] The first motherboard CPU in the pre-configured motherboard enables the UPI channel corresponding to the identification signal.

[0060] Optionally, in this embodiment, N motherboards 101 can refer to the number of motherboards that can be configured in the system, where N can be the maximum number of motherboards that the system can support, used to implement the server's computing and communication functions. The adapter board 102 can be an intermediate board in a multi-processor server system used to connect multiple motherboards and the management board 103, responsible for signal conversion, transmission, and coordination. The management board 103 can be a board responsible for the overall monitoring and management of the server, including a Baseboard Management Controller (BMC) chip and a connector, which monitors the server's temperature, voltage, and other statuses through communication with the adapter board and each motherboard. The presence signal is a signal between the motherboard and the adapter board used to confirm whether the motherboard is correctly installed in the server. The adapter board CPLD determines the number of motherboards in the current server by recognizing the presence signal. Normal operating state can be the state in which all components in the server system are correctly installed and configured and can operate according to expected functions. The identification signal is a signal used to characterize the number of motherboards currently in normal operating state. Monitoring and management can be achieved by the BMC monitoring and managing the temperature, voltage, and other statuses of the adapter board and each motherboard via the Inter-Integrated Circuit (I2C) bus, ensuring the stable operation of the server system. The UltraPath Interconnect (UPI) channel is a dedicated channel for high-speed communication between CPUs. When the server powers on, the motherboard CPU enables the UPI port based on the node ID signal, enabling direct communication between CPUs. Pre-configured motherboards can be pre-set in the server system according to actual needs, analogous to the master position in a master-slave architecture. In a multi-processor server system, the first motherboard CPU, identified as the CPU with the 0th motherboard identifier (i.e., the legacy CPU), is responsible for enabling the Enhanced Serial Peripheral Interface (ESPI) interface with the CPLD and BMC during startup to complete the boot process.

[0061] In a specific application scenario, a multi-processor server system was constructed, consisting of four motherboards, one adapter board 102, and one management board 103. Each motherboard is equipped with a CPU, CPLD, Type I connectors, and Type II connectors. Adapter board 102 is equipped with a clock generator, motherboard connectors, CPLD, management board connectors, and an I2C conversion chip. Management board 103 contains a connector and a BMC chip. When the server starts, each motherboard sends an "in-place" signal to adapter board 102, indicating that it is in normal working order. Upon receiving these signals, adapter board 102 determines that four motherboards are in place based on the number of signals, and then sends a node ID signal [1:0]=11 to each motherboard and management board 103, indicating that the current system is configured as a 4-processor server. Management board 103 monitors and manages the motherboards based on this signal. During this process, the CPU of motherboard 0, pre-configured as a legacy CPU, enables UPI channel communication with other motherboards and coordinates power-on timing with other motherboards via LTPI signals. In this scenario, the BMC chip on management board 103 selects the correct I2C channel through the I2C switch chip to monitor the motherboards in place, ensuring that it can obtain information such as motherboard temperature and voltage for effective management. Each motherboard's CPLD sets the CPU's hardware configuration pins via hardware configuration signals based on the node ID signal and its own motherboard identification signal, enabling the system to support multi-server configuration. During this process, information with high real-time requirements is transmitted between the motherboard and adapter board 102 via GPIO signals, while other information is exchanged via LTPI signals. The CPLD in adapter board 102 coordinates to ensure consistent power-on timing. The Legacy CPU communicates with the BMC chip on management board 103 via the ESPI bus to complete the boot process.

[0062] By applying the technical solution of this embodiment, a multi-processor server system with a split-board architecture is optimized, aiming to solve the technical problems of high hardware cost, high software complexity, and insufficient motherboard layout flexibility in existing multi-processor server systems. By adopting an architecture of N motherboards 101, one adapter board 102, and one management board 103, this system enables servers with different numbers of processors to share the same PCB substrate. This not only reduces hardware costs but also simplifies software development and enhances system maintainability and spatial layout flexibility. The motherboards send an presence signal to the adapter board 102, indicating whether the motherboards are in a valid working state. Based on the number of received presence signals, the adapter board 102 determines and sends an identification signal to the motherboards and management board 103. This identification signal indicates the number of currently active motherboards, allowing the management board 103 to perform targeted monitoring and management. The pre-configured first motherboard CPU can automatically activate the corresponding Ultra-High Speed ​​Path Interconnect (UPI) channel based on the identification signal to adapt to different system configuration requirements. This technical solution overcomes the challenges of high motherboard costs, complex software coordination, and limited physical layout in traditional multi-processor server architectures, enabling the construction of efficient, flexible, and cost-effective server systems.

[0063] Optionally, in this embodiment, the motherboard includes: a CPU, a first complex programmable logic device, a plurality of first connectors, and a second connector.

[0064] In this embodiment, Figure 2 This is a schematic diagram of a motherboard in a multi-processor server system according to an embodiment of this application, as shown below. Figure 2 As shown, the motherboard includes: a CPU; a first complex programmable logic device (CPLD) on the motherboard (used in this invention to handle signal transmission between the motherboard and the adapter board 102, enabling hardware configuration and signal coordination); a first connector (Type I connector on the motherboard, used for interconnection with other motherboards, transmitting UPI signals, and enabling direct communication between motherboards); and a second connector (Type II connector on the motherboard, used for interconnection with the adapter board 102, transmitting signals other than UPI signals, including key signals, clock signals, GPIO signals, I2C signals, identification signals, node ID signals, LTPI signals, and ESPI signals).

[0065] Optionally, in this embodiment, each motherboard is interconnected via a first connector to transmit UPI signals, and the motherboard is interconnected with the adapter board 102 via a second connector.

[0066] In this embodiment, the motherboard establishes connections with other motherboards via a Type I connector for transmitting UPI signals, ensuring the stability and efficiency of high-speed data communication. The motherboard connects to the adapter board 102 via a Type II connector, responsible for transmitting key motherboard signals, clock signals, GPIO signals, I2C signals, motherboard identification signals, node ID signals, LTPI signals, and ESPI signals, achieving comprehensive communication and collaboration between different components. This architecture not only simplifies hardware costs and software development complexity but also enhances system maintainability and flexibility, allowing users to select motherboard configurations as needed and optimize server space layout and performance.

[0067] Optionally, in this embodiment, the motherboard also communicates with the adapter board 102 via a first signal, which includes at least one of the following: motherboard key signal, motherboard clock signal, motherboard general input / output signal, motherboard I2C signal, LTPI signal, and enhanced serial peripheral interface (ESPI) signal.

[0068] In this embodiment, the key motherboard signals are crucial signals that require direct interconnection between the CPUs of each motherboard. These signals enable communication and collaboration between the motherboards, ensuring stable operation of the server system. Motherboard clock signal: The motherboard clock signal is generated by the clock generator on the adapter board 102 and provided to the CPUs of each motherboard via the motherboard connector as a synchronization signal, ensuring the timing of CPU operations. General Purpose Input Output (GPIO) signals: These are used to transmit information with high real-time requirements, enabling high-speed data transmission between the motherboard and the adapter board 102. Motherboard I2C signals: These are monitoring signals transmitted between the motherboard, adapter board 102, and management board 103 via the integrated circuit bus, used to monitor information such as temperature and voltage. LTPI (LVDS Tunneling Protocol and Interface) signals: These are signals used for communication between motherboards. LTPI enables power-on timing coordination between the CPUs of each motherboard, ensuring stable operation of the server system. LVDS (Low Voltage Differential Signaling) is a specific type of LP signal used in this embodiment. The Enhanced Serial Peripheral Interface (ESPI) signal is used for communication between the CPU and the CPLD or BMC. The CPU obtains the identification signal through the ESPI bus to determine the type of the current server system and enable the corresponding UPI channel.

[0069] Specifically, such as Figure 2As shown, the motherboard and adapter board 102 communicate with each other via a first signal, which includes at least one of the following: motherboard critical signal, motherboard clock signal, motherboard general purpose input / output signal, motherboard I2C signal, LTPI signal, and Enhanced Serial Peripheral Interface (ESPI) signal. Specifically, the clock generator on adapter board 102 generates four sets of clock signals, which are supplied to the CPUs of the four motherboards via motherboard connectors 0 to 3, respectively, ensuring system timing synchronization. The motherboards are interconnected by transmitting UPI signals through Type I connectors, and exchange other signals with adapter board 102 through Type II connectors, including but not limited to critical signals, clock signals, GPIO signals, I2C signals, motherboard identification signals, node ID signals (i.e., identification signals), LTPI signals, and ESPI signals. The adapter board CPLD determines the current number of motherboards in the server by detecting the motherboard presence signal, configures the node ID signal accordingly, and further coordinates the power-on sequence of each motherboard through the LTPI signal, ensuring stability and coordination during system startup. On motherboard 0, the BIOS enables the EPSI function to facilitate handshake communication between the legacy CPU and the management board BMC, completing the boot process. On other motherboards, the EPSI function is disabled.

[0070] Optionally, in this embodiment, key signals of the motherboard are transmitted to other motherboards through the motherboard connector in the adapter board 102.

[0071] Optionally, in this embodiment, the motherboard clock signal, motherboard general input / output signal, motherboard I2C signal, LTPI (LVDS Tunneling Protocol and Interface) signal, and ESPI signal are transmitted to other motherboards or management boards 103 through a second complex programmable logic device.

[0072] In this embodiment, critical signals from the motherboard are directly transmitted to other motherboards via the motherboard connector in the adapter board 102 without being processed by the CPLD on the adapter board 102. This design ensures that critical signals requiring direct interconnection between the CPUs of each motherboard can be effectively transmitted on the adapter board 102, making the transmission speed of critical motherboard signals faster. The motherboard transmits the motherboard clock signal, general purpose input / output (GPIO) signals, integrated circuit bus (I2C) signals, LVDS tunneling protocol and interface (LTPI) signals, and enhanced serial peripheral interface (ESPI) signals to other motherboards or management boards 103 via a complex programmable logic device (CPLD). Specifically, the CPLD on the adapter board 102 acts as the signal transmission center, receiving and sending these signals through motherboard connectors 0 to 3, ensuring effective communication between the motherboards and the management board 103. The clock signal is generated by the clock generator on the adapter board 102 and distributed to the CPUs of each motherboard through the motherboard connector to achieve synchronous operation. General purpose input / output (GPIO) signals and integrated circuit bus (ICB) signals are transmitted between the adapter board 102 and the motherboard to achieve real-time information exchange between motherboards. The LVDS tunneling protocol and interface signals, along with the enhanced serial peripheral interface signals, are used for communication between the motherboard and the management board 103. In particular, during the system startup process, the legacy CPU can communicate with the BMC via the ESPI bus to complete the boot process.

[0073] Optionally, in this embodiment, the system further includes:

[0074] The pre-configuration module is used to configure the CPUs in each motherboard according to the motherboard identification signal preset on the motherboard connector via hardware configuration signals to determine the first motherboard CPU; the motherboard identification signal is used to indicate the location of the motherboard.

[0075] In this embodiment, the system also includes a pre-configuration module. This module configures the CPUs in each motherboard using hardware configuration signals based on the motherboard identification signal pre-set on the motherboard connector, thereby determining the first motherboard CPU. This design enables automatic identification and configuration of the CPUs on each motherboard at the hardware level. The motherboard identification signal represents the location of the motherboard, ensuring that the system can quickly and accurately determine the location of the legacy CPU during startup, thus optimizing the startup process and system configuration. After the system is powered on, the CPLD of the adapter board 102 can determine whether the current server is configured as single-processor, dual-processor, or quad-processor by recognizing the motherboard identification signal on the motherboard connector, and then set the identifier to achieve automatic identification of the system type. This automatic identification mechanism reduces the dependence on software configuration and improves system startup efficiency and stability. Subsequently, the CPLD of each motherboard sets the CPU's hardware configuration pins using hardware configuration signals based on the node ID signal and its own motherboard identification signal, enabling the system to automatically adjust to the corresponding multi-processor server configuration according to the current number and location of motherboards without manual intervention, improving the system's flexibility and ease of use.

[0076] Optionally, in this embodiment, the pre-configuration module is further used to enable the EPSI function for the first motherboard CPU and disable the EPSI function for the other motherboard CPUs.

[0077] In this embodiment, the legacy CPU of the first motherboard enables the ESPI interface with its CPLD and BMC during startup, while the ESPI interfaces of other motherboards are disabled. This design allows the first motherboard to obtain information about the number of motherboards in the node via the ESPI bus during system startup and enable the corresponding UPI channels accordingly. Simultaneously, communication with other motherboards via the LTPI signal ensures synchronized power-on timing among the motherboards, thereby optimizing the system startup process and enhancing server stability and efficiency. The CPU of the first motherboard enables the ESPI function, while the CPUs of the other motherboards disable the ESPI function. This configuration ensures that the legacy CPU can prioritize communication with the BMC of the management board 103 to complete the boot process, while also avoiding unnecessary ESPI signal usage by other motherboards that consume system resources. In subsequent operations, the BMC can understand the actual configuration type of the server based on the node ID signal, thereby enabling the corresponding I2C channels for monitoring and management, including the detection of key parameters such as temperature and voltage. This not only simplifies the design of the management software but also improves the overall management efficiency of the server.

[0078] Optionally, in this embodiment, the adapter board 102 includes: a clock generator, N motherboard connectors, a second complex programmable logic device, a management board connector, and multiple integrated circuit bus I2C conversion chips. The adapter board 102 is communicatively connected to the management board 103 via the management board connectors.

[0079] Optionally, in this embodiment, the adapter board 102 also communicates with the management board 103 via a second signal, the second signal including at least one of the following: an EPSI signal, a substrate management controller LTPI signal, an adapter board I2C signal, and a motherboard I2C signal.

[0080] In this embodiment, a clock generator in the adapter board 102 generates multiple sets of clock signals. These clock signals are provided to the CPUs of each motherboard via the motherboard connectors to ensure clock synchronization of the server system. The motherboard connectors on the adapter board 102 interface with the Type II connectors on the motherboards to transmit clock signals, critical signals, GPIO signals, I2C signals, identification signals, node ID signals, LTPI signals, and ESPI signals. The second complex programmable logic device (CPLD) in this invention refers to the CPLD on the adapter board 102, used to handle signal transmission between each motherboard and the management board 103, enabling signal coordination and timing control between motherboards. The management board connector on the adapter board 102 interfaces with the management board 103 to transmit ESPI signals, BMC LTPI, adapter board I2C, motherboard I2C signals, and node ID signals, enabling the management board 103 to monitor and manage the entire server system. The integrated circuit bus conversion chip in this invention switches and manages the I2C signals from the BMC to each motherboard on the adapter board 102, enabling management functions such as temperature and voltage monitoring for each motherboard. It can be an I2C switch chip, or a chip with the same or similar functions.

[0081] In this embodiment, the adapter board 102 not only undertakes the crucial task of signal transmission between motherboards but also establishes an efficient communication channel with the management board 103, including at least one of the following: EPSI signal, LTPI signal of the baseboard management controller, adapter board I2C signal, and motherboard I2C signal. Specifically, the EPSI signal enables the legacy CPU to handshake with the BMC during startup, ensuring smooth interaction between the manager and the CPU; the LTPI signal is used to coordinate the power-on sequence between motherboards, making the startup process of the entire server system more orderly; and the I2C signal, through the I2C switch chip on the adapter board 102, enables the BMC to monitor and manage the status of the adapter board 102 and each motherboard, such as temperature and voltage monitoring, ensuring the safe and stable operation of the server. With the precise coordination of these signals, the solution of this invention can achieve comprehensive perception and control of the server system status, improving the flexibility and responsiveness of the entire system.

[0082] Optional, Figure 3 This is a schematic diagram of a switchboard 102 in a split-board multi-channel server system according to an embodiment of this application, as shown below. Figure 3As shown, the clock generator generates four sets of clock signals, which are provided to the CPUs of the four motherboards via motherboard connectors 0-3. This is a key component to ensure that the CPUs on the motherboards can work synchronously. The adapter board 102 has four motherboard connectors (motherboard connectors 0, 1, 2, and 3), which are connected to different motherboards. Each motherboard connector transmits not only clock signals but also motherboard GPIO signals, motherboard presence signals, node ID signals [1:0], the Xth motherboard identifier signal (X is 0, 1, 2, or 3), I2C_MBX_x (X is 0, 1, 2, or 3), and LTP1, LTP2, and LTP3 signals. The CPLD on the adapter board 102 receives and processes the signals from each motherboard connector. The CPLD obtains whether the motherboard plugged into motherboard connectors 0-3 is present through the motherboard 0-3 presence signal, and determines the current server system type (1-way, 2-way, or 4-way) based on the number of present boards, while simultaneously setting the node ID signal [1:0]. The LTPI module connected to the CPLD processes LTPI signals, which are used to achieve power-on timing coordination between motherboards. The management board 103 connector connects the adapter board 102 to the management board 103, transmitting EPSI signals, BMC LTPI signals, adapter board I2C signals, motherboard I2C signals, and node ID signals [1:0]. The I2CSwitch on the adapter board 102 allows the BMC to manage the adapter board 102 and each motherboard via I2C, enabling functions such as temperature and voltage monitoring. The I2CSwitch can select different I2C channels (channel 0, channel 1, channel 2, channel 3). Figure 3 By demonstrating these components and their connections, the diagram illustrates how the adapter board 102 enables signal transmission and coordination between motherboards in a split-board multi-processor server system. This design helps reduce hardware costs, improve system maintainability and space utilization, and also supports server systems with different configurations (single-processor, dual-processor, or quad-processor).

[0083] Optionally, in this embodiment, the clock generator generates multiple sets of clocks, which are sent to the CPUs of each motherboard through N motherboard connectors.

[0084] In this embodiment, the clock generator produces multiple sets of clock signals, which are sent to the CPUs of each motherboard via N motherboard connectors. This design ensures that all CPUs in the server system can synchronously receive precise clock signals, thereby guaranteeing system stability and data processing consistency. This configuration effectively avoids clock signal delays and distortions, even in complex multi-processor server environments, improving communication efficiency between CPUs. Especially during server startup, precise clock signals are crucial for synchronizing the power-on sequence of the CPUs on each motherboard, helping to quickly establish the system's normal operating state. Furthermore, this allows the server system to maintain high performance and high reliability across different configurations, whether single-processor, dual-processor, or quad-processor servers. The optimized clock signal distribution mechanism ensures that all CPUs operate under optimal conditions, thereby improving the overall processing power and response speed of the server system. In other embodiments not shown, the clock generator may generate even more sets of clock signals to adapt to a wider range of server architecture requirements, further enhancing the system's scalability and compatibility.

[0085] Optionally, in this embodiment, the management board 103 includes a management board connector and a baseboard management controller.

[0086] In this embodiment, Figure 4 This is a schematic diagram of a management board 103 in a multi-channel server system according to an embodiment of this application, as shown below. Figure 4 As shown, the connector is used to connect the management board 103 to other components. The BMC is the baseboard management controller, responsible for monitoring and managing the server's status. The management board 103 includes a management board connector and the baseboard management controller BMC. This design allows the management board 103 to establish a communication link with the adapter board 102 through the management board connector, thereby interacting with the various motherboards of the server system. As a core management component, the BMC determines the current configuration status of the server, i.e., a single-socket, dual-socket, or quad-socket server system, based on the node ID signal [1:0] from the adapter board 102. Based on this information, the BMC can intelligently adjust its management strategy, enabling the corresponding I2C channels to monitor and control key parameters of each motherboard, such as temperature and voltage, ensuring the stability and security of server operation. This precise system monitoring not only reduces management complexity but also optimizes resource allocation, enabling the management board 103 to efficiently adapt to the needs of servers of different sizes, achieving cost control while improving the overall system operation and maintenance efficiency. Of course, in other embodiments not shown, the management board 103 can also integrate more functional modules to enhance its adaptability and functionality in specific application scenarios. The management board 103 is designed to enable flexible system management and maintenance with a minimal number of components, thus providing users with a more economical and convenient server solution.

[0087] Optionally, in this embodiment, the management board 103 is also used to enable the I2C channel corresponding to the identification signal to monitor and manage each motherboard.

[0088] Optionally, in this embodiment, the management board 103 is also used to monitor and manage the adapter board 102 through the I2C channel between the management board 103 and the adapter board 102.

[0089] In this embodiment, the management board 103 intelligently activates the corresponding I2C channel to monitor and manage each motherboard by recognizing the identification signal. This design allows the BMC to automatically adjust its management strategy according to the current motherboard configuration of the server, i.e., 1-channel, 2-channel, or 4-channel, ensuring accurate monitoring of the temperature, voltage, and other status information of each motherboard. The BMC chip on the management board 103 utilizes the I2C communication protocol to not only monitor and manage the operating status of the motherboards but also extend its monitoring range to the adapter board 102, achieving comprehensive monitoring of the entire server system. This monitoring mechanism allows the BMC to dynamically detect the status of the adapter board 102, including key parameters such as temperature and voltage, during server system startup or operation, ensuring system stability and security. Furthermore, it provides convenience for maintenance and fault diagnosis; if the adapter board 102 malfunctions, the BMC can respond quickly and take necessary measures to reduce system downtime and improve the overall operating efficiency of the server. Obviously, this I2C communication mechanism is also applicable in other embodiments not explicitly shown in the figure. By adjusting the configuration of the I2CSwitch chip, it can be flexibly adapted to different numbers of motherboards and system configurations, further enhancing the scalability and adaptability of the system.

[0090] Optionally, in this embodiment, the first motherboard CPU communicates with the baseboard management controller of the management board 103 via the EPSI bus to complete the power-on process.

[0091] In this embodiment, the first motherboard CPU communicates with the Baseboard Management Controller (BMC) of the management board 103 via the EPSI bus to complete the boot process. This scheme enables the legacy CPU to effectively establish a connection with the BMC during startup, ensuring smooth system initialization and configuration through handshaking communication via the EPSI bus. Enabling the EPSI bus not only simplifies the communication path between the CPU and the BMC but also improves communication efficiency, thereby accelerating the entire server startup process. Furthermore, through the EPSI bus communication mechanism, the BMC can obtain CPU status information in a timely manner, enabling precise monitoring and management of the server system. In other embodiments not shown in the figure, communication between different motherboard CPUs and the BMC can also be achieved by adjusting the EPSI bus configuration, further enhancing the system's flexibility and scalability. This communication method reduces reliance on the traditional I2C bus, avoiding communication delays and errors caused by I2C bus conflicts in multi-processor server systems, and improving the overall stability and performance of the server system. Of course, for other motherboards, their CPUs will disable the EPSI interface during startup to avoid unnecessary resource consumption and ensure the priority and efficiency of communication between the legacy CPU and the BMC.

[0092] Optionally, in this embodiment, an LTPI module is provided in the second complex programmable logic device. The LTPI module is used to coordinate the power-on timing between motherboards.

[0093] In this embodiment, the second complex programmable logic device (CPLD) includes an LTPI module. The LTPI module effectively coordinates the power-on timing among the motherboards, ensuring that each server motherboard completes its initialization process according to a predetermined sequence and time during system startup. This avoids system instability or hardware conflicts caused by disordered power-on timing. This design enables precise control over the power-on process of a multi-server system, improving the reliability and efficiency of system startup. Specifically, the LTPI module analyzes and processes GPIO and LTPI signals from the motherboards, monitors the real-time status and power-on requirements of each motherboard, and then sends instructions to adjust the power-on timing of the motherboard CPUs through communication between the adapter board 102CPLD and the CPLDs of each motherboard. This ensures coordinated operation among the motherboards during system startup and reduces the risk of system startup failure.

[0094] The specific application environment architecture or specific hardware architecture on which the communication method of the multi-channel server system depends is described here.

[0095] The methods and embodiments provided in this application can be executed on a mobile terminal, computer terminal, or similar computing device. Taking running on a mobile terminal as an example, Figure 5 This is a hardware structure block diagram of a mobile terminal for a communication method of a multi-channel server system according to an embodiment of this application. Figure 5 As shown, a mobile terminal may include one or more ( Figure 5 Only one is shown in the diagram. A processor 502 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 504 for storing data are also shown. The mobile terminal may further include a transmission device 506 for communication functions and an input / output device 508. Those skilled in the art will understand that... Figure 5 The structure shown is for illustrative purposes only and does not limit the structure of the mobile terminal described above. For example, the mobile terminal may also include components that are more... Figure 5 The more or fewer components shown, or having the same Figure 5 The different configurations shown.

[0096] The memory 504 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the communication method of the multi-channel server system in this embodiment. The processor 502 executes various functional applications and data processing by running the computer program stored in the memory 504, thus implementing the aforementioned method. The memory 504 may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 504 may further include memory remotely located relative to the processor 502, and these remote memories can be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0097] Transmission device 506 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the mobile terminal's communication provider. In one example, transmission device 506 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, transmission device 506 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0098] This embodiment provides a communication method for a multi-channel server system with multiple boards. Figure 6This is a flowchart of a communication method for a multi-channel server system based on an embodiment of this application, as shown below. Figure 6 As shown, the process includes the following steps:

[0099] Step S602: Obtain the presence signal, which is used to indicate that the motherboard is currently in normal working condition.

[0100] Step S604: Generate an identification signal based on the number of in-situ signals. The identification signal is used to characterize the number of motherboards currently in normal working condition.

[0101] Step S606: Open the corresponding UPI channel according to the identification signal and monitor and manage the motherboard corresponding to the identification signal.

[0102] This application provides a communication method for a multi-processor server system. The method acquires a motherboard presence signal, indicating whether the motherboard is inserted and in normal working order. Then, based on the number of motherboards present, an identification signal is generated to indicate whether the system is in 1-processor, 2-processor, or 4-processor server mode. The CPLD in the server system determines the number of server motherboards based on the number of valid motherboard presence signals and outputs corresponding identification signals to each motherboard CPLD and the BMC (Browser Management Board). Each motherboard CPLD enables the corresponding UPI port based on this signal, while the BMC activates the corresponding I2C monitoring channel to monitor and manage the motherboard's temperature, voltage, etc. This method simplifies the system architecture, reduces hardware costs, improves software development efficiency and server maintainability by centrally processing motherboard quantity detection and UPI port enabling. Furthermore, the pluggable motherboard design enhances system flexibility and space utilization. Therefore, the technical solution of this invention effectively solves the problems of high hardware cost, high software complexity, and low server layout flexibility in traditional multi-processor server systems.

[0103] In one exemplary embodiment, the CPU of each motherboard is configured via a hardware configuration signal according to a preset motherboard identification signal; the motherboard identification signal is used to characterize the location of the motherboard.

[0104] In this embodiment, the CPUs of each motherboard are configured via hardware configuration signals based on a pre-set motherboard identification signal. The motherboard identification signal precisely identifies the motherboard's position within the system. This configuration mechanism ensures that the server system can automatically identify and adapt to the current motherboard layout after power-on, regardless of whether it is in a 1-way, 2-way, or 4-way system mode. Specifically, the CPLD of the adapter board 102 can clearly distinguish the presence of motherboards 0-3 by recognizing the motherboard identification signal on the motherboard connector, thereby determining which motherboard CPU should be configured as a legacy CPU, while the others are configured as non-legacy CPUs. This hardware-level automatic configuration not only simplifies the system initialization process but also ensures the correct enabling of the UPI ports, allowing the server to seamlessly switch to the corresponding operating mode based on the actual number of motherboards installed, effectively improving system flexibility and efficiency. Furthermore, through this mechanism, the CPLD of each motherboard can adjust the CPU's hardware configuration PIN based on the node ID signal and its own motherboard identification signal, thereby promoting the rapid setup and normal operation of multi-way server systems. Smooth transitions between multi-way server systems can be achieved without manual intervention, reducing operational complexity and optimizing server management processes.

[0105] In one exemplary embodiment, the method further includes coordinating the power-on timing among the motherboards.

[0106] In this embodiment, a technical solution for coordinating the power-on sequence between motherboards is also incorporated. Specifically, the CPLD in the adapter board 102 receives and processes the GPIO and LTPI signals of each motherboard, enabling it to monitor the motherboard status in real time and adjust the power-on sequence based on this information. This ensures that the power-on sequence between motherboards is synchronized, effectively preventing system instability or failure caused by improper power-on sequence. This coordination mechanism is implemented through the LTPI module in the CPLD of the adapter board 102. This module can dynamically adjust the signal transmission priority according to the real-time monitored motherboard status, ensuring that all motherboards start up smoothly and orderly even in a multi-processor server system, thus improving system stability and reliability.

[0107] The key to this technical solution lies in the LTPI module of the CPLD on the adapter board. It not only handles signal transmission between motherboards, but more importantly, through rapid response to GPIO signals and efficient processing of LTPI signals, it achieves precise control of the motherboard power-on timing. The beneficial effect of this is that regardless of the server system configuration—whether running alone, in dual-processor, or quad-processor mode—it ensures stable and efficient server operation, greatly improving server flexibility and scalability, while also simplifying system management and maintenance complexity. Through this technical solution, this invention can significantly improve the performance and user experience of multi-processor server systems in practical applications.

[0108] In one alternative implementation, Figure 7 This is an example diagram of a communication method for a multi-channel server system based on an embodiment of this application, as shown below. Figure 7 As shown, the specific steps are as follows: 1. The server is powered on. After the server starts, the adapter board CPLD begins to work. 2. Identify the number of motherboards: The adapter board CPLD determines the number of motherboards in the current server by identifying the number of valid signals of motherboards 0-3 in place. 3. Output node ID signal: The adapter board CPLD outputs node ID signals [1:0] to notify each motherboard and BMC management board of the number of motherboards in the current server. 4. Motherboard CPLD identification: Each motherboard CPLD learns the number of motherboards in the current server through the node ID signals [1:0], and learns its own position through the xth motherboard identification signal. 5. CPU setting: Each motherboard CPU sets the 0th motherboard CPU as a legacy CPU and the other motherboard CPUs as non-legacy CPUs through the hardware configuration signal according to its own position. In this invention, the CPU setting can be performed after the motherboard is installed. 6. BMC monitoring and management: The BMC learns the number of motherboards in the current server through the node ID signals [1:0], and enables the corresponding I2C channel to monitor and manage each motherboard. 7. ESPI Interface Enable: During the boot process of the legacy CPU on motherboard 0, the ESPI interface between the motherboard and its CPLD and BMC is enabled. Other motherboards disable their ESPI interfaces. 8. UPI Channel Enable and Communication: Motherboard 0 obtains the number of motherboards in the current node from the motherboard CPLD via ESPI. Based on the number of motherboards, it enables the corresponding UPI channel during boot and communicates with other motherboards via LPTI to ensure synchronized power-on timings among all motherboards.

[0109] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0110] This embodiment also provides a communication device for a multi-channel server system, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0111] Figure 8 This is a structural block diagram of the communication device of a multi-channel server system according to an embodiment of this application, such as... Figure 8 As shown, the device includes:

[0112] The signal acquisition module 802 is used to acquire an in-situ signal, which is used to indicate that the current motherboard is in normal working condition.

[0113] The signal generation module 804 is used to generate an identification signal based on the number of in-situ signals, the identification signal being used to characterize the number of motherboards currently in normal working condition;

[0114] The monitoring module 806 is used to open the corresponding UPI channel according to the identification signal and to monitor and manage the motherboard corresponding to the identification signal.

[0115] By incorporating a signal processing module and a driver module into a multi-channel server system using the aforementioned device, the control signal output to the hot-swappable device is determined based on its target turn-on time. Whether the signal is an initial hot-swappable signal or a target hot-swappable signal is determined based on the target turn-on time of the hot-swappable device. When the target turn-on time is less than or equal to a time threshold, the connection between the second input and second output terminals of the driver module is established, connecting the signal processing module to the hot-swappable device. The target hot-swappable signal controls the hot-swappable device, thereby accelerating its turn-on and shortening the power supply module branch activation time, thus improving the power supply turn-on speed of the storage system. Conversely, when the target turn-on time exceeds the time threshold, the connection between the second input and second output terminals of the driver module is deactivated, disconnecting the signal processing module from the hot-swappable device. The initial hot-swappable signal then controls the hot-swappable device, slowing its turn-on and increasing the power supply module branch activation time. This allows the control of the hot-swappable device to adapt to various operating scenarios and requirements of the storage system. Therefore, the problem of low adaptability of the power supply turn-on speed in the storage system is solved, thereby improving the overall adaptability of the power supply turn-on speed of the storage system.

[0116] In one exemplary embodiment, the apparatus further includes: a pre-configuration module, configured to configure the CPU of each motherboard via a hardware configuration signal according to a pre-set motherboard identification signal; the motherboard identification signal is used to characterize the position of the motherboard.

[0117] In one exemplary embodiment, the apparatus further includes a coordination module for coordinating the power-on timing among the motherboards.

[0118] It should be noted that the above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application. The above modules can be implemented by software or hardware. For the latter, implementation can be achieved in the following ways, but is not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0119] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0120] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0121] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0122] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0123] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0124] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0125] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

[0126] A detailed description of exemplary embodiments of this application has been provided above through exemplary and non-limiting examples. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, without departing from the scope of the invention. Therefore, the proper scope of the invention will be determined by the claims.

Claims

1. A multi-processor server system with a split-board architecture, characterized in that, The system includes: N motherboards, adapter boards, and management boards. The motherboards are interconnected, each motherboard is interconnected with the adapter board, and the adapter board is interconnected with the management board. Each of the motherboards sends an presence signal to the adapter board; the presence signal indicates that the motherboard is currently in normal working condition. The adapter board sends an identification signal to the motherboard and the management board according to the number of received presence signals, so that the management board can monitor and manage the motherboard corresponding to the identification signal; wherein, the identification signal is used to represent the number of motherboards currently in normal working condition; The first motherboard CPU in the pre-configured motherboard enables the Ultra-High Speed ​​Path Interconnect (UPI) channel corresponding to the identification signal.

2. The system according to claim 1, characterized in that, The motherboard includes: a CPU, a first complex programmable logic device, multiple first connectors, and a second connector; The adapter board includes: a clock generator, N motherboard connectors, a second complex programmable logic device, a management board connector, and multiple integrated circuit bus I2C conversion chips.

3. The system according to claim 2, characterized in that, Each of the motherboards is interconnected via the first connector to transmit UPI signals, and the motherboard is interconnected with the adapter board via the second connector; the adapter board is interconnected with the management board via the management board connector.

4. The system according to claim 2, characterized in that, The motherboard also communicates with the adapter board via a first signal, the first signal including at least one of the following: motherboard key signal, motherboard clock signal, motherboard general input / output signal, motherboard I2C signal, LTPI signal and enhanced serial peripheral interface (ESPI) signal.

5. The system according to claim 4, characterized in that, The key signals of the motherboard are transmitted to other motherboards through the motherboard connector in the adapter board.

6. The system according to claim 4, characterized in that, The motherboard clock signal, the motherboard general purpose input / output signal, the motherboard I2C signal, the LTPI signal, and the ESPI signal are transmitted to other motherboards or the management board through the second complex programmable logic device.

7. The system according to claim 2, characterized in that, The system also includes: A pre-configuration module is used to configure the CPUs in each motherboard according to a motherboard identification signal pre-set on the motherboard connector via a hardware configuration signal to determine the first motherboard CPU; the motherboard identification signal is used to characterize the position of the motherboard.

8. The system according to claim 7, characterized in that, The pre-configuration module is also used to enable the EPSI function for the first motherboard CPU and disable the EPSI function for the other motherboard CPUs.

9. The system according to claim 2, characterized in that, The clock generator produces multiple sets of clocks, which are sent to the CPUs of each motherboard through the N motherboard connectors.

10. The system according to claim 1, characterized in that, The management board includes a management board connector and a baseboard management controller.

11. The system according to claim 4, characterized in that, The adapter board also communicates with the management board via a second signal, the second signal including at least one of the following: the EPSI signal, the substrate management controller LTPI signal, the adapter board I2C signal, and the motherboard I2C signal.

12. The system according to claim 1, characterized in that, The management board is also used to enable the I2C channel corresponding to the identification signal to monitor and manage each motherboard.

13. The system according to claim 1, characterized in that, The management board is also used to monitor and manage the adapter board through the I2C channel between the management board and the adapter board.

14. The system according to claim 1, characterized in that, The first motherboard CPU communicates with the baseboard management controller of the management board via the EPSI bus to complete the boot process.

15. The system according to claim 2, characterized in that, The second complex programmable logic device is equipped with an LTPI module, which is used to coordinate the power-on timing between motherboards.

16. A communication method for a multi-channel server system with multiple servers on a separate board, characterized in that, The method is performed by any one of the multi-channel server systems according to claims 1 to 15, and the method includes: Acquire an in-situ signal, which is used to indicate that the motherboard is currently in normal working condition; An identification signal is generated based on the number of in-situ signals, and the identification signal is used to characterize the number of motherboards currently in normal working condition; The corresponding UPI channel is activated based on the identification signal, and the motherboard corresponding to the identification signal is monitored and managed.

17. The method according to claim 16, characterized in that, Also includes: The CPU of each motherboard is configured via a hardware configuration signal based on a pre-set motherboard identification signal; the motherboard identification signal is used to indicate the location of the motherboard.

18. The method according to claim 16, characterized in that, Also includes: Coordinate the power-on sequence between motherboards.

19. A communication device for a multi-channel server system, characterized in that, include: The signal acquisition module is used to acquire the presence signal, which is used to indicate that the motherboard is currently in normal working condition. A signal generation module is used to generate an identification signal based on the number of in-situ signals, the identification signal being used to characterize the number of motherboards currently in normal working condition; The monitoring module is used to activate the corresponding UPI channel based on the identification signal and to monitor and manage the motherboard corresponding to the identification signal.

20. The apparatus according to claim 19, characterized in that, Also includes: The pre-configuration module is used to configure the CPU of each motherboard according to the pre-set motherboard identification signal via hardware configuration signals; The motherboard identification signal is used to indicate the location of the motherboard.

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