Clock Synchronization in ADPLL

Abstract

Embodiments of a clock synchronization unit of an all-digital phase-locked loop (ADPLL), a successive approximation register (SAR) time-to-digital converter (TDC) of the ADPLL, and a clock synchronization method in the ADPLL are disclosed. In one embodiment, the clock synchronization unit of the ADPLL includes a dual flip-flop synchronizer, a phase frequency detector (PFD) connected to the dual flip-flop synchronizer, and a synchronization control circuit configured to control the dual flip-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal, and to control the dual flip-flop synchronizer and the PFD to perform the clock synchronization between the reference clock input signal and the divided clock input signal with PFD operation instead. Other embodiments are also described.

Description

Background Art

[0001] An all-digital phase-locked loop (ADPLL) can be used to generate a clock in digital and analog circuits. In a divider-based ADPLL, during the phase-locking phase, the reference clock and the divider clock are asynchronous with each other, and when phase locking is achieved, during the phase-tracking phase, the phase relationship between the reference clock and the divider clock is known. In a divider-based ADPLL, clock synchronization between the reference clock and the divider clock may introduce metastability and / or increase noise. For example, since the reference clock can change simultaneously with the sampling edge of the divider clock, a single flip-flop synchronizer may enter metastability during the phase-tracking phase. Summary of the Invention

[0002] Embodiments of a clock synchronization unit for an ADPLL, a successive approximation register (SAR) time-to-digital converter (TDC) for an ADPLL, and a method for clock synchronization in an ADPLL are disclosed. In one embodiment, the clock synchronization unit of the ADPLL includes a dual flip-flop synchronizer, a phase frequency detector (PFD) connected to the dual flip-flop synchronizer, and a synchronization control circuit configured to control the dual flip-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal, and to control the dual flip-flop synchronizer and the PFD to perform the clock synchronization between the reference clock input signal and the divided clock input signal with PFD operation instead.

[0003] Other embodiments are also described.

[0004] In one embodiment, the PFD operation includes generating a plurality of charge pump control signals for the charge pump unit of the ADPLL at the PFD.

[0005] In one embodiment, the synchronization control circuit is further configured to generate a synchronization control signal in response to the divided clock input signal. The dual flip-flop synchronizer includes a first flip-flop and a second flip-flop connected in series configured to be enabled by the divided clock input signal, and a first multiplexer and a second multiplexer connected to the first flip-flop and the second flip-flop and configured to select one of a plurality of inputs as an output in response to the synchronization control signal.

[0006] In one embodiment, the synchronization control circuit is further configured to generate a PFD control signal in response to the divided clock input signal. The PFD includes: a first flip-flop configured to be enabled by the reference clock input signal to generate a first charge pump control signal; a second flip-flop configured to be enabled in response to the PFD control signal to generate a second charge pump control signal; and a multiplexer configured to generate a reset signal for the first flip-flop and the second flip-flop in response to the first charge pump control signal and the second charge pump control signal.

[0007] In one embodiment, the PFD further includes an AND gate configured to generate an input for the multiplexer based on the first charge pump control signal and the second charge pump control signal.

[0008] In one embodiment, the clock synchronization unit is a component of the SAR TDC of the ADPLL. The synchronization control circuit is further configured to generate a PFD control signal in response to the divided clock input signal. The PFD includes: a first flip-flop configured to be enabled by the reference clock input signal to generate a first charge pump control signal for the charge pump unit of the SAR TDC; a second flip-flop configured to be enabled in response to the PFD control signal to generate a second charge pump control signal for the charge pump unit of the SAR TDC; a multiplexer configured to generate a reset signal for the first flip-flop and the second flip-flop in response to the first charge pump control signal and the second charge pump control signal; and an AND gate configured to generate an input for the multiplexer based on the first charge pump control signal and the second charge pump control signal.

[0009] In one embodiment, the synchronization control circuit includes a flip-flop connected to the PFD or the dual flip-flop synchronizer.

[0010] In one embodiment, the flip-flop includes: a first flip-flop and a second flip-flop connected in series and configured to be enabled by an inverted version of the divided clock input signal; a third flip-flop and a fourth flip-flop connected in series and configured to be reset by the outputs of the first flip-flop and the second flip-flop; and a fifth flip-flop configured to be enabled by an inverted version of the divided clock input signal and reset by the outputs of the first flip-flop and the second flip-flop.

[0011] In one embodiment, the synchronization control circuit further includes: a first AND gate configured to perform an AND operation on a synchronization control signal and a counter value; and a second AND gate configured to perform an AND operation on the divided clock input signal and the output of the fifth flip-flop.

[0012] In one embodiment, a SAR TDC for an ADPLL includes: a clock synchronization unit, a charge pump unit connected to the dual flip-flop synchronizer, an integrator unit connected to the charge pump unit, and a successive approximation ADC unit. The clock synchronization unit includes: a dual flip-flop synchronizer, a phase frequency detector (PFD) connected to the dual flip-flop synchronizer, and a synchronization control circuit configured to control the dual flip-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal, and to control the dual flip-flop synchronizer and the PFD to replace the execution of the clock synchronization between the reference clock input signal and the divided clock input signal with PFD operation. The charge pump unit is configured to generate a current pulse based on a time difference between the reference clock input signal and the divided clock input signal. The integrator unit is configured to generate an integrator output voltage based on the current pulse. The successive approximation ADC unit is configured to generate a digital signal based on the integrator output voltage by successive approximation.

[0013] In one embodiment, the PFD operation includes generating a charge pump control signal for the charge pump unit at the PFD.

[0014] In one embodiment, the synchronization control circuit is further configured to generate a synchronization control signal in response to the divided clock input signal. The dual flip-flop synchronizer includes a first flip-flop and a second flip-flop connected in series configured to be enabled by the divided clock input signal, and a first multiplexer and a second multiplexer connected to the first flip-flop and the second flip-flop and configured to select one of a plurality of inputs as an output in response to the synchronization control signal.

[0015] In one embodiment, the synchronization control circuit is further configured to generate a PFD control signal in response to the divided clock input signal. The PFD includes: a first flip-flop configured to be enabled by the reference clock input signal to generate a first charge pump control signal for the charge pump unit; a second flip-flop configured to be enabled in response to the PFD control signal to generate a second charge pump control signal for the charge pump unit; and a multiplexer configured to generate a reset signal for the first flip-flop and the second flip-flop in response to the first charge pump control signal and the second charge pump control signal.

[0016] In one embodiment, the PFD further includes an AND gate configured to generate an input for the multiplexer based on the first charge pump control signal and the second charge pump control signal.

[0017] In one embodiment, the synchronization control circuit includes a flip-flop connected to the PFD or the dual flip-flop synchronizer.

[0018] In one embodiment, the flip-flop includes: a first flip-flop and a second flip-flop connected in series, configured to be enabled by an inverted version of the divided clock input signal; a third flip-flop and a fourth flip-flop connected in series, configured to be reset by the outputs of the first flip-flop and the second flip-flop; and a fifth flip-flop, configured to be enabled by an inverted version of the divided clock input signal and reset by the outputs of the first flip-flop and the second flip-flop.

[0019] In one embodiment, the synchronization control circuit further includes: a first AND gate, configured to perform an AND operation on a synchronization control signal and a counter value; and a second AND gate, configured to perform an AND operation on the divided clock input signal and the output of the fifth flip-flop.

[0020] In one embodiment, a method for clock synchronization in an ADPLL includes: controlling a dual flip-flop synchronizer and a PFD connected to the dual flip-flop synchronizer to perform clock synchronization between a reference clock input signal and a divided clock input signal; and controlling the dual flip-flop synchronizer and the PFD to replace the execution of the clock synchronization between the reference clock input signal and the divided clock input signal with PFD operation.

[0021] In one embodiment, controlling the dual flip-flop synchronizer and the PFD to replace the execution of the clock synchronization between the reference clock input signal and the divided clock input signal with the PFD operation includes: controlling the dual flip-flop synchronizer and the PFD to replace the execution of the clock synchronization between the reference clock input signal and the divided clock input signal by generating a charge pump control signal for a charge pump unit of the ADPLL at the PFD.

[0022] In one embodiment, generating the charge pump control signal for the charge pump unit of the ADPLL at the PFD includes: generating the charge pump control signal at the PFD for adjusting a current source of the charge pump unit of the ADPLL.

[0023] Other aspects of the present invention will become apparent from the following detailed description in conjunction with the accompanying drawings, which illustrate by way of example the principles of the present invention. Brief Description of the Drawings

[0024] Figure 1 is a schematic block diagram of an ADPLL according to an embodiment of the present invention.

[0025] Figure 2illustrates according to an embodiment of the present invention Figure 1 the SAR TDC of the ADPLL shown.

[0026] Figure 3 illustrates according to an embodiment of the present invention Figure 2 the synchronization unit of the SAR TDC shown.

[0027] Figure 4 illustrates corresponding to Figure 3 the signal timing diagram of the synchronization unit shown.

[0028] Figure 5 is a process flow diagram showing a method for clock synchronization in a divider-based ADPLL according to an embodiment of the present invention.

[0029] Throughout the specification, like reference numerals may be used to identify like elements. Detailed Description of the Invention

[0030] It is readily understood that the components of the embodiments generally described herein and illustrated in the figures can be arranged and designed in a variety of different configurations. Thus, the following more detailed description of the various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure, but merely represents various embodiments. Although aspects of the embodiments are presented in the figures, the figures are not necessarily drawn to scale, unless specifically indicated.

[0031] Without departing from the spirit or essential characteristics of the present invention, the present invention may be embodied in other specific forms. The described embodiments are to be considered in all respects only as illustrative and not restrictive. Thus, the scope of the present invention is indicated by the appended claims rather than by this detailed description. All changes within the meaning and range of equivalents of the claims will be included within their scope.

[0032] Features, advantages, or similar language throughout this specification does not imply that all features and advantages that can be achieved with the present invention should be or are in any single embodiment of the present invention. Rather, the language referring to the features and advantages is understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, the discussions of the features and advantages throughout this specification and the similar language may, but do not necessarily, refer to the same embodiment.

[0033] In addition, the described features, advantages, and characteristics of the present invention may be combined in any suitable manner in one or more embodiments. Based on the description herein, those skilled in the relevant art will recognize that the present invention may be practiced without one or more specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not exist in all embodiments of the present invention.

[0034] The phrase "in one embodiment", "an embodiment", or similar language throughout this specification means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Thus, the phrases "in one embodiment", "in an embodiment", and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0035] Figure 1 is a schematic block diagram of an ADPLL 180 according to an embodiment of the present invention. In Figure 1 the illustrated embodiment, the ADPLL includes a successive approximation register (SAR) time-to-digital converter (TDC) 100, a quantization noise cancellation unit 110, a digital loop filter 120, a numerically controlled oscillator (DCO) 130, a frequency divider 140, and a digital control unit 150. In some embodiments, the ADPLL is used to compare the phase of a reference signal with the phase of a signal derived from the output signal of the ADPLL and to adjust the DCO to maintain phase matching between the two signals. The ADPLL can be used in communication, computer, and other electronic applications. Although the ADPLL shown herein has certain components and describes certain functions, other embodiments of the ADPLL may include fewer or more components to achieve the same, fewer, or more functions.

[0036] In Figure 1 the illustrated embodiment, the SAR TDC 100 receives a divided clock input signal 107 from the frequency divider 140 and a reference clock input signal 101. The SAR TDC is configured to determine the time difference between the reference clock input signal and the divided clock input signal. In some embodiments, the SAR TDC generates a sampled reference clock signal 108 and / or a normalized SAR TDC output 109 based on the time difference between the reference clock input signal and the divided clock input signal.

[0037] In Figure 1In the illustrated embodiment, the quantization noise cancellation unit 110 is configured to reduce or eliminate divider quantization noise. The output of the quantization noise cancellation unit is a phase error signal 132, which is provided to the digital loop filter 120. In some embodiments, the result of adding the phase offset signal 102 to the normalized SAR TDC output 109 from the SAR TDC 100 is provided to the quantization noise cancellation unit to reduce or eliminate divider quantization noise in the digital domain.

[0038] In Figure 1 the illustrated embodiment, the digital loop filter 120 is configured to convert the phase error signal 132 into a digital output to control the DCO 130. The DCO 130 is configured to generate an output signal 106 as the output of the ADPLL.

[0039] In Figure 1 the illustrated embodiment, the divider 140 is configured to receive the output signal 106 of the DCO 130 and divide the frequency of the output signal 106 to generate a divided clock input signal 107, whose frequency is a fraction of the frequency of the output signal 106.

[0040] In Figure 1 the illustrated embodiment, the digital control unit 150 is configured to control the SAR TDC 100, the quantization noise cancellation unit 110, and / or the divider 140. The digital control unit can be implemented as a digital signal processor (DSP), a microcontroller, or a central processing unit (CPU). In some embodiments, the digital control unit includes a Σ-Δ modulator. In Figure 1 the illustrated embodiment, the digital control unit provides a synchronization control signal 121 to the SAR TDC based on the normalized tuning word (NTW) 103, a division value 105 to the divider, and an accumulated Σ-Δ error 104 to the quantization noise cancellation unit 110. In some embodiments, the digital control unit receives a sampled reference clock signal 108 from the SAR TDC and a divided clock input signal 107 from the divider 140.

[0041] Figure 2 is a schematic block diagram of an SAR TDC 200 according to an embodiment of the present invention. Figure 2 The illustrated SAR TDC 200 is Figure 1 an embodiment of the illustrated SAR TDC 100. However, Figure 1 the depicted SAR TDC 100 is not limited to Figure 2 the illustrated embodiment. In Figure 2In the illustrated embodiment, the SAR TDC 200 includes a synchronization unit 222, a charge pump (CP) unit 224, an integrator unit 226, a switching unit 227, and a successive approximation analog-to-digital converter (ADC) unit 228.

[0042] In Figure 2 the illustrated embodiment, a reference clock input signal 101 and a divided clock input signal 107 from a divider 140 of the illustrated ADPLL 180 are provided to the synchronization unit 222. In some embodiments, the synchronization unit converts the time difference between the periods of the reference clock input signal and the divided clock input signal into output signals 242, 244, the durations of which are based on the time difference between the respective periods of the reference clock input signal and the divided clock input signal. Figure 1 In

[0043] In Figure 2 the illustrated embodiment, the charge pump unit 224 is connected to the clock synchronization unit 222 and includes "upward" current sources 232, 234 driven by the signal 244, and at least two "downward" current sources (not shown) driven by the signal 242. The charge pump unit is configured to generate current pulses based on the time difference between the reference clock input signal 101 and the divided clock input signal 107. In Figure 2 the illustrated embodiment, the charge pump unit converts the signals 242, 244 into an output current pulse 246 in response to an input charge pump control signal 113.

[0044] In Figure 2 the embodiment depicted, the integrator unit 226 is connected to the charge pump unit 224 and is configured to generate an integrator output voltage based on the output current pulse 246. The integrator unit may include a transconductance amplifier 252 having feedback capacitors represented by capacitors 254, 256. In Figure 2In the illustrated embodiment, the output current pulses 246 from the charge pump unit are respectively connected to the non-inverting and inverting input terminals of a transconductance amplifier, which integrates the charges on capacitors 254, 256. The transconductance amplifier includes an inverting output 215a and a non-inverting output 215b, and the difference between the inverting and non-inverting outputs is the integrator output voltage 215. The integrator output voltage from the transconductance amplifier depends on the integration of the output current pulses from the charge pump unit. The output from the integrator unit is provided to the successive approximation ADC unit 228, which is configured to convert the integrated charges on capacitors 254, 256 into a normalized SAR TDC output 109 by successive approximation. The successive approximation ADC unit can be implemented with one or more logic circuits. In some embodiments, the successive approximation ADC unit includes at least one comparator, at least one AND gate, at least one control logic, at least one flip-flop, at least one exclusive OR (XOR) gate, at least one digital-to-analog converter (DAC), and / or at least one shift register. The switch unit 227 is configured to connect or disconnect the successive approximation ADC unit from the input of the transconductance amplifier 252. In some embodiments, the switch unit includes at least two switches 260, 262.

[0045] Figure 3 is a schematic block diagram of a synchronization unit 322 according to an embodiment of the present invention. Figure 3 The illustrated synchronization unit 322 is Figure 2 an embodiment of the illustrated synchronization unit 222. However, Figure 2 the depicted synchronization unit 222 is not limited to Figure 3 the illustrated embodiment. In Figure 3 the illustrated embodiment, the synchronization unit 322 includes a dual flip-flop synchronizer 362, a phase frequency detector (PFD) 364, and a synchronization control circuit 366.

[0046] In Figure 3In the illustrated embodiment, the synchronization unit 322 is selected / controlled by the synchronization control circuit 366 and operates in a phase-locked state and a phase-tracking state. During the phase-locked state, the divided clock input signal (clk_div) 107 is used for synchronization with the reference clock input signal (fref) 101. During the phase-tracking state, the synchronization between the reference clock input signal (fref) 101 and the divided clock input signal (clk_div) 107 is replaced by PFD operation under the control of the synchronization control circuit. In some embodiments, the PFD operation involves generating a charge pump control signal for the charge pump unit 224 of the SAR TDC 200 at the PFD 364. In one embodiment, the PFD operation involves generating charge pump control signals 242, 244 at the PFD to control and / or adjust the current sources of the charge pump unit. For example, the PFD operation may involve generating charge pump control signals 242, 244 at the PFD to control or adjust the "up" current sources 232, 234 and the "down" current sources of the charge pump unit to set the effective CP current of the charge pump unit (e.g., increase or decrease the effective CP current of the charge pump unit). In Figure 3 In the illustrated embodiment, the positive and negative time differences between the reference clock input signal (fref) 101 and the divided clock input signal (clk_div) 107 can be measured in the phase-tracking state.

[0047] The dual flip-flop synchronizer 362 of the synchronization unit 322 includes two serially-connected flip-flops 368, 370, two multiplexers 372, 374, and an OR gate 376. In Figure 3In the depicted embodiment, the flip - flops 368, 370 are configured to be enabled by the divided - clock input signal (clk_div) 107 and sample the reference - clock input signal (fref) 101 to generate the sampled reference - clock signal (clk_ref_sample) 108. The multiplexers 372, 374 are connected to the first flip - flop 368 and the second flip - flop 370 and are configured to select one of two inputs as an output in response to the synchronization control signal (ctl_en_pfd_mode) 381 received by the synchronization control circuit 366. A single - flip - flop synchronizer is prone to metastability problems. For example, since the reference - clock input signal (fref) 101 may change simultaneously with the sampling edge of the divided - clock input signal (clk_div) 107, a single - flip - flop synchronizer may enter metastability during the phase - tracking phase. Compared with a single - flip - flop synchronizer that is prone to metastability problems, a dual - flip - flop synchronizer has better resistance to metastability due to the additional divided - clock periods used for synchronization. In some embodiments, during the phase - lock phase, the phase - offset signal 102 is increased to accommodate the additional divided - clock periods for synchronization. In the phase - locked state, only the signal (cp_up) 244 for driving the "up" current sources 232, 234 of the charge - pump unit 224 is generated (i.e., the signal 242 is zero).

[0048] The phase - frequency detector (PFD) 364 of the synchronization unit 322 includes two flip - flops 378, 380, a multiplexer 382, and an AND gate 384. The flip - flop 378 is configured to be enabled by the reference - clock input signal (fref) 101 to generate the cp_up signal 244 for the charge - pump unit 224. The flip - flop 380 is configured to be enabled in response to the synchronization control signal (ctl_en_pfd_mode) 381 to generate the cp_down signal 242 for the charge - pump unit. The multiplexer 382 is configured to generate a reset signal 379 for the flip - flops 378, 380 in response to the cp_up signal 242 and the cp_down signal 244. The signal edge (e.g., rising edge) of the sampled reference - clock signal (clk_ref_sample) 108 then resets the flip - flop 378. The effective CP current en_cp is a combination of the cp_up signal 244 and the cp_down signal 242. In some embodiments, the effective CP current en_cp can be expressed as: en_cp = cp_up XOR cp_down. The AND gate 384 is configured to generate an input for the multiplexer based on the cp_up signal 244 and the cp_down signal 242.

[0049] The synchronization control circuit 366 of the synchronization unit 322 includes five flip - flops 386, 388, 390, 392, 394, two AND gates 396, 398, and comparator logic 399. The flip - flops 386, 388 synchronize the removal of the reset of the asynchronous reset signal rstasync on the falling edge of the divided - clock input signal (clk_div) 107. The flip - flops 390, 392 synchronize the change of the ctl_en_pfd_mode signal with the falling edge of the clk_ref_sample signal (the clk_ref_sample transition is aligned with the rising edge of the clk_div clock). The flip - flop 394 is configured to be triggered by the falling edge of the divided - clock input signal (clk_div) 107 and reset by the output of the flip - flop 388. The AND gate 396 is configured to perform an AND operation on the synchronization control signal (ctl_en_pfd_mode) 381 and the output of the comparator logic 399. The output of the comparator logic 399 is the comparison result between the internal counter div_counter 385 and the count target clk_div_gate_code 387. The AND gate 398 is configured to perform an AND operation on the divided - clock input signal (clk_div) 107 and the output of the flip - flop 394.

[0050] In an example of the operation of the synchronization control circuit 366, during the phase - locked state, the divided - clock input signal (clk_div) 107 is gated by the synchronization control signal (ctl_en_pfd_mode) 381, which is valid on the falling edge of the divided - clock input signal (clk_div) 107, thereby generating a PFD input signal (clk_div_pfd) 389 for the phase - frequency detector (PFD) 364. During the phase - tracking state, the signal (cp_up) 244 and the signal (cp_down) 242 are generated. The effective CP current is proportional to en_cp = cp_up XOR cp_down. During the phase - locked state, the synchronization control signal (ctl_en_pfd_mode) 381 also affects the generation of the sampled reference - clock signal (clk_ref_sample) 108. During the switching between the locked and tracking states, the count target (clk_div_gate_code) 387 of the internal counter (div_counter) 385 is temporarily decremented by 1 and restored to its previous value in the next cycle. During the phase - tracking state, the adjustable phase - offset signal 102 can be adjusted to only fit within the range of the divider ∑ - Δ modulator. Thus, the CP signal has a minimum length (no time is required for synchronization). The minimum length of the CP reduces the integrated CP noise and improves the in - band noise floor of the ADPLL 180.

[0051] Figure 4 is shown corresponding toFigure 3 The signal timing diagram of the synchronization unit 322 shown. In Figure 4 the signal timing diagram shown, a reference clock input signal (fref) 101, a PFD input signal (clk_div_pfd) 389, a divided clock input signal (clk_div) 107, an internal counter div_counter 385, a signal (cp_up) 244, an active CP current (en_cp) 448, a signal (cp_down) 242, a sampled reference clock signal (clk_ref_sample) 108, a processed synchronization control signal (ctl_en_pfd_mode_sync) 383, a count target (clk_div_gate_code) 387, and a phase offset signal 102 during the phase-locked state (before time point t7) and the phase tracking state (after time point t7) are shown. For a given frequency channel, a fixed number of divider periods are suitable for one reference clock period of the reference clock input signal (fref) 101. For example, in Figure 4 the signal timing diagram shown, each clock period of the reference clock input signal (fref) 101 is equal to five clock periods of the divided clock input signal (clk_div) 107. However, in other embodiments, each clock period of the reference clock input signal (fref) 101 is equal to more than five or less than five clock periods of the divided clock input signal (clk_div) 107. The switching between the locked and tracking states is controlled by the ctl_en_pfd_mode signal. The ctl_en_pfd_mode is asserted on the rising edge of the clk_ref_sample clock.

[0052] In Figure 4 the signal timing diagram shown, during the phase-locked state (before time point t7), the divided clock input signal (clk_div) 107 is used for the synchronization of the reference clock input signal (fref) 101. During the phase tracking state (after time point t7), under the control of the synchronization control circuit 366, the execution of the synchronization between the reference clock input signal (fref) 101 and the divided clock input signal (clk_div) 107 is replaced by PFD operation.

[0053] At time point t0, the reference clock input signal (fref) 101 changes from 0 to 1, causing the flip - flop 378 to change its output from 0 to 1 at the rising edge of the reference clock input signal (fref) 101. Consequently, the signal (cp_up) 244 and the active CP current (en_cp) 448 change from 0 to 1 at time point t0. At time point t0, the processed synchronous control signal (ctl_en_pfd_mode_sync) 383 is at logic 0. Thus, the multiplexer 372 of the dual - flip - flop synchronizer 362 selects its input at the input terminal "0" (which is the signal (cp_up) 244) as its output.

[0054] At time point t1, the divided - frequency clock input signal (clk_div) 107 changes from 0 to 1, and the flip - flop 368 sets its output to the same value as its input (i.e., sets its output to 1) at the rising edge of the divided - frequency clock input signal (clk_div) 107.

[0055] At time point t2, the divided - frequency clock input signal (clk_div) 107 changes from 0 to 1 again, and the flip - flop 370 sets its output to the same value as its input (i.e., sets its output to 1) at the rising edge of the divided - frequency clock input signal (clk_div) 107. At time point t2, the processed synchronous control signal (ctl_en_pfd_mode_sync) 383 is at logic 0. Thus, the multiplexer 374 of the dual - flip - flop synchronizer 362 selects its input at the input terminal "0" (which is the output of the flip - flop 370) as its output, and the sampled reference clock signal (clk_ref_sample) 108 changes from 0 to 1. Additionally, the multiplexer 382 of the phase - frequency detector (PFD) 364 selects the input at the input terminal "0" (which is the output of the flip - flop 370) as its output, and the flip - flops 378, 380 of the PFD are reset. Consequently, the signal (cp_up) 244 and the active CP current (en_cp) 448 change from 1 to 0 at time point t2. After two consecutive rising edges of the divided - frequency clock input signal (clk_div) 107, the sampled reference clock signal (clk_ref_sample) 108 changes from 1 to 0 at time point t3.

[0056] At time point t4, the reference clock input signal (fref) 101 changes from 0 to 1 again, the processed synchronous control signal (ctl_en_pfd_mode_sync) 383 remains at logic 0, and thus, the multiplexer 372 of the dual - flip - flop synchronizer 362 selects its input at the input terminal "0" (which is the signal (cp_up) 244) as its output.

[0057] At time point t5, the divided clock input signal (clk_div) 107 changes from 0 to 1 for the second time after time point t4, and the flip-flop 370 sets its output to the same value as its input (i.e., sets its output to 1) at the rising edge of the divided clock input signal (clk_div) 107. At time point t5, the processed synchronization control signal (ctl_en_pfd_mode_sync) 383 is still at logic 0, and thus the multiplexer 374 of the dual flip-flop synchronizer 362 selects its input at input terminal "0" (which is the output of the flip-flop 370) as its output. And the sampled reference clock signal (clk_ref_sample) 108 changes from 0 to 1. Additionally, the multiplexer 382 of the phase frequency detector (PFD) 364 selects the input at input terminal "0" (which is the output of the flip-flop 370) as its output, and the flip-flops 378, 380 of the PFD are reset. Therefore, the signals (cp_up) 244 and the effective CP current (en_cp) 448 change from 1 to 0 at time point t5. After two consecutive rising edges of the divided clock input signal (clk_div) 107, the sampled reference clock signal (clk_ref_sample) 108 changes from 1 to 0 at time point t6.

[0058] At time point t5, assert the clt_en_pfd_mode signal. The synchronization mode change is delayed until time point t7. At time point t7, the phase-locked state ends, and the phase tracking state begins, and the processed synchronization control signal (ctl_en_pfd_mode_sync) 383 changes from 0 to 1.

[0059] At time point t8, the reference clock input signal (fref) 101 changes from 0 to 1, causing the flip-flop 378 to change its output from 0 to 1 at the rising edge of the reference clock input signal (fref) 101. Therefore, the signals (cp_up) 244 and the effective CP current (en_cp) 448 change from 0 to 1. At time point t8, the processed synchronization control signal (ctl_en_pfd_mode_sync) 383 is at logic 1, and thus the multiplexer 372 of the dual flip-flop synchronizer 362 selects its input at input terminal "1" (which is the signal (ctl_en_clk_div_pfd) 391 from the flip-flop 394) as its output.

[0060] At time point t9, the divided clock input signal (clk_div) 107 changes from 0 to 1, and the flip-flop 368 sets its output to the same value as its input (i.e., sets its output to 1) at the rising edge of the divided clock input signal (clk_div) 107. At time point t9, the processed synchronous control signal (ctl_en_pfd_mode_sync) 383 is at logic 1, and thus the multiplexer 374 of the dual flip-flop synchronizer 362 selects its input at the input terminal "1" (i.e., the output of the OR gate 376) as its output. And the sampled reference clock signal (clk_ref_sample) 108 changes from 0 to 1. In addition, at time point t9, the PFD input signal (clk_div_pfd) 389 changes from 0 to 1, causing the flip-flop 380 to change its output from 0 to 1 at the rising edge of the PFD input signal (clk_div_pfd) 389. Therefore, the signal (cp_down) 242 changes from 0 to 1. The effective CP current (en_cp) 448 changes from 1 to 0.

[0061] At time point t10, the multiplexer 382 of the PFD 364 selects the input at the input terminal "1" (which is the output of the AND gate 384) as its output, and the flip-flops 378 and 380 of the PFD are both reset. Therefore, at time point t10, both the signal (cp_up) 244 and the signal (cp_down) 242 change from 1 to 0.

[0062] At time point t9, the div_counter signal 385 is different from the clk_div_gate_code signal 387 and the ctl_en_clk_div_pfd signal 391 and changes from 1 to 0 at the next falling edge (time point t11) of the divided clock input signal (clk_div) 107. The PFD input signal (clk_div_pfd) 389 changes from 1 to 0. After two consecutive rising edges of the divided clock input signal (clk_div) 107, the sampled reference clock signal (clk_ref_sample) 108 changes from 1 to 0 at time point t12.

[0063] Figure 5 is a flowchart showing a method for clock synchronization in a divider-based all-digital phase-locked loop (ADPLL) according to an embodiment of the present invention. The divider-based ADPLL can be used with a reference Figure 1-3is the same as or similar to the ADPLL. At block 502, control the dual flip-flop synchronizer and the phase frequency detector (PFD) connected to the dual flip-flop synchronizer to perform clock synchronization between the reference clock input signal and the divided clock input signal. At block 504, control the dual flip-flop synchronizer and the PFD (e.g., via the synchronization control circuit 366) to perform the operation of the PFD instead of the execution of clock synchronization between the reference clock input signal and the divided clock input signal.

[0064] In the foregoing description, specific details of various embodiments are provided. However, some embodiments may be practiced with less than all of these specific details. In other instances, for the sake of brevity and clarity, the description of certain methods, processes, components, structures, and / or functions is not more detailed than is necessary to implement the various embodiments of the present invention.

[0065] Although the operations of the methods herein are shown and described in a particular order, the order of the operations of each method may be changed such that some operations may be performed in an opposite order, or such that some operations may be performed at least partially concurrently with other operations. In another embodiment, the instructions or sub-operations of different operations may be implemented in an intermittent and / or alternating manner.

[0066] Alternatively, embodiments of the present invention may be implemented entirely in hardware, or in an implementation that includes both hardware and software elements. In embodiments using software, the software may include, but is not limited to, firmware, resident software, microcode, and the like.

[0067] Although specific embodiments of the present invention have been described and illustrated, the present invention is not limited to the specific forms or arrangements of the parts so described and illustrated. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A clock synchronization unit for an all-digital phase-locked loop ADPLL, characterized in that, The clock synchronization unit includes: A dual flip-flop synchronizer; A phase frequency detector PFD connected to the dual flip-flop synchronizer; and A synchronization control circuit configured to control the dual flip-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal, and to control the dual flip-flop synchronizer and the PFD to perform the PFD operation instead of the execution of the clock synchronization between the reference clock input signal and the divided clock input signal, wherein the synchronization control circuit is configured to: In the phase locked state, control the dual flip-flop synchronizer and the PFD to perform clock synchronization between the reference clock input and the divided clock input signal using the divided clock input signal; In the phase tracking state, control the dual flip-flop synchronizer and the PFD to perform the PFD operation instead of performing clock synchronization between the reference clock input and the divided clock input signal using the divided clock input signal; Wherein the synchronization control circuit is further configured to generate a synchronization control signal in response to the divided clock input signal, wherein the dual flip-flop synchronizer is configured to be started by the divided clock input signal and to select one of a plurality of inputs as an output in response to the synchronization control signal.

2. The clock synchronization unit according to claim 1, characterized in that, The PFD operation includes generating a plurality of charge pump control signals for the charge pump unit of the ADPLL at the PFD.

3. The clock synchronization unit according to claim 1, characterized in that, Wherein the dual flip-flop synchronizer includes a first flip-flop and a second flip-flop connected in series configured to be enabled by the divided clock input signal, and wherein the dual flip-flop synchronizer further includes a first multiplexer and a second multiplexer connected to the first flip-flop and the second flip-flop and configured to select one of a plurality of inputs as an output in response to the synchronization control signal.

4. The clock synchronization unit according to claim 1, characterized in that, The synchronization control circuit is further configured to generate a PFD control signal in response to the divided clock input signal, and wherein the PFD includes: A first flip-flop configured to be enabled by the reference clock input signal to generate a first charge pump control signal; A second flip-flop configured to be enabled in response to the PFD control signal to generate a second charge pump control signal; and A multiplexer configured to generate a reset signal for the first flip-flop and the second flip-flop in response to the first charge pump control signal and the second charge pump control signal.

5. The clock synchronization unit according to claim 4, characterized in that, The PFD further includes an AND gate configured to generate an input for the multiplexer based on the first charge pump control signal and the second charge pump control signal.

6. The clock synchronization unit according to claim 1, characterized in that, The clock synchronization unit is a component of a successive approximation register SAR time-digital converter TDC of the ADPLL, wherein the synchronization control circuit is further configured to generate a PFD control signal in response to the divided clock input signal, and wherein the PFD includes: A first flip-flop configured to be enabled by the reference clock input signal to generate a first charge pump control signal for a charge pump unit of the SAR TDC; A second flip-flop configured to be enabled in response to the PFD control signal to generate a second charge pump control signal for the charge pump unit of the SAR TDC; A multiplexer configured to generate a reset signal for the first flip-flop and the second flip-flop in response to the first charge pump control signal and the second charge pump control signal; and An AND gate configured to generate an input for the multiplexer based on the first charge pump control signal and the second charge pump control signal.

7. The clock synchronization unit according to claim 1, characterized in that, The synchronization control circuit includes a plurality of flip-flops connected to the PFD or the dual flip-flop synchronizer.

8. The clock synchronization unit according to claim 7, characterized in that, The flip-flops include: A first flip-flop and a second flip-flop connected in series, configured to be enabled by an inverted version of the divided clock input signal; A third flip-flop and a fourth flip-flop connected in series, configured to be reset by the outputs of the first flip-flop and the second flip-flop; and A fifth flip-flop configured to be enabled by an inverted version of the divided clock input signal and reset by the outputs of the first flip-flop and the second flip-flop.

9. A successive approximation register SAR time-to-digital converter TDC for an all-digital phase-locked loop ADPLL, characterized in that, The SAR TDC includes: A clock synchronization unit, which includes: A dual flip-flop synchronizer; A phase frequency detector PFD connected to the dual flip-flop synchronizer; and A synchronization control circuit configured to control the dual flip-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal, and control the dual flip-flop synchronizer and the PFD to replace the execution of the clock synchronization between the reference clock input signal and the divided clock input signal with PFD operation; A charge pump unit connected to the clock synchronization unit and configured to generate a current pulse based on a time difference between the reference clock input signal and the divided clock input signal; An integrator unit connected to the charge pump unit and configured to generate an integrator output voltage based on the current pulse; and A successive approximation analog-to-digital converter ADC unit configured to generate a digital signal based on successive approximation of the integrator output voltage; Wherein the synchronization control circuit is configured to: In a phase-locked state, control the dual flip-flop synchronizer and the PFD to perform clock synchronization between the reference clock input and the divided clock input signal using the divided clock input signal; In a phase-tracking state, control the dual flip-flop synchronizer and the PFD to replace the execution of clock synchronization between the reference clock input and the divided clock input signal with PFD operation; Wherein the synchronization control circuit is further configured to generate a synchronization control signal in response to the divided clock input signal, wherein the dual flip-flop synchronizer is configured to be started by the divided clock input signal and select one of a plurality of inputs as an output in response to the synchronization control signal.

10. A method for clock synchronization in an all-digital phase-locked loop ADPLL, characterized in that, The method includes: Control a dual flip-flop synchronizer and a phase frequency detector (PFD) connected to the dual flip-flop synchronizer to perform clock synchronization between a reference clock input signal and a divided clock input signal; and Control the dual flip-flop synchronizer and the PFD to perform the PFD operation instead of the execution of the clock synchronization between the reference clock input signal and the divided clock input signal; In a phase-locked state, control the dual flip-flop synchronizer and the PFD to perform clock synchronization between the reference clock input and the divided clock input signal using the divided clock input signal; In a phase-tracking state, control the dual flip-flop synchronizer and the PFD to perform the PFD operation instead of performing clock synchronization between the reference clock input and the divided clock input signal using the divided clock input signal; Wherein, in response to the divided clock input signal, the method further comprises: Generating a synchronization control signal; Starting with the divided clock input signal; Selecting one of a plurality of inputs as an output in response to the synchronization control signal.

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