Analog-to-digital conversion circuit based on VTC and TDC and oriented to RRAM storage and calculation integrated chip

Abstract

The invention relates to an analog-to-digital conversion circuit based on VTC and TDC for an RRAM storage and calculation integrated chip, and the circuit comprises a first comparator which is used for comparing an input first voltage signal with a first reference signal, so as to output a first digital signal; the charge pump is used for receiving the first digital signal as an enable voltage, performing voltage reduction on an input first voltage signal under the enable voltage and outputting a second voltage signal; the voltage-time converter is used for mapping the second voltage signal into a time domain signal; and a time-to-digital converter for mapping the time domain signal into a second digital signal and outputting the first digital signal and the second digital signal as a combination. The whole input voltage range is folded once through the two-stage structure, the linear input interval and performance of the VTC under the large input voltage are optimized through the charge pump and the self-bias low-voltage cascode current mirror, and the time domain analog-to-digital conversion circuit with the wide input range and high precision is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular, to an analog-to-digital conversion circuit based on VTC and TDC for RRAM computing-in-memory chips. Background Art

[0002] With the rapid development of artificial intelligence and large model technologies and the extensive expansion of their application fields, massive data and huge model parameters pose strong and efficient demands on hardware computing power. The storage units in the computing-in-memory structure perform data storage while performing data calculations, breaking through the bottleneck of the "memory wall" caused by the separation of storage units and computing units in the von Neumann architecture, which is beneficial to improving computing efficiency and enhancing hardware computing power. In recent years, resistive random access memory (RRAM), which has characteristics such as low power consumption, high speed, and non-volatility, has received extensive attention and shown great potential in the computing-in-memory structure. The memristor array of the RRAM-based computing-in-memory chip consists of memristors and transistors. The role of the memristor is to store information through the high and low resistance values of the device, and the role of the transistor is to control the opening of the memristor. Based on Kirchhoff's current law, the input voltage signal is converted into a multiply-accumulate current through the transconductance of the memristor array, and the multiply-accumulate current is converted into a digital signal through the analog-to-digital conversion circuit. The magnitudes of the multiply-accumulate currents generated by turning on different numbers and different resistance values of the memristor array units are different. Considering the low accuracy of the multiply-accumulate current, the multiply-accumulate current is generally converted into a voltage and then quantified using an analog-to-digital conversion circuit. The requirements for wide input range and high-precision conversion increase the area and cost of the analog-to-digital conversion circuit, becoming a bottleneck restricting the improvement of computing performance.

[0003] According to different signal processing methods, analog-to-digital conversion circuits are divided into the voltage domain and the time domain. The voltage-domain analog-to-digital conversion circuit discretizes and quantifies the continuous voltage amplitude, and can achieve relatively high precision within a certain range. However, with the progress of semiconductor technology and the reduction of the supply voltage, the difficulty of achieving high precision increases. The time-domain analog-to-digital conversion circuit emerges as the times require. Its working principle is to convert the input voltage signal into a time quantity and then convert the time quantity into a digital output. Its conversion process is mainly based on digital logic, and has high resolution and anti-interference ability. The traditional time-domain analog-to-digital conversion circuit mainly consists of a voltage-to-time converter VTC and a time-to-digital converter TDC. The VTC converts the voltage signal into a time signal with different pulse widths, and the TDC converts it into a digital signal. The main reason restricting the wide input range and high-precision application of the time-domain analog-to-digital conversion circuit is the non-linearity problem of the VTC. This is because the resistance of the current mirror in the actual VTC is a finite value, resulting in a limited input linear range, thus restricting the time-domain conversion accuracy. Therefore, it is crucial to design a time-domain analog-to-digital conversion circuit with a wide input range and high precision.

[0004] Currently, there is no effective solution to the problem that the input linear range is limited in the related technology, thus restricting the time-domain conversion accuracy. Summary of the Invention

[0005] In view of this, it is necessary to provide an analog-to-digital conversion circuit based on VTC and TDC for RRAM memory-computation integrated chips and an RRAM memory-computation integrated chip to solve the problem that the input linear range is limited in the related technology, thus restricting the time-domain conversion accuracy.

[0006] The present invention provides an analog-to-digital conversion circuit based on VTC and TDC for RRAM memory-computation integrated chips, including a two-stage structure for folding the input voltage range; the first-stage structure includes a first comparator; the second-stage structure includes a charge pump, a voltage-to-time converter, and a time-to-digital converter; The first comparator is connected to the charge pump and is used to compare the input first voltage signal and the first reference signal to output a first digital signal; The charge pump is connected to the voltage-to-time converter and is used to receive the first digital signal as an enable voltage, step down the input first voltage signal under the enable voltage, and output a second voltage signal; The voltage-to-time converter is connected to the time-to-digital converter and is used to map the second voltage signal into a time-domain signal; The time-to-digital converter is used to map the time-domain signal into a second digital signal and output the first digital signal and the second digital signal as a combined output.

[0007] In one embodiment, the first comparator compares the first voltage signal and the first reference signal to output the first digital signal, and at the same time, the first digital signal is used as the charge pump enable voltage control; wherein, the first reference signal is half of the supply voltage, corresponding to folding the input voltage range in half.

[0008] In one embodiment, the charge pump includes an enable voltage control unit, a capacitor C1, a capacitor C2, a diode D1, and a diode D2; The enable voltage control unit is disposed between one end of the capacitor C1 and the output end of the first comparator; The other end of the capacitor C1 is respectively connected to the anode of the diode D1 and the cathode of the diode D2; The cathode of the diode D1 is connected to the positive input terminal of the first comparator; The anode of the diode D2 is respectively connected to one end of the capacitor C2 and the voltage-to-time converter; The other end of the capacitor C2 is grounded.

[0009] In one embodiment, the voltage-time converter includes a sample-and-hold module, a second comparator, a current mirror module, and a logic circuit; The sample-and-hold module is disposed between the charge pump and the negative input terminal of the second comparator, and is configured to sample and hold the second voltage signal; The positive input terminal of the second comparator is connected to the current mirror module, and the output terminal of the second comparator is connected to the logic circuit, and is configured to receive the second voltage signal and the capacitor voltage signal generated by charging of the current mirror module, and compare the second voltage signal and the capacitor voltage signal to output a third voltage signal; The logic circuit is configured to determine the time-domain signal according to the third voltage signal and the clock signal; the pulse width of the time-domain signal is proportional to the amplitude of the second voltage signal.

[0010] In one embodiment, the charging current of the capacitor C3 in the voltage-time converter is provided by a self-biased low-voltage cascode current mirror; the self-biased low-voltage cascode current mirror biases the gate voltage of the cascode transistor through a resistor.

[0011] In one embodiment, the reference current in the voltage-time converter is generated by a bandgap reference circuit and a voltage-to-current circuit; The bandgap reference circuit is connected to the voltage-to-current circuit and is configured to generate a reference voltage with a low temperature coefficient; The voltage-to-current circuit is configured to convert the reference voltage into a reference current according to a preset ratio.

[0012] In one embodiment, the logic circuit is a phase detector.

[0013] In one embodiment, the time-to-digital converter includes a delay unit and a D flip-flop; The delay unit and the D flip-flop form a delay line structure, and quantize the pulse width of the time-domain signal into a digital value to output the second digital signal.

[0014] In one embodiment, the first digital signal output by the first-stage structure and the second digital signal output by the second-stage structure are output after being combined by a multiplexer and an encoder.

[0015] In a second aspect, an RRAM memory-computation integrated chip provided by an embodiment of the present application includes the analog-to-digital conversion circuit based on VTC and TDC for the RRAM memory-computation integrated chip as described in the first aspect above; the analog-to-digital conversion circuit serves as the readout circuit of the RRAM memory-computation integrated chip.

[0016] In this embodiment, the built-in analog-to-digital conversion circuit serves as the readout circuit of the RRAM memory and computing integrated chip; the two-stage structure of the analog-to-digital conversion circuit folds the entire input voltage range, enabling the circuit structure reuse of a single VTC and a single TDC under a wide input range, which has the advantage of reducing the circuit layout area. As the readout circuit of the RRAM memory and computing integrated chip, it quantifies and outputs the resistance values of the memristor arrays with different numbers and different resistance values turned on.

[0017] The analog-to-digital conversion circuit based on VTC and TDC for the RRAM memory and computing integrated chip provided by the present invention, wherein the analog-to-digital conversion circuit includes a first comparator, a charge pump, a voltage-to-time converter, and a time-to-digital converter; the first comparator is connected to the charge pump and is used to compare the input first voltage signal and the first reference signal to output a first digital signal; the charge pump is connected to the voltage-to-time converter and is used to receive the first digital signal as the enable voltage, step down the input first voltage signal under the enable voltage, and output a second voltage signal; the voltage-to-time converter is connected to the time-to-digital converter and is used to map the second voltage signal into a time-domain signal; the time-to-digital converter is used to map the time-domain signal into a second digital signal and use the first digital signal and the second digital signal as a combined output. The analog-to-digital conversion circuit of this application uses a two-stage structure to fold the entire input voltage range once, and through the self-biased low-voltage cascode current mirror in the charge pump and the voltage-to-time converter, optimizes the linear input range and performance of the voltage-to-time converter under a large input voltage, solves the problem that the conversion accuracy is limited by the non-linear characteristics of the voltage-to-time converter, and realizes a time-domain analog-to-digital conversion circuit with a wide input range and high precision. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural block diagram of an analog-to-digital conversion circuit based on VTC and TDC for the RRAM memory and computing integrated chip provided by an embodiment of the present invention; Figure 2 It is a circuit schematic diagram of a charge pump provided by an embodiment of the present invention; Figure 3 It is a circuit schematic block diagram of a voltage-to-time converter provided by an embodiment of the present invention; Figure 4 It is a circuit schematic diagram of a voltage-to-time converter provided by an embodiment of the present invention.

[0019] Reference numerals: 10, first comparator; 20, charge pump; 30, voltage-to-time converter; 31, reference current mirror; 32, self-biased low-voltage cascode current mirror; 33, charge and discharge control switch tube; 40, time-to-digital converter. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be described and explained below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided in the present application without creative efforts belong to the scope of protection of the present application. In addition, it can also be understood that although the efforts made in such a development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present application, some design, manufacturing or production changes based on the technical content disclosed in the present application are only conventional technical means and should not be understood as the content disclosed in the present application being insufficient.

[0021] Referring to "embodiments" in the present application means that the specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The appearance of this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those of ordinary skill in the art explicitly and implicitly understand that the embodiments described in the present application can be combined with other embodiments without conflict.

[0022] Unless otherwise defined, the technical terms or scientific terms involved in the present application shall have the ordinary meaning understood by those of ordinary skill in the technical field to which the present application belongs. In the present application, when an element is referred to as "provided on" another element, it can be directly provided on the other element or there may also be an intermediate element. When an element is considered to be "arranged on" another element, it can be directly arranged on the other element or there may be an intermediate element at the same time. When an element is considered to be "fixed to" another element, it can be directly fixed to the other element or there may be an intermediate element at the same time. The terms "first", "second", "third", etc. involved in the present application are only used to distinguish similar objects and do not represent a specific order for the objects. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0023] Please refer to Figure 1 , the present invention provides an analog-to-digital conversion circuit based on VTC and TDC for a RRAM computing-in-memory chip, including a two-stage structure that folds the input voltage range; the first-stage structure includes a first comparator 10; the second-stage structure includes a charge pump 20, a voltage-to-time converter 30, and a time-to-digital converter 40; The first comparator 10, connected to the charge pump 20, is used to compare the input first voltage signal and the first reference signal to output a first digital signal; The charge pump 20, connected to the voltage-time converter 30, is used to receive the first digital signal as the enable voltage, step down the input first voltage signal under the enable voltage, and output a second voltage signal; The voltage-time converter 30, connected to the time-digital converter 40, is used to map the second voltage signal into a time-domain signal; The time-digital converter 40 is used to map the time-domain signal into a second digital signal and use the first digital signal and the second digital signal as a combined output.

[0024] Specifically, the two-stage structure of the analog-to-digital conversion circuit can fold the input voltage range. Among them, the first-stage structure includes the first comparator 10; the positive input terminal of the first comparator 10 inputs the first voltage signal; the negative input terminal of the first comparator 10 inputs the first reference signal; then the first comparator 10 compares the input first voltage signal and the first reference signal to output a first digital signal; this first digital signal has two functions. The first function is to be part of the final output of the analog-to-digital conversion circuit; another function is to be the enable voltage of the charge pump 20 in the second-stage structure to control the operation of the charge pump 20. Preferably, under the conditions of a 180nm process and a supply voltage VDD of 3.3V, based on factors such as linearity, conversion gain, and overhead, the input voltage range is selected to be folded in half, and the first reference signal Vref is set to half of the supply voltage VDD, corresponding to folding the input voltage range in half. Among them, the first voltage signal is Vin.

[0025] Among them, the second-stage structure includes the charge pump 20, the voltage-time converter 30 (VTC), and the time-digital converter 40 (TDC); the charge pump 20 steps down the input first voltage signal under the enabling action of the first digital signal and outputs a second voltage signal to the voltage-time converter 30; the voltage-time converter 30 maps the second voltage signal into a time-domain signal and transmits the time-domain signal to the time-digital converter 40; the time-digital converter 40 maps the time-domain signal into a second digital signal and combines the first digital signal Vout1 and the second digital signal Vout2 into the final output Vout of the analog-to-digital conversion circuit. Preferably, the number of bits of the first digital signal is 1 bit, the number of bits of the second digital signal is 7 bits, and the total number of output bits is 8 bits. Therefore, it can be considered that the two-stage structure of the analog-to-digital conversion circuit reduces the requirements for the linear input performance of the VTC and the design number of bits of the TDC.

[0026] In the related art, the time-domain analog-to-digital conversion circuit mainly consists of a voltage-time converter 30 and a time-digital converter 40. The VTC converts the voltage signal into a time signal with different pulse widths, and the TDC converts it into a digital signal. The main reason that limits the time-domain analog-to-digital conversion circuit to have a wide input range and high-precision applications is the non-linearity problem of the VTC. This is because the resistance of the current mirror in the actual VTC is a finite value, resulting in a limited input linear range, thus restricting the time-domain conversion accuracy. In this embodiment, the analog-to-digital conversion circuit includes a two-stage structure that folds the input voltage range; the first-stage structure includes a first comparator 10; the second-stage structure includes a charge pump 20, a voltage-time converter 30, and a time-digital converter 40; the first comparator 10 is connected to the charge pump 20 and is used to compare the input first voltage signal and the first reference signal to output a first digital signal; the charge pump 20 is connected to the voltage-time converter 30 and is used to receive the first digital signal as an enable voltage, step down the input first voltage signal under the enable voltage, and output a second voltage signal; the voltage-time converter 30 is connected to the time-digital converter 40 and is used to map the second voltage signal into a time-domain signal; the time-digital converter 40 is used to map the time-domain signal into a second digital signal, and use the first digital signal and the second digital signal as a combined output. It uses a two-stage structure to fold the entire input voltage range, realizes the circuit structure reuse of a single VTC and a single TDC under a wide input range, and has the advantage of reducing the circuit layout area; and through the self-biased low-voltage cascode current mirror in the charge pump 20 and the voltage-time converter 30, the linear input range and performance of the voltage-time converter 30 at a large input voltage are optimized, solving the problem of restricting the conversion accuracy due to the non-linear characteristics of the voltage-time converter 30, and realizing a time-domain analog-to-digital conversion circuit with a wide input range and high precision.

[0027] The above circuits will be described in detail below: In one embodiment, as Figure 2 shown, the charge pump includes an enable voltage control unit, a capacitor C1, a capacitor C2, a diode D1, and a diode D2; The enable voltage control unit is disposed between one end of the capacitor C1 and the output end of the first comparator; The other end of the capacitor C1 is respectively connected to the anode of the diode D1 and the cathode of the diode D2; The cathode of the diode D1 is connected to the positive input terminal of the first comparator; The anode of the diode D2 is respectively connected to one end of the capacitor C2 and the voltage-time converter; The other end of the capacitor C2 is grounded.

[0028] Specifically, capacitor C1 is the step-down capacitor of the charge pump, and capacitor C2 is the buffer capacitor of the charge pump. Diodes D1 and D2 control the current flow direction, enabling the current to flow from the input to the output; thereby preventing reverse current from entering the first comparator, and further improving the stability of the operation of the analog-to-digital conversion circuit.

[0029] Among them, the charge pump controls the output first digital signal after voltage step-down according to the enable voltage. Its basic principle is to use the charging and discharging of the step-down capacitor to step down the input first voltage signal to the required output voltage value (i.e., output the second voltage signal). The voltage Vout3 of the output second voltage signal is the voltage Vin of the input first voltage signal minus the voltage Vs of the first digital signal, and the expression is: Vout3 = Vin - Vs.

[0030] Among them, the enable voltage control unit includes a single-pole double-throw switch S1; it controls the access of the enable voltage (the first digital signal). Specifically: when the input first voltage signal Vin is greater than the first reference signal Vref, the output of the first comparator is high level. At this time, the single-pole double-throw switch S1 connects to the enable voltage 1, and the voltage value of the enable voltage 1 is VDD / 2; then it can be considered that the voltage value of the input first voltage signal Vin is reduced by VDD / 2. When the input first voltage signal Vin is less than or equal to the first reference signal Vref, the output of the first comparator is low level. At this time, the single-pole double-throw switch S1 connects to the enable voltage 2, and the value of the enable voltage 2 is 0, then it is considered that the voltage value of the input first voltage signal Vin remains unchanged.

[0031] Through this embodiment, the folding of the input voltage range and the range of the maximum input voltage are achieved, and the reliability of use is high.

[0032] In one of the embodiments, as Figure 3 and Figure 4 shown, the voltage-time converter includes a sample-and-hold module, a second comparator, a current mirror module, and a logic circuit; The sample-and-hold module is arranged between the charge pump and the negative input terminal of the second comparator, and is used to sample and hold the second voltage signal; The positive input terminal of the second comparator is connected to the current mirror module, and the output terminal of the second comparator is connected to the logic circuit, and is used to receive the second voltage signal and the capacitor voltage signal generated by the charging of the current mirror module, and compare the second voltage signal and the capacitor voltage signal to output a third voltage signal; The logic circuit is used to determine the time-domain signal according to the third voltage signal and the clock signal; the pulse width of the time-domain signal is proportional to the amplitude of the second voltage signal.

[0033] Specifically, the voltage-time converter can map the second voltage signal into a time-domain signal. Its basic principle is to simultaneously input the second voltage signal and the capacitor voltage signal generated by charging the current mirror module into the second comparator for comparison, so as to output the third voltage signal. Then, the third voltage signal is processed by the logic circuit, and finally the pulse width of the time-domain signal is proportional to the amplitude of the input second voltage signal.

[0034] In Figure 4 , the current mirror module includes a reference current Iref; a reference current mirror 31 composed of MOS transistors M1 and M2; a self-biased low-voltage cascode current mirror 32 composed of a resistor R1, MOS transistors M3, M4, M5, and M6; a charge and discharge control switch transistor 33 composed of MOS transistors M7, M8, and M9; and a capacitor C3. Among them, the reference current Iref is connected to the self-biased low-voltage cascode current mirror 32 through the reference current mirror 31, generally at the uA level, and is set according to factors such as power consumption. The charge and discharge of the capacitor C3 and the current output by the self-biased low-voltage cascode current mirror 32 together determine the capacitor voltage signal.

[0035] Among them, the sources of MOS transistors M1 and M2 are grounded; the gates of MOS transistor M1, the drain of MOS transistor M1, and the gate of MOS transistor M2 are all connected to the reference current Iref; the drain of MOS transistor M2 is respectively connected to one end of the resistor R1, the gate of MOS transistor M5, and the gate of MOS transistor M6; the other end of the resistor R1 is respectively connected to the gate of MOS transistor M3, the gate of MOS transistor M4, and the drain of MOS transistor M5; the source of MOS transistor M5 is connected to the drain of MOS transistor M3; the sources of MOS transistors M3 and M4 are both connected to the supply voltage VDD; the drain of MOS transistor M4 is connected to the source of MOS transistor M6; the drain of MOS transistor M6 generates a charging current IC to the sources of MOS transistors M7 and M8; the drain of MOS transistor M7 is grounded; the gate of MOS transistor M7 is connected to the clock signal CLKN; the gate of MOS transistor M8 is connected to the clock signal CLK; the drain of MOS transistor M8 is respectively connected to one end of the capacitor C3, the drain of MOS transistor M9, and the positive input terminal of the second comparator; the other end of the capacitor C3 is grounded; the source of MOS transistor M9 is grounded; the gate of MOS transistor M9 is connected to the clock signal CLK.

[0036] Among them, the signals of the clock signal CLKN and the clock signal CLK are opposite at the same moment. For example, when the clock signal CLK is at a high level, the clock signal CLKN is at a low level. When the clock signal CLK is at a high level, the MOS transistors M7 and M9 are turned on. The current generated by the self-biased low-voltage cascode current mirror 32 passes through the MOS transistor M7 to ground. The gate of the MOS transistor M8 is connected to a high level and is turned off. The MOS transistor M9 is turned on, causing the capacitor C3 to discharge to 0. When the clock signal CLK is at a low level, the MOS transistor M8 is turned on, causing the capacitor C3 to charge. The charging rate is determined by the ratio I / C of the current IC of the self-biased low-voltage cascode current mirror 32 and the capacitance value of the capacitor C3. This is because: the self-biased low-voltage cascode current mirror 32 generates a constant current to charge the capacitor. When the charging current is constant, the voltage on the capacitor has a linear relationship with time, and the voltage rises at a constant rate I / C with time. Then when the capacitor voltage signal VC is greater than the negative input (the second voltage signal) of the second comparator, it will cause a jump in the third voltage signal (the output of the second comparator). The clock signal CLK and the third voltage signal output by the second comparator pass through a logic circuit to output a time-domain signal of the phase difference between the two.

[0037] More specifically, M1, M2, and M9 are NMOS transistors, and the others are PMOS transistors. In other embodiments, the MOS transistors can also be implemented using other equivalent circuits, which are not limited herein.

[0038] Preferably, under the conditions of a 180nm process and a supply voltage VDD of 3.3V, the second voltage signal input after being stepped down by the charge pump satisfies the linear working range of the single-ended constant-current type VTC. Specifically, the capacitance value of the capacitor C3 is set according to the following expression: ; In the formula, k·Iref is the current value of the self-biased low-voltage cascode current mirror 32, k is the amplification factor of the self-biased low-voltage cascode current mirror 32 for the reference current; t is the conversion time, which is related to the operating frequency of the clock signal CLK; Vvtc is the conversion voltage range in the voltage-time converter. According to the first comparator and the charge pump folding the input voltage range in half, Vvtc is set to VDD / 2.

[0039] Among them, the sample and hold module can be controlled by the clock signal CLK to maintain synchronization.

[0040] Through this embodiment, the linear input range and performance of the voltage-time converter under a large input voltage can be further optimized by the action of the self-biased low-voltage cascode current mirror 32.

[0041] In one of the embodiments, the logic circuit is a phase detector.

[0042] Specifically, the phase detector can quickly output the time-domain signal of the phase difference between the third voltage signal and the clock signal CLK, reducing the hardware cost.

[0043] In one embodiment, the charging current of the capacitor C3 in the voltage-to-time converter is provided by the self-biased low-voltage cascode current mirror 32; the self-biased low-voltage cascode current mirror 32 biases the gate voltage of the cascode transistor through a resistor.

[0044] Specifically, compared with the conventional cascode current mirror, the output voltage margin of this embodiment increases by a threshold voltage, thereby improving the linearity of the output current, but the resistor is affected by PVT; that is, through this embodiment, the output voltage margin can be improved and a smaller overhead can be achieved.

[0045] Preferably, considering the PVT fluctuations and the resistor voltage drop, the resistance value R1 refers to Vod / Iref and takes the lower limit, where Vod is the overdrive voltage of the transistor; in order to reduce the body effect, the input transistor has a large W / L; considering the area and voltage margin, the cascode transistor uses the minimum allowable channel length.

[0046] In one embodiment, as Figure 3 shown, the reference current in the voltage-to-time converter is generated by a bandgap reference circuit and a voltage-to-current circuit; The bandgap reference circuit, connected to the voltage-to-current circuit, is used to generate a reference voltage with a low temperature coefficient; The voltage-to-current circuit is used to convert the reference voltage into a reference current according to a preset ratio.

[0047] Specifically, the bandgap reference circuit and the voltage-to-current circuit constitute a bias circuit to generate a reference current for the reference current mirror. Among them, the bandgap reference circuit uses the sum of a voltage proportional to temperature and a voltage inversely proportional to temperature, and the temperature coefficients of the two cancel each other out to achieve a voltage reference independent of temperature, and its value is generally 1.25V. The working principle of the voltage-to-current circuit is Iref = Vref / R, where R is the resistance value of the resistor.

[0048] Since the reference voltage has a low temperature coefficient, converting the reference voltage into a reference current according to a preset ratio also has the characteristic of a low temperature coefficient. Among them, the conversion ratio can be set according to actual usage requirements, and it is generally in the uA level.

[0049] In one embodiment, the time-to-digital converter includes a delay unit and a D flip-flop; The delay unit and the D flip-flop constitute a delay line structure to quantize the pulse width of the time-domain signal into a digital value to output a second digital signal.

[0050] Specifically, the basic principle of the time-to-digital converter is based on the time characteristics of the signal propagation in the delay line structure, and the output second digital signal is the quantization value of the pulse width of the time-domain signal.

[0051] In this embodiment, the time-to-digital converter adopts a delay line structure composed of delay units and D flip-flops. If the time-to-digital converter is N-bit, then 2 N groups of basic delay units and D flip-flops are required.

[0052] Through this embodiment, the time-to-digital converter can check analog impairments and resolution limitations, and it can also use the sine wave fitting method to test the effective number of bits ENOB of the analog-to-digital conversion circuit, debug the parameter design of each sub-circuit module according to ENOB, optimize the circuit parameter design, and obtain an analog-to-digital conversion circuit with a wide input range and high precision.

[0053] In one of the embodiments, the first digital signal output by the first-stage structure and the second digital signal output by the second-stage structure are combined and output after passing through a multiplexer and an encoder.

[0054] Through this embodiment, the combined output of the first digital signal and the second digital signal can be controlled.

[0055] In addition, in combination with the analog-to-digital conversion circuit based on VTC and TDC for the RRAM memory-computation integrated chip in the above embodiments, the embodiments of the present application can be implemented for an RRAM memory-computation integrated chip.

[0056] The RRAM memory-computation integrated chip includes the analog-to-digital conversion circuit based on VTC and TDC for any RRAM memory-computation integrated chip in the above embodiments; the analog-to-digital conversion circuit serves as the readout circuit of the RRAM memory-computation integrated chip.

[0057] Through the above RRAM memory-computation integrated chip, since its built-in analog-to-digital conversion circuit serves as the readout circuit of the RRAM memory-computation integrated chip; the two-stage structure of the analog-to-digital conversion circuit folds the entire input voltage range, realizes the circuit structure reuse of a single VTC and a single TDC in a wide input range, and has the advantage of reducing the circuit layout area. As the readout circuit of the RRAM memory-computation integrated chip, it quantifies and outputs the resistance values of different numbers and different resistance values of the memristor arrays.

[0058] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0059] Those of ordinary skill in the art should recognize that the above embodiments are only used to illustrate the present invention and are not intended to limit the present invention. As long as appropriate changes and variations are made to the above embodiments within the spirit and scope of the present invention, they fall within the scope of protection required by the present invention.

Claims

1. An analog-to-digital conversion circuit based on VTC and TDC for an RRAM storage-computing integrated chip, characterized in that: A two-stage structure including a folded input voltage range; the first stage structure including a first comparator; the second stage structure including a charge pump, a voltage-to-time converter and a time-to-digital converter; The first comparator is connected to the charge pump and is used to compare the input first voltage signal with the first reference signal to output a first digital signal; The charge pump is connected to the voltage-to-time converter, and is used to receive the first digital signal as an enable voltage, step down the input first voltage signal under the enable voltage, and output a second voltage signal; The voltage-to-time converter is connected to the time-to-digital converter and is used to map the second voltage signal into a time domain signal; The time-to-digital converter is used to map the time domain signal into a second digital signal, and output the first digital signal and the second digital signal as a combination.

2. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage-computing integrated chip according to claim 1, characterized in that: The first comparator compares the first voltage signal and the first reference signal to output the first digital signal, and the first digital signal is used as the charge pump enable voltage control; wherein the first reference signal is half of the supply voltage, corresponding to folding the input voltage range into half.

3. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage-computing integrated chip according to claim 1, characterized in that: The charge pump includes an enabling voltage control unit, a capacitor C1, a capacitor C2, a diode D1 and a diode D2; The enabling voltage control unit is arranged between one end of the capacitor C1 and the output end of the first comparator; The other end of the capacitor C1 is connected to the anode of the diode D1 and the cathode of the diode D2 respectively; The cathode of the diode D1 is connected to the positive input terminal of the first comparator; The anode of the diode D2 is connected to one end of the capacitor C2 and the voltage-time converter respectively; The other end of the capacitor C2 is grounded.

4. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage-computing integrated chip according to claim 1, characterized in that: The voltage-to-time converter includes a sample-and-hold module, a second comparator, a current mirror module, and a logic circuit; The sampling and holding module is arranged between the charge pump and the negative input terminal of the second comparator, and is used for sampling and holding the second voltage signal; The positive input terminal of the second comparator is connected to the current mirror module, and the output terminal of the second comparator is connected to the logic circuit, and is used to receive the second voltage signal and the capacitor voltage signal generated by charging the current mirror module, and compare the second voltage signal with the capacitor voltage signal to output a third voltage signal; The logic circuit is used to determine the time domain signal according to the third voltage signal and the clock signal; the pulse width of the time domain signal is proportional to the amplitude of the second voltage signal.

5. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage-computing integrated chip according to claim 4, characterized in that: The charging current of the capacitor C3 in the voltage-to-time converter is provided by a self-biased low-voltage cascode current mirror; the self-biased low-voltage cascode current mirror biases the gate voltage of the cascode transistor through a resistor.

6. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage-computing integrated chip according to claim 4, characterized in that: The reference current in the voltage-to-time converter is generated by a bandgap reference circuit and a voltage-to-current circuit; The bandgap reference circuit is connected to the voltage-to-current circuit and is used to generate a reference voltage with a low temperature coefficient; The voltage-to-current circuit is used to convert the reference voltage into a reference current according to a preset ratio.

7. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage-computing integrated chip according to claim 4, characterized in that: The logic circuit is a phase detector.

8. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage-computing integrated chip according to claim 1, characterized in that: The time-to-digital converter includes a delay unit and a D flip-flop; The delay unit and the D flip-flop form a delay line structure, which quantizes the pulse width of the time domain signal into digital data to output the second digital signal.

9. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage-computing integrated chip according to claim 1, characterized in that: The first digital signal output by the first-stage structure and the second digital signal output by the second-stage structure are combined and outputted through a multiplexer and an encoder.

10. A RRAM storage-computing integrated chip, characterized in that: It comprises an analog-to-digital conversion circuit based on VTC and TDC for an RRAM storage-computing integrated chip as described in any one of claims 1 to 9; the analog-to-digital conversion circuit serves as a readout circuit of the RRAM storage-computing integrated chip.

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