Calibration system applied to DLL-TDC

Abstract

The invention provides a calibration system applied to DLL-TDC, and solves the technical problems of low circuit linearity and large time measurement result error of an existing time-to-digital converter. The device comprises a DLL-TDC module and a calibration network module. The DLL-TDC module is used for feeding back a control voltage in real time and carrying out preliminary calibration on the delay time of each delay unit; obtaining the number of the delay units passing by at the stop moment and a count value according to the start and stop of the to-be-measured signal, and calculating the number of the delay units passing by the to-be-measured signal; and the calibration network module is used for detecting the change relationship between the temperature and the delay time, correspondingly predicting the delay time of the to-be-detected signal passing through each delay unit according to the temperature, and adding the delay time to obtain the time interval of the calibrated to-be-detected signal. The circuit can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit technology, and more specifically, relates to a calibration system for a DLL-TDC. Background Art

[0002] Precision time measurement holds significant research value and widespread application in engineering applications and scientific research, playing a crucial role in fields such as laser ranging, particle physics, and quantum communications. For example, in laser ranging, the distance between the detector and the target object can be accurately calculated by measuring the time difference between the transmitted and returned laser signals. Currently, application-specific integrated circuit (ASIC) time-to-digital converters (TDCs) have become a mainstream solution for precision time measurement.

[0003] A time-to-digital converter (TDC) is a high-precision time measurement circuit capable of measuring small time intervals. It has significant application demand in research areas such as lidar, fluorescence lifetime imaging, and 3D time-of-flight sensors. A Chinese invention patent application, CN202111470307.4, proposes a neural network measurement and calibration system and method for TDL-TDCs. This system uses a learning network to identify the nonlinear relationship between delay time and temperature data for delay elements. A tapped delay chain circuit is then used to perform fine time measurements, resulting in precise nonlinear calibration results for each element in the delay chain. However, in applications requiring extremely high measurement accuracy, such as autonomous driving and underwater terrain exploration, dynamic calibration of the TDC using an FPGA-based configuration can lead to temperature instability in the tapped delay chain (TDL) structure. This can cause deviations in the number of delay elements in the TDC as the measured signal passes through it. This can lead to misalignment between the delay time and the delay elements during subsequent neural network measurements, resulting in low TDC linearity and poor time measurement results. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a calibration system for a DLL-TDC to solve the technical problems in the prior art of low linearity of a time-to-digital converter circuit and large errors in time measurement results.

[0005] To achieve the above-mentioned object, an embodiment of the present application provides a calibration system for DLL-TDC, comprising: a DLL-TDC module and a calibration network module; The DLL-TDC module is used to provide real-time feedback on the control voltage and perform preliminary calibration on the delay time of each delay unit. Based on the start and stop of the signal to be measured, the number of delay units and the count value passed at the time of stop are obtained, and the number of delay units passed by the signal to be measured is calculated. The calibration network module is used to detect the changing relationship between temperature and delay time, and predict the delay time of the signal to be tested passing through each delay unit according to the temperature correspondence, and add them up to obtain the time interval of the signal to be tested after calibration.

[0006] Preferably, the DLL-TDC module includes a delay-locked loop, a voltage-controlled ring oscillator, a counter and a latch; The delay-locked loop is used for real-time feedback control voltage; The voltage-controlled ring oscillator is used to dynamically adjust the oscillation frequency according to the control voltage, and to start and stop oscillation according to the signal to be measured; The counter is used to count the number of oscillation cycles of the voltage-controlled ring oscillator to obtain a count value; The latch is used to latch the number of delay units and the count value that the signal to be tested passes through in the voltage-controlled ring oscillator at the time of stopping according to the start and stop state entered by the signal to be tested, and multiply the count value by the delay unit in each voltage-controlled ring oscillator cycle, and then add the count value to the number of delay units that the signal to be tested passes through in the voltage-controlled ring oscillator at the time to obtain the number of delay units that the signal to be tested passes through.

[0007] Preferably, the delay locked loop comprises a voltage controlled delay chain, a phase frequency detector and a charge pump; The voltage-controlled delay chain is used to generate a feedback clock signal according to the control voltage; The phase frequency detector is used to adjust the duty cycle of the pulse signal according to the phase difference between the reference clock signal and the feedback clock signal, and control the rise and fall of the control voltage in the charge pump; The charge pump is used to output the control voltage.

[0008] Preferably, the calibration network module determines whether the outputs of adjacent delay units are consistent, obtains the position in the voltage-controlled ring oscillator at the stop moment, latches the corresponding address in the latch, multiplies the proportion of the corresponding address to the total address by the count value, obtains the delay time of each corresponding delay unit, and adds them together to obtain the time interval of the signal to be measured after calibration.

[0009] Preferably, the network module is calibrated, and the delay time within the set temperature range and constant interval conditions is obtained by using the code density as the original training sample set for training; the delay time within the non-set temperature range and constant interval conditions is used as the verification data set to adjust the network parameters of the calibration network module.

[0010] Preferably, the phase and frequency detector includes an AND gate, and the pulse signal before the signal to be measured arrives is locked by the AND gate to achieve reset.

[0011] Preferably, the charge pump includes a current mirror and an amplifier, and the current mirror is used to replicate the current to make the charging current and the discharging current symmetrical.

[0012] Preferably, the phase and frequency detector converts the duty cycle of the pulse signal into a current signal to control the output end of the charge pump; The amplifier establishes a charge and discharge control loop through the capacitor at the output end to control the charging and discharging of the charge pump.

[0013] Preferably, the latch selects the enabled signal port and pulls the start flag high, generating a pulse and simulating the oscillation of the voltage-controlled ring oscillator to obtain the oscillation period and the count value.

[0014] Preferably, the counter is configured as a two-layer output circuit, which is controlled by output signals of adjacent delay units respectively; the output signals of adjacent delay units differ by half an oscillation period.

[0015] The beneficial effect of the present application is that: the present application proposes a calibration system for DLL-TDC, which obtains the number of delay units passed by the signal to be measured through the DLL-TDC module, and uses the trained calibration network module to predict the delay time of the signal to be measured passing through each delay unit according to the corresponding prediction, thereby accurately quantifying the time interval of the signal to be measured and realizing accurate calibration of the time interval of the signal to be measured.

[0016] First, the TDC module integrated with the DLL utilizes real-time feedback from the DLL control voltage, constantly calibrating the delay time of each delay cell in the TDC with the new control voltage. This dynamically compensates for delay variations caused by factors such as power supply voltage fluctuations and delay cell manufacturing process variations, ensuring that the delay time of each delay cell in the DLL-TDC module remains uniform, stable, and reliable, improving system linearity.

[0017] Next, based on the start and stop of the signal to be tested, the number of delay cells and the count value passed at the time of the stop are obtained to calculate the number of delay cells that the signal to be tested has passed through. By recording the number of delay cells and the count value passed by the signal to be tested at the time of the stop, the total delay time of the propagation of the signal to be tested can be accurately calculated. Compared to the traditional method of only recording the count values ​​at the start and stop times, this application can capture every delay cell that the signal to be tested passes through during its propagation, thereby avoiding errors caused by inaccurate estimation of the number of delay cells.

[0018] Finally, the calibration network module accurately predicts the delay time of each delay unit based on the temperature, accurately reflecting the delay under actual conditions, thereby improving the overall time interval measurement accuracy and further finely quantifying the time interval of the signal to be measured.

[0019] In summary, the present application uses the DLL-TDC module to accurately adjust the delay time of each delay unit in real time to accurately obtain the number of delay units that the signal to be measured passes through, thereby improving the linearity of the system; at the same time, the calibration network module is used to accurately identify the specific values ​​of the delay time corresponding to each delay unit at different temperatures, thereby improving the overall measurement accuracy and obtaining the precise time interval of the signal to be measured. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 A schematic diagram of a calibration system structure for a DLL-TDC according to an embodiment of the present application; Figure 2 A flowchart of a delay-locked loop provided in accordance with an embodiment of the present application; Figure 3 A charge pump circuit design diagram provided in one embodiment of the present application; Figure 4 A schematic diagram of the circuit structure of a time-to-digital converter provided in one embodiment of the present application; Figure 5 A flowchart of TDC measurement start signal processing provided in one embodiment of the present application; Figure 6 A flowchart of TDC measurement stop signal processing provided in one embodiment of the present application; Figure 7 A circuit diagram of a voltage-controlled delay unit provided in one embodiment of the present application; Figure 8 A working principle diagram of a two-phase counter provided in one embodiment of the present application; Figure 9 This is a schematic diagram of the overall circuit design of a counter provided in one embodiment of the present application; Figure 10 This is a top-level circuit design diagram of a counter provided in one embodiment of the present application; Figure 11 A latch circuit design diagram provided for an embodiment of the present application; Figure 12 A schematic diagram of the test platform structure provided in one embodiment of the present application; Figure 13 A schematic diagram of DNL / INL of each delay unit at 47°C provided in an embodiment of the present application; Figure 14A schematic diagram of the error between the network predicted value and the actual measured value at 23°C provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0023] This application proposes a calibration system for a DLL-TDC (Time-Delayed Clock) (TDC) system. The system includes a DLL-TDC module built into an ASIC chip and a calibration network module located in a host computer. The DLL-TDC module includes a delay-locked loop (DLPL). The DLPL's feedback loop generates a control voltage (Vctrl) to adjust the delay time of the delay cells, reducing delay time variations within each delay cell, ensuring consistent delay times and initially improving system linearity. The calibration network module is trained in different temperature environments to rapidly generate delay time values ​​for each delay cell, enabling precise quantification of the time interval of the measured signal.

[0024] See also Figure 1 , a calibration system applied to DLL-TDC provided in one embodiment of the present application, including: a DLL-TDC module and a calibration network module.

[0025] The DLL-TDC module provides real-time feedback on the control voltage Vctrl and performs preliminary calibration on the delay time of each delay cell, ensuring that the delay times of each delay cell are equal. Based on the start and stop of the signal under test, the module obtains the number of delay cells and the count value passed at the time of the test, and calculates the number of delay cells passed by the signal under test.

[0026] The calibration network module is used to detect the changing relationship between temperature and delay time. The delay time of the signal to be measured passing through each delay unit is predicted according to the temperature prediction, and the time interval of the signal to be measured after calibration is obtained by adding them together.

[0027] The DLL-TDC module includes a delay-locked loop (DLLL), a voltage-controlled ring oscillator (VCO), a latch, and a counter. The DLLL also includes a charge pump, a phase frequency detector (PFD), a low-pass filter, and a voltage-controlled delay chain.

[0028] The voltage-controlled delay chain is used to generate a feedback clock signal CLK_FB according to the control voltage Vctrl of the previous cycle, and input the feedback clock signal CLK_FB into a phase-frequency detector (PFD). The phase-frequency detector adjusts the duty cycles of the pulse signals UP and DOWN according to the phase difference between the reference clock signal CLK_REF and the feedback clock signal CLK_FB, thereby controlling the rise and fall of the control voltage in the charge pump (CP) to generate a new control voltage Vctrl. After being filtered by a low-pass filter, it is output to the voltage-controlled ring oscillator and undergoes the next cycle to generate a new control voltage Vctrl in real time, so as to preliminarily average and calibrate the delay time of the delay unit in the voltage-controlled ring oscillator, and align the phases of the reference clock signal CLK_REF and the feedback clock signal CLK_FB. Among them, the pulse signals UP and DOWN are obtained by converting the deviation of the rising edges of the reference clock signal CLK_REF and the feedback clock signal CLK_FB input into the two channels of the phase-frequency detector.

[0029] Please refer to Figure 2 , specifically, first input the feedback clock signal CLK_FB and the reference clock signal CLK_REF into the phase-frequency detector (PFD) to determine whether the phases of the two signals are the same. If they are not the same, divide them according to the position of the phase of the feedback clock signal, which is divided into the case where the phase of the feedback signal is advanced and the case where the phase of the feedback signal is lagged. When the phase of the feedback signal is advanced, it means that the duty cycle is DOWN>UP, and the charge pump (CP) is adjusted to reduce the output voltage Vctrl to make the phases of the reference clock signal and the feedback clock signal consistent, and a new control voltage Vctrl is obtained; when the phase of the feedback signal is lagged, it means that the duty cycle is DOWN<UP, and the charge pump (CP) is adjusted to increase the output voltage to make the phases of the reference clock signal and the feedback clock signal consistent, and a new control voltage Vctrl is obtained; if the phases are the same, it means that the duty cycle is DOWN=UP, and the control voltage Vctrl output by the charge pump (CP) remains unchanged.

[0030] The PFD is used to adjust the duty cycle of the pulse signal based on the phase difference between the reference clock signal and the feedback clock signal, controlling the rise and fall of the control voltage in the charge pump. Specifically, the PFD compares the input reference clock signal CLK_REF with the clock signal CLK_FB fed back from the voltage-controlled delay chain, generating pulse signals UP and DOWN with widths corresponding to the phase difference. These pulse signals are used to control the subsequent step-up and step-down of the charge pump. To improve response speed, reduce blind spots and dead zones, and enhance the performance of the PFD, this application utilizes a fast, simple, and low-power True Single Phase Clock (TSPC) D-type flip-flop. The PFD uses an AND gate to lock the pulse signals UP and DOWN before the signal to be measured arrives, achieving a reset. Specifically, during system startup, a reset signal (such as RSTE) is initiated to initialize the system to a specific state. By introducing an AND gate in the feedback loop, the reset signal is synchronized with the clock signal, thereby preventing malfunctions caused by signal asynchrony. A symmetrical multi-stage differential buffer is used at the output to correct for offsets in the UP and DOWN pulse signals, ensuring consistent charge and discharge of the charge pump. Because the buffer size increases in stages, the frequency and phase detector's ability to drive the charge pump switches is effectively increased, preventing dead zones. The circuit diagram of the charge pump is as follows Figure 3 As shown, the charge pump is used to output the control voltage Vctrl. The left side is a current mirror, including NMOS transistors M1, M2, M3, M4, M5, and M6. NMOS transistor M1's source is connected to M2's gate, its gate is connected to the reset signal, and its drain is connected to the input current. NMOS transistor M2's source is connected to M4's gate, its gate is connected to M3's gate, and its drain is connected to M1's source. NMOS transistor M3's source is connected to M5's gate, its gate is connected to M2's gate, and its drain is connected to N5's drain. NMOS transistor M4's source is connected to AGND, its gate is connected to M5's gate, and its drain is connected to M2's source. NMOS transistor M5's source is connected to AGND, its gate is connected to M4's gate, and its drain is connected to M3's source. NMOS transistor M6's source is connected to AGND, its gate is connected to M2's gate, and its drain is connected to AGND. The current mirror replicates the current to the left branch of the amplifier, providing the input reference bias for amplifier AMP. By accurately replicating the current in this way, the charging and discharging currents are made symmetrical, thus reducing current mismatch. This in turn reduces the phase noise and spurious signals in the delay-locked loop caused by current mismatch, improving the overall performance of the system.

[0031] The amplifier AMP establishes a charge-discharge control loop through the capacitor at the output of the charge pump to control the charging and discharging of the charge pump. The amplifier in this application uses a folded cascode amplifier, which not only provides high-gain amplification but also reduces output impedance through a cascode structure, providing high-bandwidth, rapid output voltage correction, and improving the system's frequency response.

[0032] When the pulse signal UP is low, PMOS transistor N1 is turned on, the voltage at the node is AGND, and the lower PMOS transistor N7 is turned off and left floating. If the pulse signal DOWN is high at this time, a discharge path is formed, and the output voltage decreases. If the pulse signal UP is high and the pulse signal DOWN is low, a charging path is formed, and the output voltage increases.

[0033] Specifically, when the signal UP = 1 at the gate of PMOS transistor N3 and the signal UPN = 0 at the gate of NMOS transistor M7, the upper PMOS transistor N1 turns on, and the analog voltage AVDD inputs charge to the output terminal CP_OUT, causing the voltage at the output terminal CP_OUT to increase. When the signal DOWN = 1 at the gate of PMOS transistor N8 and the signal DOWNN = 0 at the gate of NMOS transistor M10, NMOS transistor M11 turns on, and the capacitor at the output terminal CP_OUT releases charge to AGND, causing the voltage to decrease. The amplifier monitors the voltage at the output terminal CP_OUT in real time and compares it with the target voltage of the left reference circuit. The output control signal controls the subsequent circuitry, which should be able to adjust the conduction frequency of the charge and discharge circuits to bring the voltage at the output terminal CP_OUT back to the same level as the target voltage of the left reference circuit. When the UP and DOWN signals are not strictly opposite, the charge and discharge paths are simultaneously conductive, and the current in the right branch is determined by the current mirror below, providing overcurrent protection. To prevent oscillation, STBP and STBN are pulsed on at power-on to shield the amplifier output and provide a stable bias point for the capacitor at the output terminal CP_OUT to prevent oscillation or lock-up (the amplifier locks the output at AVDD or AGND due to excessive input offset voltage). The control of the charge and discharge circuit is transferred to the amplifier only after the amplifier and capacitor are fully established.

[0034] See also Figure 4 , is a circuit diagram of the voltage controlled ring oscillator, latch and counter. Figure 5, which is a flow chart of the voltage-controlled ring oscillator, latch and counter measuring the start signal of the signal to be measured. During the measurement process, when the start signal START is input to the latch, the latch will detect whether the signal port is in the enabled state. If the signal port is enabled, the latch will immediately pull the start flag high to indicate the start of the measurement. Then, the latch generates a pulse and the analog part voltage-controlled ring oscillator starts oscillating, and the analog part oscillation period and count value are obtained, which are latched and sampled; otherwise, the measurement start signal continues to be input. The present application uses a latch to determine whether the signal port is enabled, which can accurately control the start timing of the voltage-controlled ring oscillator to ensure that oscillation starts at the right time. When the signal port is enabled, the latch will pull the start flag high and generate a pulse signal, and the analog part ring oscillator starts oscillating at the same time. This synchronous operation ensures the coordinated operation of the digital part and the analog part, avoiding errors caused by timing differences.

[0035] See also Figure 6 This is a flow chart for measuring a stop signal using a voltage-controlled ring oscillator, latch, and counter. The purpose is to determine the number of delay cells in the voltage-controlled ring oscillator and the count value at the moment the stop signal arrives, which is used for subsequent time interval calculation. In an optional embodiment, the present application provides four stop signals, STOP1, STOP2, STOP3, and STOP4, and corresponding input channels. It also sets the maximum number of stop signals each channel can receive and four measurement modes. Specifically, the test stop signal STOP is input to a latch, which determines whether the stop signal port is enabled. If so, the stop signal counter for that channel is incremented by one, raising the stop flag for that channel. Otherwise, the stop signal continues to be input. After the stop flag is raised, the test mode is selected based on the threshold value preset by the TDC circuit (configured by the SPI communication protocol). If the conditions for test mode 1 are met, all four channels are measured individually. If the conditions for test mode 2 are met, channels one and two are measured together: out_stop2 = out_stop1 = stop1_in. Channels three and four are measured individually. If the conditions of test mode 3 are met, the combined measurement of channels one and two is: out_stop2 = out_stop1 = stop1_in, and the combined measurement of channels three and four is: out_stop4 = out_stop3 = stop3_in. If the conditions of test mode 4 are met, the combined measurement of all four channels is: out_stop4 = out_stop3 = out_stop2 = out_stop1 = stop1_in. The results obtained in this test mode are input into the latch pulse generation module and the analog part, and the analog ring oscillator value and counter value are latched and sampled. If the counter value is greater than the expected value, the measurement ends. Otherwise, the measurement stop signal is input again.

[0036] Specifically, see Figure 4, this application uses inverters as delay units of a voltage-controlled ring oscillator, and an odd number of inverters are connected end to end to form a voltage-controlled ring oscillator. The voltage-controlled ring oscillator is used to dynamically adjust the oscillation frequency according to the control voltage Vctrl. When the start signal START is received, each delay unit of the voltage-controlled ring oscillator begins to adjust the oscillation frequency according to the control voltage Vctrl output by the charge pump until a stop signal is received. This application selects 55 inverters connected end to end to form a voltage-controlled ring oscillator, and the circuit diagram of each inverter is as shown below. Figure 7 As shown. The number of inverters is required to be an odd number, but the specific number is not limited and can be selected according to actual conditions. In this application, the N-channel width of the NMOS transistor M0 in the inverter is set to 2μm, the P-channel width of the PMOS transistor M1 is set to 4μm, and the channel length of both MOS transistors is set to 180nm. The gate of the NMOS transistor M2 is connected to the control voltage (Vctrl, VC) to adjust the charge and discharge speed of the voltage-controlled ring oscillator delay unit. The drain is connected to the source of the NMOS transistor M0, and the source is grounded. The gate of the NMOS transistor M0 and the gate of the PMOS transistor M1 are connected to the input signal (IN). The drain of the NMOS transistor M0 and the drain of the PMOS transistor M1 are grounded via resistor C0. The source of the NMOS transistor M0 is grounded, and the source of the PMOS transistor M1 is connected to the power supply (DVDD).

[0037] The counter is used to count the number of oscillation cycles of the voltage-controlled ring oscillator, which plays a role in expanding the range. After two cycles of the voltage-controlled ring oscillator are completed, the value of the counter will increase by one. In order to ensure the high speed and high precision of the system, this application sets the range of the system to 20μs, calculates the working cycle of the voltage-controlled ring oscillator according to the number of delay units in the voltage-controlled ring oscillator and the delay time of each delay unit, and finally selects different levels of counters for counting according to the working cycle of the voltage-controlled ring oscillator. This application uses a 13-level counter for counting. There is no limit on the number of counter levels here and it can be set according to actual conditions.

[0038] Furthermore, in order to avoid the long-term instability caused by the asynchronous counter, which leads to inaccurate timing, this application uses a synchronous counter and uses a two-phase counter to sample the stable output. Its working principle is as follows Figure 8 As shown in the figure, the blue part is the phase where the data is valid, which meets the setup time and hold time of sampling.

[0039] Since the carry signal of the voltage-controlled ring oscillator needs to pass through the transmission path before reaching the counter, it often causes delays and unstable output signals, affecting the accuracy of the timing results. Therefore, the present application sets the counter as a two-layer output circuit, which is controlled by the output signals of adjacent delay units (inverters). The output signals of the two differ by half an oscillation cycle, ensuring that when the sampling signal is sampled, the counter to be sampled can be determined based on the lowest bit of the oscillation cycle, thereby sampling a valid count value, improving sampling accuracy, and avoiding sampling a transition state or an uncertain count value. At the same time, this method of interleaving the output signals between adjacent delay units can effectively reduce the impact of external interference on the sampling results and improve the stability and reliability of the system.

[0040] The overall circuit structure of the counter is as follows Figure 9 As shown, it includes a 13-stage synchronous counter on the left and a 13-stage two-phase counter on the right. Figure 10 The output from the previous stage is connected to three NAND gates. The output result is calculated by the NOR gate and connected to the XOR gate with the highest level carry output. The XOR gate output is connected to a D flip-flop for output.

[0041] Furthermore, the latch is used to latch and hold the output of the voltage-controlled ring oscillator and the counter for a period of time when the timing start and stop signals STOP1, STOP2, STOP3 and STOP4 arrive, so that the setup time and hold time of the sampled signal can be met when sampling the sampling signal. Figure 11 This is the circuit diagram of a latch. After the latch signal _CK is input to the _CK port, it outputs two opposing control signals through an inverter and a CMOS transmission gate serving as a delay element. These signals control the operating state of the controlled gate, thereby latching data. The latch signal _CK is then passed through two stages of inverters to generate two control signals CK1 and _CK1 with opposite phases. The control signals CK1 and _CK1, along with the input signal D after passing through the controlled gate, are then XORed together with the reset signal _RST through the inverter output. The XOR operation is then performed on the two stages of inverters, where the latched value Q is output. The controlled gate below the XOR gate is used to latch the XOR gate's output under specific conditions.

[0042] When latching, the latch is first reset. A low signal (RST) is input to the reset port (_RST), causing the NOR gate input to go high. Therefore, while the reset signal RST is active, the latch output remains low. After the reset is complete, the latch output is adjusted back to a low level. When the reset signal is removed and the latch signal _CK is low, the left-hand controlled gate operates normally, while the controlled gate below the NOR gate closes. At this point, the signal at the D input is first inverted and then NORed with the inverted reset input ("0"). Since the reset input is '0', the NOR result equals the signal at the D input. This signal then passes through two inverters and is transmitted to the output port. Therefore, in this case, the output signal is the same as the signal at the D input. At this time, if a high level is input to the _CK port, the controlled gate is closed and the NOR gate is opened. This change locks the state of the NOR gate, so that no matter how the input signal at the D end changes, the output will maintain the original value, thereby completing the latch function and obtaining the count value and the number of delay units in the voltage-controlled ring oscillator.

[0043] To obtain a more accurate time interval for the signal under test, this application uses a code density test method to calibrate the system bit by bit based on the temperature of the chip's operating environment. This method trains a neural network to generate a calibration network module. The calibration network module predicts the delay time corresponding to each delay unit based on the temperature, and then adds them together to obtain the time interval for the signal under test.

[0044] In an optional embodiment, a code density test platform is built using a signal generator and an FPGA to collect the code density test results obtained at each interval within a set temperature range and a constant temperature interval for the chip under test, and transmit them to a host computer to calculate the delay time of each delay unit as the original training sample data set. The temperature range set in this application is 10°C to 55°C, and the constant temperature interval is 5°C. There are no requirements for the temperature range and constant temperature interval here, and they can be set by yourself. The code density test results at non-set temperatures are collected as a verification data set. According to the regression prediction network, the network parameters (the number of hidden layers, the number of input and output nodes in each layer) are adjusted so that the loss function value of the verification data set is reduced to 1exp(-3) to obtain a calibration network module. Among them, the circuit of the chip under test is consistent with the DLL-TDC module.

[0045] Specifically, see Figure 12Figure 2 shows the test platform structure. The chip under test is placed in a constant temperature chamber and the temperature is adjusted. A signal generator is connected to the corresponding pins on the chip and randomly sends test start pulses (START). An FPGA test board or host computer communicates with the chip under test via the SPI protocol, and the enable signal for the test stop pulse (STOP) is set high. After the enable bit of the enable signal is pulled high, the outputs of adjacent delay cells (inverters) in the voltage-controlled ring oscillator are initially inconsistent. When the external input clock's rising edge arrives, if the outputs of two adjacent bits are consistent, the low bit represents the position of the delay cell in the voltage-controlled ring oscillator where the test stop pulse propagated. After being latched in a latch, the position detection and encoding module detects the position of the test stop pulse in the voltage-controlled ring oscillator and converts it into binary data. This data is then transmitted to the FPGA via SPI. In the FPGA, the binary data is used as the address and the variable corresponding to the address in RAM is incremented by 1. Binary data is repeatedly retrieved until the expected number of calibrations is completed. Finally, the data in RAM is sent to the host computer or FPGA. In an optional embodiment, 55 inverters are provided in the voltage-controlled ring oscillator, and the ratio of the data of each of the 55 addresses to the total data is multiplied by the count value to obtain the delay time, and the training sample data set is obtained after the data processing is completed.

[0046] A calibration network module based on a regression prediction neural network model is constructed, which is determined to be a multi-layer perceptron (MLP). In an optional embodiment, temperature information is used as input, the number of input nodes is set to 7, one hidden layer is set, and the number of output nodes is set to 55, representing the delay time of 55 delay units. In order to prevent overfitting, the training sample data set is divided into multiple batches, with 32 groups of data in each batch. After inputting a set of training sample data, the calibration network module calculates the output value of each node. According to the optimization method of stochastic gradient descent, the network parameters are adjusted in the negative gradient direction of the objective function. When the error is less than 1exp(-3), the parameters are saved and training is stopped. Collect 3 groups of delay times under constant interval conditions within the non-set temperature range as a verification data set to observe whether the loss function value of the verification data set meets expectations. Among them, the differential nonlinearity (DNL) and integral nonlinearity (INL) of each delay unit of the chip at 47°C are as follows Figure 13 The horizontal axis represents the delay unit number (1 to 55), and the vertical axis represents the error value (VALUE), ranging from -1.5 to 1.5. As can be seen in the figure, the differential nonlinearity and integral nonlinearity fluctuate between -0.5 and 0.5, demonstrating excellent linearity.

[0047] After the calibration network module is trained, the code density test results of the chip under test are collected at 5°C intervals within the temperature range of 17°C to 52°C. The trained calibration network module is used to predict the delay time of each delay unit at temperatures between 17°C and 52°C. If the error between the predicted value obtained by the calibration network module and the measured value of the delay unit is within 0.2%, it is marked as a correct prediction; otherwise, it is marked as unqualified. The error between the predicted value and the measured value of the calibration network module at 23°C is as follows: Figure 14 As shown in the figure, most of the error values ​​fluctuate between -0.5 ps and 0.5 ps, indicating that the difference between the predicted value and the measured value is very small. The number of delay units marked as correct is divided by the total number of delay units, 55, to obtain the accuracy of the calibration network module at the corresponding temperature. Multiple statistics show that the accuracy of the calibration network module is between 90% and 92%, indicating that the calibration network module of the present application can accurately obtain the delay time value corresponding to each delay unit.

[0048] Finally, the number of delay units passed by the signal to be tested obtained by the DLL-TDC module is matched with the delay time value of each delay unit obtained by the calibration network module, and then the two are added to obtain the time interval of the signal to be tested.

[0049] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0050] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A calibration system for DLL-TDC, characterized in that: Includes DLL-TDC module and calibration network module; The DLL-TDC module is used to provide real-time feedback of the control voltage and perform preliminary calibration on the delay time of each delay unit; the number of delay units and the count value passed by the signal under test at the time of start and stop are obtained according to the start and stop of the signal under test, and the number of delay units passed by the signal under test is calculated; The calibration network module is used to detect the relationship between temperature and delay time, predict the delay time of the signal to be measured passing through each delay unit according to the temperature correspondence, and add them to obtain the time interval of the signal to be measured after calibration.

2. The calibration system for DLL-TDC according to claim 1, wherein: The DLL-TDC module includes a delay-locked loop, a voltage-controlled ring oscillator, a counter and a latch; The delay phase-locked loop is used for real-time feedback control voltage; The voltage-controlled ring oscillator is used to dynamically adjust the oscillation frequency according to the control voltage and to oscillate according to the start and stop of the signal to be measured; The counter is used to count the number of oscillation periods of the voltage-controlled ring oscillator to obtain the count value; The latch is configured to latch the number of delay units in the voltage-controlled ring oscillator that the signal to be tested passes through at the stop moment and the count value according to the start / stop state entered by the signal to be tested, multiply the count value by the number of delay units in each voltage-controlled ring oscillator cycle, and then add the multiplied count value to the number of delay units in the voltage-controlled ring oscillator that the signal to be tested passes through at the stop moment, to obtain the number of delay units that the signal to be tested passes through.

3. The calibration system for DLL-TDC according to claim 2, wherein: The delay phase-locked loop includes a voltage-controlled delay chain, a phase frequency detector and a charge pump; The voltage-controlled delay chain is used to generate a feedback clock signal according to the control voltage; The phase frequency detector is used to adjust the duty cycle of the pulse signal according to the phase difference between the reference clock signal and the feedback clock signal, and control the increase or decrease of the control voltage in the charge pump; The charge pump is used to output a control voltage.

4. The calibration system for DLL-TDC according to claim 2, wherein: The calibration network module determines whether the outputs of adjacent delay units are consistent, obtains the position of the stop moment in the voltage-controlled ring oscillator, latches the corresponding address in the latch, multiplies the ratio of the corresponding address to the total address by the count value, and obtains the delay time of each delay unit corresponding to the delay unit. The sum of the ratios is used to obtain the time interval of the signal to be measured after calibration.

5. The calibration system for DLL-TDC according to claim 1, wherein: The calibration network module uses code density to obtain the delay time within a set temperature range and a constant interval condition as an original training sample set for training; and uses the delay time within a non-set temperature range and a constant interval condition as a verification data set to adjust the network parameters of the calibration network module.

6. The calibration system for DLL-TDC according to claim 3, wherein: The phase and frequency detector includes an AND gate, and the pulse signal before the signal to be measured arrives is locked by the AND gate to achieve reset.

7. The calibration system for DLL-TDC according to claim 3, wherein: The charge pump includes a current mirror and an amplifier. The current mirror is used to replicate current to make the charging current and the discharging current symmetrical.

8. The calibration system for DLL-TDC according to claim 7, wherein: The phase frequency detector converts the duty cycle of the pulse signal into a current signal to control the output end of the charge pump; The amplifier establishes a charge and discharge control loop through the capacitor at the output end to control the charging and discharging of the charge pump.

9. The calibration system for DLL-TDC according to claim 2, wherein: The latch selects the enabled signal port and pulls the start flag high, generating a pulse and simulating the oscillation of the voltage-controlled ring oscillator to obtain the oscillation period and count value.

10. The calibration system for DLL-TDC according to claim 9, characterized in that: The counter is configured as a two-layer output circuit, which is controlled by the output signals of adjacent delay units respectively; the output signals of adjacent delay units differ by half the oscillation period.

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