High-precision time-to-digital converter based on memristor

Abstract

The invention discloses a high-precision time-to-digital converter based on a memristor. The converter comprises a first delay chain and N time decision devices, the first delay chain comprises N series-connected memristor-based delay units, and the output end of each memristor-based delay unit is correspondingly connected with the first input end of one time decision device; a starting signal is respectively input to first input ends of the N time decision devices through the N series-connected memristor-based time delay units of the first time delay chain, and an ending signal is directly input to second input ends of the N time decision devices. The time-to-digital converter is high in precision, high in linearity and easy to apply.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and more specifically, to a high-precision time-to-digital converter based on a memristor. Background Art

[0002] In recent years, high-precision time interval measurement technology has been widely used in medical image scanning technology, phase-locked loop technology and laser radar imaging technology. Among them, high-precision and high-linear time-to-digital converter is the core of high-precision time interval measurement technology.

[0003] Time-to-digital converters can be divided into two categories according to their implementation principles. Analog implementation based on time-to-voltage converter and analog-to-digital converter and digital implementation based on delay chain. Among them, time-to-digital converters based on analog implementation are often difficult to migrate to advanced CMOS processes due to their characteristics, and are easily affected by temperature and noise, and consume a large area and power. Compared with them, digital implementation has the advantages of high integration, small area, low power consumption, and strong circuit robustness, and has become the mainstream trend in the implementation of time-to-digital converters. However, the current digitally implemented time-to-digital converters still have the problem of poor linearity, and there are certain difficulties in their application.

[0004] The prior art discloses a differential delay chain time digital converter. The differential delay chain time digital converter is composed of a plurality of multi-way switch differential delay chain units cascaded, each of which is composed of a trigger and two configurable path delay modules, the trigger at least comprising a data input terminal, a clock input terminal and an output terminal; each configurable path delay module comprises an input terminal and an output terminal, and the input terminal of each configurable path delay module is connected to the output terminal of the corresponding configurable path delay module of the previous stage. The digital converter has low precision and the delay is difficult to adjust. Summary of the invention

[0005] The present invention aims to solve the defects of poor linearity and difficulty in application of the time-to-digital converter in the prior art, and provides a high-precision time-to-digital converter based on a memristor. The time-to-digital converter has high linearity, high precision and is easy to apply.

[0006] The primary purpose of the present invention is to solve the above technical problems. The technical solution of the present invention is as follows:

[0007] A high-precision time-to-digital converter based on a memristor comprises a first delay chain and N time decision devices; wherein the first delay chain comprises N series-connected delay units based on a memristor, and the output end of each delay unit based on a memristor is correspondingly connected to the first input end of a time decision device;

[0008] The start signal is respectively input to the first input ends of the N time decision devices through the N series-connected memristor-based delay units of the first delay chain, and the end signal is directly input to the second input ends of the N time decision devices.

[0009] A high-precision time-to-digital converter based on a memristor, comprising a first delay chain, a second delay chain and N time judges; wherein the first delay chain comprises N series-connected delay units based on a memristor, and the second delay chain comprises N series-connected delay units based on a memristor; each delay unit based on a memristor of the first delay chain is connected to a first input end of a time judge; and the output end of each delay unit based on a memristor of the second delay chain is correspondingly connected to a second input end of a time judge;

[0010] The start signal is input to the first input ends of the N time decision devices through the N series-connected memristor-based delay units of the first delay chain, and the end signal is input to the second input ends of the N time decision devices through the N series-connected memristor-based delay units of the second delay chain.

[0011] A high-precision time-to-digital converter based on a memristor, comprising: a first delay chain, a second delay chain and 2N time decision devices;

[0012] The first delay chain includes N series-connected memristor-based delay units, and the second delay chain includes N series-connected memristor-based delay units;

[0013] The output ends of the N memristor-based delay units of the first delay chain and the N memristor-based delay units of the second delay chain are respectively connected to the first input end of a time decision device;

[0014] The start signal is input to the first input ends of the N time decision devices through the N series-connected memristor-based delay units of the first delay chain, and the end signal is input to the first input ends of the remaining N time decision devices through the N series-connected memristor-based delay units of the second delay chain, and the clock signal is directly input to the second input ends of the 2N time decision devices.

[0015] Further, the delay unit based on memristor includes: a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, and a first memristor Memristor1;

[0016] The gate of the first MOS tube M1 is connected to the gate of the second MOS tube M2, the source of the first MOS tube M1 is connected to one end of the first memristor Memristor1 and the source of the third MOS tube M3, the drain of the first MOS tube M1 is connected to the drain of the second MOS tube M2, the gate of the third MOS tube M3 and the gate of the fourth MOS tube M4, the drain of the third MOS tube M3 is connected to the drain of the fourth MOS tube M4, the source of the second MOS tube M2 is connected to the drain of the fifth MOS tube M5, the source of the fourth MOS tube M4 is connected to the drain of the sixth MOS tube M6, the gate of the fifth MOS tube M5 is connected to the gate of the sixth MOS tube M6, the other end of the first memristor Memristor1 and the drain of the seventh MOS tube M7, and the source of the fifth MOS tube M5 is connected to the source of the sixth MOS tube M6 and the source of the seventh MOS tube M7;

[0017] The start signal or the end signal is input to the gate of the first MOS tube M1 and the gate of the second MOS tube M2, and is output from the drain of the third MOS tube M3 and the drain of the fourth MOS tube M4.

[0018] Further, the memristor-based delay unit includes: an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13, a second memristor Memristor2, and a third memristor Memristor3;

[0019] The source of the eighth MOS tube M8 is connected to the source of the tenth MOS tube M10, the gate of the eighth MOS tube M8 is connected to the gate of the ninth MOS tube M9, the drain of the eighth MOS tube M8 is connected to the drain of the ninth MOS tube M9, the gate of the tenth MOS tube M10, and the gate of the eleventh MOS tube M11, the drain of the tenth MOS tube M10 is connected to the drain of the eleventh MOS tube M11, the source of the ninth MOS tube M9 is connected to the drain of the twelfth MOS tube M12 and one end of the third memristor Memristor3, the source of the eleventh MOS tube M11 is connected to one end of the second memristor Memristor2 and the drain of the thirteenth MOS tube M13, the gate of the twelfth MOS tube M12 is connected to the gate of the thirteenth MOS tube M13, the source of the twelfth MOS tube M12 is connected to the source of the thirteenth MOS tube M13, the other end of the third memristor Memristor3, and the other end of the second memristor Memristor2;

[0020] The start signal or the end signal is input to the gate of the eighth MOS tube M8 and the gate of the ninth MOS tube M9 , and is output from the drain of the tenth MOS tube M10 and the drain of the eleventh MOS tube M11 .

[0021] Further, the memristor-based delay unit includes: a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16, a seventeenth MOS tube M17, and a fourth memristor Memristor4;

[0022] The gate of the fourteenth MOS tube M14 is connected to the gate of the fifteenth MOS tube M15, the source of the fourteenth MOS tube M14 is connected to the source of the sixteenth MOS tube M16, the drain of the fourteenth MOS tube M14 is connected to the drain of the fifteenth MOS tube M15, the gate of the sixteenth MOS tube M16, the gate of the seventeenth MOS tube M17, and one end of the fourth memristor Memristor4, the drain of the sixteenth MOS tube M16 is connected to the drain of the seventeenth MOS tube M17, and the source of the fifteenth MOS tube M15 is connected to the other end of the fourth memristor Memristor4 and the source of the seventeenth MOS tube M17;

[0023] The start signal or the end signal is input to the gate of the fourteenth MOS tube M14 and the gate of the fifteenth MOS tube M15 , and is output from the drain of the sixteenth MOS tube M16 and the drain of the seventeenth MOS tube M17 .

[0024] Further, the memristor-based delay unit includes: an eighteenth MOS tube M18, a nineteenth MOS tube M19, a twentieth MOS tube M20, a twenty-first MOS tube M21, a fifth memristor Memristor5, and a sixth memristor Memristor6;

[0025] The source of the eighteenth MOS tube M18 is connected to the source of the twentieth MOS tube M20, the gate of the eighteenth MOS tube M18 is connected to the gate of the nineteenth MOS tube M19, the drain of the eighteenth MOS tube M18 is connected to the drain of the nineteenth MOS tube M19, the gate of the twentieth MOS tube M20, and the gate of the twenty-first MOS tube M21, the drain of the twentieth MOS tube M20 is connected to the drain of the twenty-first MOS tube M21, the source of the nineteenth MOS tube M19 is connected to one end of the fifth memristor Memristor5, the source of the twenty-first MOS tube M21 is connected to one end of the sixth memristor Memristor6, and the other end of the fifth memristor Memristor5 is connected to the other end of the sixth memristor Memristor6;

[0026] The start signal or the end signal is input to the gate of the eighteenth MOS tube M18 and the gate of the nineteenth MOS tube M19, and is output from the drain of the twentieth MOS tube M20 and the drain of the twenty-first MOS tube M21.

[0027] Furthermore, the time determiner is a D flip-flop or a phase detector.

[0028] Further, the phase detector includes: a twenty-second MOS tube M22, a twenty-third MOS tube M23, a twenty-fourth MOS tube M24, a twenty-fifth MOS tube M25, a twenty-sixth MOS tube M26, a twenty-seventh MOS tube M27, a twenty-eighth MOS tube M28, and a twenty-ninth MOS tube M29;

[0029] The gate of the twenty-second MOS tube M22 is connected to the gate of the twenty-fifth MOS tube M25, the source of the twenty-second MOS tube M22 is connected to the source of the twenty-third MOS tube M23, the source of the twenty-sixth MOS tube M26, and the source of the twenty-seventh MOS tube M27, the drain of the twenty-second MOS tube M22 is connected to the drain of the twenty-third MOS tube M23, the gate of the twenty-sixth MOS tube M26, the gate of the twenty-eighth MOS tube M28, and the drain of the twenty-fourth MOS tube M24, the gate of the twenty-third MOS tube M23 is connected to the gate of the twenty-sixth MOS tube M26, the gate of the twenty-eighth MOS tube M28, and the drain of the twenty-fourth MOS tube M24. The gate of the fourteenth MOS tube M24, the drain of the twenty-sixth MOS tube M26, the drain of the twenty-seventh MOS tube M27, and the drain of the twenty-eighth MOS tube M28 are connected, the gate of the twenty-seventh MOS tube M27 is connected to the gate of the twenty-ninth MOS tube M29, the source of the twenty-fourth MOS tube M24 is connected to the drain of the twenty-fifth MOS tube M25, the source of the twenty-eighth MOS tube M28 is connected to the drain of the twenty-ninth MOS tube M29, and the source of the twenty-ninth MOS tube M29 is connected to the source of the twenty-fifth MOS tube M25;

[0030] The signal of the first input terminal is input to the gate of the twenty-second MOS tube M22 and the gate of the twenty-fifth MOS tube M25 , and the signal of the second input terminal is input to the gate of the twenty-seventh MOS tube M27 and the gate of the twenty-ninth MOS tube M29 .

[0031] Furthermore, the delay of the first delay unit of the first delay chain is different from that of the first delay unit of the second delay chain.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The present invention uses a delay unit based on a memristor so that when the resistance value of the memristor changes, the delay of the delay unit can be adjusted within a small range, so that the delay units on the same delay chain remain highly consistent, thereby solving the nonlinear problem of traditional time-to-digital converters and improving measurement accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a structural diagram of a high-precision time-to-digital converter based on a memristor provided in Example 1.

[0035] Figure 2This is a structural diagram of a high-precision time-to-digital converter based on a memristor provided in Example 2.

[0036] Figure 3 This is a structural diagram of a first delay chain of a high-precision time-to-digital converter based on a memristor provided in Example 3.

[0037] Figure 4 This is a structural diagram of a second delay chain of a high-precision time-to-digital converter based on a memristor provided in Example 3.

[0038] Figure 5 This is a structural diagram of a memristor-based delay unit provided in Example 4.

[0039] Figure 6 This is a structural diagram of a memristor-based delay unit provided in Example 5.

[0040] Figure 7 This is a structural diagram of a memristor-based delay unit provided in Example 6.

[0041] Figure 8 This is a structural diagram of a memristor-based delay unit provided in Example 7.

[0042] Fig. 9 This is a structural diagram of the phase detector provided in Example 8.

[0043] Fig.10 Linearity line graph of the 32-bit vernier time-to-digital converter provided in Example 8. DETAILED DESCRIPTION

[0044] The drawings are for illustrative purposes only and should not be construed as limiting the present patent;

[0045] In order to better illustrate the present embodiment, some parts in the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product;

[0046] It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0047] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0048] Example 1

[0049] like Figure 1 As shown, a high-precision time-to-digital converter based on a memristor includes a first delay chain and N time determiners; wherein the first delay chain includes N series-connected delay units based on a memristor, and the output end of each delay unit based on a memristor is correspondingly connected to the first input end of a time determiner;

[0050] The start signal is respectively input to the first input ends of the N time decision devices through the N series-connected memristor-based delay units of the first delay chain, and the end signal is directly input to the second input ends of the N time decision devices.

[0051] Traditional delay units may have different delays due to process deviations, internal voltage IR-Drop, etc., resulting in reduced measurement accuracy.

[0052] When the time-to-digital converter is working, the rising edge of the START signal is transmitted along the delay unit link in the time-to-digital converter link. The longer the propagation time is, the more delay units will output 1. When the rising edge of the STOP signal comes, the time decision device takes away the output signal of the entire delay link at one time. At this time, the output value of N time decision devices is similar to 111111000000 (a total of n bits, n is the number of delay units). By calculating the number of 1 and 0, the time interval between the START signal and the STOP signal can be obtained. Assume that the delay of each delay unit is T cell When a single START and STOP signal arrives, the register output is 111...000... (including n1 1s), so the measured time interval is

[0053] T=n1×T cell

[0054] However, when using ordinary delay units, the delay of each delay unit will be different due to process deviations and IR-Drop voltage drops, which will eventually lead to inaccurate time intervals obtained by counting and reduced system linearity. By replacing ordinary delay units with high-precision adjustable delay units, the delay of each single delay unit can be adjusted with high precision within a small range, making each delay unit of the time-to-digital converter highly consistent to fix the nonlinearity problem of the time-to-digital converter.

[0055] Example 2

[0056] like Figure 2 As shown, a high-precision time-to-digital converter based on a memristor comprises a first delay chain, a second delay chain and N time determiners; wherein the first delay chain comprises N series-connected delay units based on a memristor, and the second delay chain comprises N series-connected delay units based on a memristor; each delay unit based on a memristor of the first delay chain is connected to a first input end of a time determiner; and the output end of each delay unit based on a memristor of the second delay chain is correspondingly connected to a second input end of a time determiner;

[0057] The start signal is input to the first input ends of the N time decision devices through the N series-connected memristor-based delay units of the first delay chain, and the end signal is input to the second input ends of the N time decision devices through the N series-connected memristor-based delay units of the second delay chain.

[0058] The unit delay of the first delay chain is T s , the unit delay of the second delay chain is T f , where T f <T s The specific delay is achieved by adjusting the resistance of the memristor or by adjusting the gate voltage of the parallel NMOS of the adjustable delay unit. At the beginning of a single time difference measurement, the rising edge of the STOP signal arrives with a delay of a period of time after the rising edge of the START signal. Since the delay of the second delay chain is smaller than that of the first delay chain, the STOP signal will catch up with the START signal after passing through n units and will be ahead of the START signal in the second half of the chain. Therefore, after sampling by the time judge, the time digital converter outputs a value similar to 111111000000, and the measured time difference is

[0059] T=n×(T s -T f )

[0060] In a traditional time-to-digital converter, the use of ordinary delay units will cause differences in the delay of each unit in the time-to-digital converter due to process mismatch, voltage drop and other problems, which ultimately leads to nonlinear problems in the time-to-digital converter system. The present invention improves the delay unit into a delay adjustable unit based on a memristor, realizes high-precision adjustment of each delay unit, makes the delay of each unit highly consistent, and solves the nonlinear problem of the traditional time-to-digital converter.

[0061] Example 3

[0062] like Figure 3 , Figure 4 As shown, a high-precision time-to-digital converter based on a memristor comprises: a first delay chain, a second delay chain and 2N time decision devices;

[0063] The first delay chain includes N series-connected memristor-based delay units, and the second delay chain includes N series-connected memristor-based delay units;

[0064] The output ends of the N memristor-based delay units of the first delay chain and the N memristor-based delay units of the second delay chain are respectively connected to the first input end of a time decision device;

[0065] The start signal is input to the first input ends of the N time decision devices through the N series-connected memristor-based delay units of the first delay chain, and the end signal is input to the first input ends of the remaining N time decision devices through the N series-connected memristor-based delay units of the second delay chain, and the clock signal is directly input to the second input ends of the 2N time decision devices.

[0066] Furthermore, the delay of the first delay unit of the first delay chain is different from that of the first delay unit of the second delay chain.

[0067] It should be noted that this embodiment adopts a multi-chain differential mode, which is actually composed of multiple single-chain time-to-digital converters, whose CLK terminal is a fixed clock input, and the START signal and the STOP signal are input signals. The difference between each chain is that the delay of the first delay unit is different. In a specific embodiment, in the case of two chain differentials, the first delay unit is T s and T f , where T s =2T f Except for the first unit, the delay of other units in the two chains is T s When the time-to-digital converter is working, the START signal is delayed for the first time T s The STOP signal is measured in the first delay time T f The delay of the first unit is misaligned, and the delay of the subsequent units is T s , the outputs of the two chains are both 11111…00000. By comparing the outputs of the two chains, we can get the different parts, which are n bits in total. The measured time interval is

[0068]

[0069] This embodiment adopts the form of multi-chain difference to achieve double accuracy by taking two chains as an example. The same principle can be used in the actual time-to-digital converter to form a structure of n chains, and the first delay unit is divided into The measurement accuracy is n times higher than the original one.

[0070] Example 4

[0071] Based on the high-precision time-to-digital converter based on a memristor described in any one of Embodiments 1 to 3, that is, this embodiment adopts the same high-precision time-to-digital converter based on a memristor as any one of Embodiments 1 to 3.

[0072] Furthermore, if Figure 5As shown, the memristor-based delay unit includes: a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, and a first memristor Memristor1;

[0073] The gate of the first MOS tube M1 is connected to the gate of the second MOS tube M2, the source of the first MOS tube M1 is connected to one end of the first memristor Memristor1 and the source of the third MOS tube M3, the drain of the first MOS tube M1 is connected to the drain of the second MOS tube M2, the gate of the third MOS tube M3 and the gate of the fourth MOS tube M4, the drain of the third MOS tube M3 is connected to the drain of the fourth MOS tube M4, the source of the second MOS tube M2 is connected to the drain of the fifth MOS tube M5, the source of the fourth MOS tube M4 is connected to the drain of the sixth MOS tube M6, the gate of the fifth MOS tube M5 is connected to the gate of the sixth MOS tube M6, the other end of the first memristor Memristor1 and the drain of the seventh MOS tube M7, and the source of the fifth MOS tube M5 is connected to the source of the sixth MOS tube M6 and the source of the seventh MOS tube M7;

[0074] The start signal or the end signal is input to the gate of the first MOS tube M1 and the gate of the second MOS tube M2, and is output from the drain of the third MOS tube M3 and the drain of the fourth MOS tube M4.

[0075] It should be noted that the first MOS tube M1 and the third MOS tube M3 are PMOS tubes; the second MOS tube M2, the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, and the seventh MOS tube M7 are NMOS tubes.

[0076] When the memristor-based delay unit described in this embodiment is applied to a time-to-digital converter, the vctrl terminals of all the memristor-based delay units on the same delay chain are connected.

[0077] The first MOS tube M1, the second MOS tube M2, the third MOS tube M3, and the fourth MOS tube M4 form an inverter, the fifth MOS tube M5 and the sixth MOS tube M6 are conduction MOS, one end of the first memristor Memristor1 is connected to the power supply VDD, and the other end of the first memristor Memristor1 is connected to the drain of the seventh MOS tube M7, and Memristor1 and M7 form a voltage-dividing structure. The resistance value of Memristor1 can be continuously adjusted between a high-resistance state and a low-resistance state, and the voltage output by the voltage-dividing structure formed by Memristor1 and M7 is adjustable, that is, the gate voltage of M5 can be adjusted by adjusting the resistance of the memristor, so that the on-resistance of M5 changes within a certain range. When the on-resistance of M5 is R M5onWhen , the falling delay of this level of inverter can be expressed as:

[0078] t PHL =0.69(R M5on +R M2on )C L

[0079] It should be noted that a memristor can also be changed into a form of multiple memristors connected in parallel.

[0080] Example 5

[0081] Based on the high-precision time-to-digital converter based on a memristor described in any one of Embodiments 1 to 3, that is, this embodiment adopts the same high-precision time-to-digital converter based on a memristor as any one of Embodiments 1 to 3.

[0082] Furthermore, if Figure 6 As shown, the memristor-based delay unit includes: an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13, a second memristor Memristor2, and a third memristor Memristor3;

[0083] The source of the eighth MOS tube M8 is connected to the source of the tenth MOS tube M10, the gate of the eighth MOS tube M8 is connected to the gate of the ninth MOS tube M9, the drain of the eighth MOS tube M8 is connected to the drain of the ninth MOS tube M9, the gate of the tenth MOS tube M10, and the gate of the eleventh MOS tube M11, the drain of the tenth MOS tube M10 is connected to the drain of the eleventh MOS tube M11, the source of the ninth MOS tube M9 is connected to the drain of the twelfth MOS tube M12 and one end of the third memristor Memristor3, the source of the eleventh MOS tube M11 is connected to one end of the second memristor Memristor2 and the drain of the thirteenth MOS tube M13, the gate of the twelfth MOS tube M12 is connected to the gate of the thirteenth MOS tube M13, the source of the twelfth MOS tube M12 is connected to the source of the thirteenth MOS tube M13, the other end of the third memristor Memristor3, and the other end of the second memristor Memristor2;

[0084] The start signal or the end signal is input to the gate of the eighth MOS tube M8 and the gate of the ninth MOS tube M9 , and is output from the drain of the tenth MOS tube M10 and the drain of the eleventh MOS tube M11 .

[0085] It should be noted that the eighth MOS tube M8 and the tenth MOS tube M10 are PMOS tubes; the ninth MOS tube M9, the eleventh MOS tube M11, the twelfth MOS tube M12, and the thirteenth MOS tube M13 are NMOS tubes.

[0086] When the memristor-based delay unit described in this embodiment is applied to a time-to-digital converter, the vctrl terminals of all the memristor-based delay units on the same delay chain are connected.

[0087] The eighth MOS tube M8, the ninth MOS tube M9, the tenth MOS tube M10, and the eleventh MOS tube M11 form a common inverter, and the twelfth MOS tube M12 and the thirteenth MOS tube M13 are on-state MOS. When the time-to-digital converter is working, VCTRL is kept above the threshold of the twelfth MOS tube M12 and the thirteenth MOS tube M13 to ensure that the inverter transmits signals normally. Memristor3 and Memristor2 are two memristors, whose resistance values ​​are adjustable in a wide range, but due to being connected in parallel with the twelfth MOS tube M12 and the thirteenth MOS tube M13, the resistance of the structure of the MOS and memristor in parallel under the inverter is only adjusted near the on-resistance of the inverter, where, assuming that the resistance under the inverter is R, R can be obtained by the formula:

[0088] R=R M12on ||R Memristor

[0089] At this time, the falling edge on resistance R on becomes the on-resistance R of M9 n9on The resistor in series with R:

[0090] R on =R M9on +R

[0091] For this level of inverter, its falling delay can be expressed as:

[0092] t PHL =0.69R on C L

[0093] By adjusting the resistance of the memristor, the falling delay of the single-stage inverter is fine-tuned, thereby achieving fine-tuning of the delay of the delay unit. When applied to a time-to-digital converter, when the delay of a delay unit of the time-to-digital converter is large, the resistance of the memristor is adjusted to a smaller value to reduce the delay of the delay unit; when the delay of a delay unit of the time-to-digital converter is small, the resistance of the memristor is adjusted to a larger value to increase the delay of the delay unit, thereby solving the linearity problem of the time-to-digital converter.

[0094] It should be noted that a memristor can also be changed into a form of multiple memristors connected in parallel.

[0095] Example 6

[0096] Based on the high-precision time-to-digital converter based on a memristor described in any one of Embodiments 1 to 3, that is, this embodiment adopts the same high-precision time-to-digital converter based on a memristor as any one of Embodiments 1 to 3.

[0097] Furthermore, if Figure 7 As shown, the memristor-based delay unit includes: a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16, a seventeenth MOS tube M17, and a fourth memristor Memristor4;

[0098] The gate of the fourteenth MOS tube M14 is connected to the gate of the fifteenth MOS tube M15, the source of the fourteenth MOS tube M14 is connected to the source of the sixteenth MOS tube M16, the drain of the fourteenth MOS tube M14 is connected to the drain of the fifteenth MOS tube M15, the gate of the sixteenth MOS tube M16, the gate of the seventeenth MOS tube M17, and one end of the fourth memristor Memristor4, the drain of the sixteenth MOS tube M16 is connected to the drain of the seventeenth MOS tube M17, and the source of the fifteenth MOS tube M15 is connected to the other end of the fourth memristor Memristor4 and the source of the seventeenth MOS tube M17;

[0099] The start signal or the end signal is input to the gate of the fourteenth MOS tube M14 and the gate of the fifteenth MOS tube M15 , and is output from the drain of the sixteenth MOS tube M16 and the drain of the seventeenth MOS tube M17 .

[0100] It should be noted that the fourteenth MOS tube M14 and the sixteenth MOS tube M16 are PMOS tubes; the fifteenth MOS tube M15 and the seventeenth MOS tube M17 are NMOS tubes.

[0101] It should be noted that a memristor can also be changed into a form of multiple memristors connected in parallel.

[0102] Example 7

[0103] Based on the high-precision time-to-digital converter based on a memristor described in any one of Embodiments 1 to 3, that is, this embodiment adopts the same high-precision time-to-digital converter based on a memristor as any one of Embodiments 1 to 3.

[0104] Furthermore, if Figure 8As shown, the memristor-based delay unit includes: an eighteenth MOS tube M18, a nineteenth MOS tube M19, a twentieth MOS tube M20, a twenty-first MOS tube M21, a fifth memristor Memristor5, and a sixth memristor Memristor6;

[0105] The source of the eighteenth MOS tube M18 is connected to the source of the twentieth MOS tube M20, the gate of the eighteenth MOS tube M18 is connected to the gate of the nineteenth MOS tube M19, the drain of the eighteenth MOS tube M18 is connected to the drain of the nineteenth MOS tube M19, the gate of the twentieth MOS tube M20, and the gate of the twenty-first MOS tube M21, the drain of the twentieth MOS tube M20 is connected to the drain of the twenty-first MOS tube M21, the source of the nineteenth MOS tube M19 is connected to one end of the fifth memristor Memristor5, the source of the twenty-first MOS tube M21 is connected to one end of the sixth memristor Memristor6, and the other end of the fifth memristor Memristor5 is connected to the other end of the sixth memristor Memristor6;

[0106] The start signal or the end signal is input to the gate of the eighteenth MOS tube M18 and the gate of the nineteenth MOS tube M19, and is output from the drain of the twentieth MOS tube M20 and the drain of the twenty-first MOS tube M21.

[0107] It should be noted that the eighteenth MOS tube M18 and the twentieth MOS tube M20 are PMOS tubes, and the nineteenth MOS tube M19 and the twenty-first MOS tube M21 are NMOS tubes.

[0108] It should be noted that a memristor can also be changed into a form of multiple memristors connected in parallel.

[0109] Example 8

[0110] Based on the high-precision time-to-digital converter based on a memristor described in any one of Embodiments 1 to 3, that is, this embodiment adopts the same high-precision time-to-digital converter based on a memristor as any one of Embodiments 1 to 3.

[0111] Furthermore, the time determiner is a D flip-flop or a phase detector.

[0112] Furthermore, if Fig. 9 As shown, the phase detector includes: a twenty-second MOS tube M22, a twenty-third MOS tube M23, a twenty-fourth MOS tube M24, a twenty-fifth MOS tube M25, a twenty-sixth MOS tube M26, a twenty-seventh MOS tube M27, a twenty-eighth MOS tube M28, and a twenty-ninth MOS tube M29;

[0113] The gate of the twenty-second MOS tube M22 is connected to the gate of the twenty-fifth MOS tube M25, the source of the twenty-second MOS tube M22 is connected to the source of the twenty-third MOS tube M23, the source of the twenty-sixth MOS tube M26, and the source of the twenty-seventh MOS tube M27, the drain of the twenty-second MOS tube M22 is connected to the drain of the twenty-third MOS tube M23, the gate of the twenty-sixth MOS tube M26, the gate of the twenty-eighth MOS tube M28, and the drain of the twenty-fourth MOS tube M24, the gate of the twenty-third MOS tube M23 is connected to the gate of the twenty-sixth MOS tube M26, the gate of the twenty-eighth MOS tube M28, and the drain of the twenty-fourth MOS tube M24. The gate of the fourteenth MOS tube M24, the drain of the twenty-sixth MOS tube M26, the drain of the twenty-seventh MOS tube M27, and the drain of the twenty-eighth MOS tube M28 are connected, the gate of the twenty-seventh MOS tube M27 is connected to the gate of the twenty-ninth MOS tube M29, the source of the twenty-fourth MOS tube M24 is connected to the drain of the twenty-fifth MOS tube M25, the source of the twenty-eighth MOS tube M28 is connected to the drain of the twenty-ninth MOS tube M29, and the source of the twenty-ninth MOS tube M29 is connected to the source of the twenty-fifth MOS tube M25;

[0114] The signal of the first input terminal is input to the gate of the twenty-second MOS tube M22 and the gate of the twenty-fifth MOS tube M25 , and the signal of the second input terminal is input to the gate of the twenty-seventh MOS tube M27 and the gate of the twenty-ninth MOS tube M29 .

[0115] It should be noted that the twenty-second MOS tube M22, the twenty-third MOS tube M23, the twenty-sixth MOS tube M26, and the twenty-seventh MOS tube M27 are PMOS tubes, and the twenty-fourth MOS tube M24, the twenty-fifth MOS tube M25, the twenty-eighth MOS tube M28, and the twenty-ninth MOS tube M29 are NMOS tubes.

[0116] In a specific embodiment, the converted signal is output from the first output end, that is, the gate of the twenty-third MOS tube M23, the gate of the twenty-fourth MOS tube M24, the drain of the twenty-sixth MOS tube M26, the drain of the twenty-seventh MOS tube M27, and the drain of the twenty-eighth MOS tube M28; the converted signal can also be output from the second output end, that is, the drain of the twenty-second MOS tube M22, the drain of the twenty-third MOS tube M23, the gate of the twenty-sixth MOS tube M26, the gate of the twenty-eighth MOS tube M28, and the drain of the twenty-fourth MOS tube M24.

[0117] It should be noted that in the phase detector, the input signals of the two input terminals are respectively input into the first input terminal and the second input terminal in sequence, and the outputs are correspondingly output from the first output terminal and the second output terminal in sequence. Since the phase detector has a symmetrical structure, if the input signals of the two input terminals are close in time domain, the sequence of the input signals can be correctly distinguished.

[0118] like Fig.10 As shown, the DNL index represents the magnitude of the output deviation from the standard, and the smaller the value, the better the linearity. The linearity of the time-to-digital converter of the present invention is higher.

[0119] The same or similar reference numerals correspond to the same or similar components;

[0120] The terms used in the drawings to describe positional relationships are only used for illustrative purposes and should not be construed as limiting this patent;

[0121] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A high-precision time-to-digital converter based on a memristor, characterized in that: It includes a first delay chain and N time judges; wherein the first delay chain includes N series-connected memristor-based delay units, and the output end of each memristor-based delay unit is correspondingly connected to the first input end of a time judge; The start signal is respectively input to the first input ends of the N time decision devices through the N series-connected memristor-based delay units of the first delay chain, and the end signal is directly input to the second input ends of the N time decision devices.

2. A high-precision time-to-digital converter based on a memristor, characterized in that: It includes a first delay chain, a second delay chain and N time judges; wherein the first delay chain includes N series-connected delay units based on memristors, and the second delay chain includes N series-connected delay units based on memristors; each delay unit based on memristors of the first delay chain is connected to a first input end of a time judge; and the output end of each delay unit based on memristors of the second delay chain is correspondingly connected to a second input end of a time judge; The start signal is input to the first input ends of the N time decision devices through the N series-connected memristor-based delay units of the first delay chain, and the end signal is input to the second input ends of the N time decision devices through the N series-connected memristor-based delay units of the second delay chain.

3. A high-precision time-to-digital converter based on a memristor, characterized in that: include: A first delay chain, a second delay chain and 2N time judges; The first delay chain includes N series-connected memristor-based delay units, and the second delay chain includes N series-connected memristor-based delay units; The output ends of the N memristor-based delay units of the first delay chain and the N memristor-based delay units of the second delay chain are respectively connected to the first input end of a time decision device; The start signal is input to the first input ends of the N time decision devices through the N series-connected memristor-based delay units of the first delay chain, and the end signal is input to the first input ends of the remaining N time decision devices through the N series-connected memristor-based delay units of the second delay chain, and the clock signal is directly input to the second input ends of the 2N time decision devices.

4. A memristor-based high-precision time-to-digital converter according to any one of claims 1 to 3, characterized in that: The memristor-based delay unit includes: a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, and a first memristor Memristor1; The gate of the first MOS tube M1 is connected to the gate of the second MOS tube M2, the source of the first MOS tube M1 is connected to one end of the first memristor Memristor1 and the source of the third MOS tube M3, the drain of the first MOS tube M1 is connected to the drain of the second MOS tube M2, the gate of the third MOS tube M3 and the gate of the fourth MOS tube M4, the drain of the third MOS tube M3 is connected to the drain of the fourth MOS tube M4, the source of the second MOS tube M2 is connected to the drain of the fifth MOS tube M5, the source of the fourth MOS tube M4 is connected to the drain of the sixth MOS tube M6, the gate of the fifth MOS tube M5 is connected to the gate of the sixth MOS tube M6, the other end of the first memristor Memristor1 and the drain of the seventh MOS tube M7, and the source of the fifth MOS tube M5 is connected to the source of the sixth MOS tube M6 and the source of the seventh MOS tube M7; The start signal or the end signal is input to the gate of the first MOS tube M1 and the gate of the second MOS tube M2, and is output from the drain of the third MOS tube M3 and the drain of the fourth MOS tube M4.

5. A memristor-based high-precision time-to-digital converter according to any one of claims 1 to 3, characterized in that: The memristor-based delay unit includes: an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13, a second memristor Memristor2, and a third memristor Memristor3; The source of the eighth MOS tube M8 is connected to the source of the tenth MOS tube M10, the gate of the eighth MOS tube M8 is connected to the gate of the ninth MOS tube M9, the drain of the eighth MOS tube M8 is connected to the drain of the ninth MOS tube M9, the gate of the tenth MOS tube M10, and the gate of the eleventh MOS tube M11, the drain of the tenth MOS tube M10 is connected to the drain of the eleventh MOS tube M11, the source of the ninth MOS tube M9 is connected to the drain of the twelfth MOS tube M12 and one end of the third memristor Memristor3, the source of the eleventh MOS tube M11 is connected to one end of the second memristor Memristor2 and the drain of the thirteenth MOS tube M13, the gate of the twelfth MOS tube M12 is connected to the gate of the thirteenth MOS tube M13, the source of the twelfth MOS tube M12 is connected to the source of the thirteenth MOS tube M13, the other end of the third memristor Memristor3, and the other end of the second memristor Memristor2; The start signal or the end signal is input to the gate of the eighth MOS tube M8 and the gate of the ninth MOS tube M9 , and is output from the drain of the tenth MOS tube M10 and the drain of the eleventh MOS tube M11 .

6. A memristor-based high-precision time-to-digital converter according to any one of claims 1 to 3, characterized in that: The memristor-based delay unit includes: a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16, a seventeenth MOS tube M17, and a fourth memristor Memristor4; The gate of the fourteenth MOS tube M14 is connected to the gate of the fifteenth MOS tube M15, the source of the fourteenth MOS tube M14 is connected to the source of the sixteenth MOS tube M16, the drain of the fourteenth MOS tube M14 is connected to the drain of the fifteenth MOS tube M15, the gate of the sixteenth MOS tube M16, the gate of the seventeenth MOS tube M17, and one end of the fourth memristor Memristor4, the drain of the sixteenth MOS tube M16 is connected to the drain of the seventeenth MOS tube M17, and the source of the fifteenth MOS tube M15 is connected to the other end of the fourth memristor Memristor4 and the source of the seventeenth MOS tube M17; The start signal or the end signal is input to the gate of the fourteenth MOS tube M14 and the gate of the fifteenth MOS tube M15 , and is output from the drain of the sixteenth MOS tube M16 and the drain of the seventeenth MOS tube M17 .

7. A high-precision time-to-digital converter based on a memristor according to any one of claims 1 to 3, characterized in that: The memristor-based delay unit includes: an eighteenth MOS tube M18, a nineteenth MOS tube M19, a twentieth MOS tube M20, a twenty-first MOS tube M21, a fifth memristor Memristor5, and a sixth memristor Memristor6; The source of the eighteenth MOS tube M18 is connected to the source of the twentieth MOS tube M20, the gate of the eighteenth MOS tube M18 is connected to the gate of the nineteenth MOS tube M19, the drain of the eighteenth MOS tube M18 is connected to the drain of the nineteenth MOS tube M19, the gate of the twentieth MOS tube M20, and the gate of the twenty-first MOS tube M21, the drain of the twentieth MOS tube M20 is connected to the drain of the twenty-first MOS tube M21, the source of the nineteenth MOS tube M19 is connected to one end of the fifth memristor Memristor5, the source of the twenty-first MOS tube M21 is connected to one end of the sixth memristor Memristor6, and the other end of the fifth memristor Memristor5 is connected to the other end of the sixth memristor Memristor6; The start signal or the end signal is input to the gate of the eighteenth MOS tube M18 and the gate of the nineteenth MOS tube M19, and is output from the drain of the twentieth MOS tube M20 and the drain of the twenty-first MOS tube M21.

8. A high-precision time-to-digital converter based on a memristor according to any one of claims 1 to 3, characterized in that: The time decision device is a D flip-flop or a phase detector.

9. The high-precision time-to-digital converter based on a memristor according to claim 8, characterized in that: The phase detector includes: a twenty-second MOS tube M22, a twenty-third MOS tube M23, a twenty-fourth MOS tube M24, a twenty-fifth MOS tube M25, a twenty-sixth MOS tube M26, a twenty-seventh MOS tube M27, a twenty-eighth MOS tube M28, and a twenty-ninth MOS tube M29; The gate of the twenty-second MOS tube M22 is connected to the gate of the twenty-fifth MOS tube M25, the source of the twenty-second MOS tube M22 is connected to the source of the twenty-third MOS tube M23, the source of the twenty-sixth MOS tube M26, and the source of the twenty-seventh MOS tube M27, the drain of the twenty-second MOS tube M22 is connected to the drain of the twenty-third MOS tube M23, the gate of the twenty-sixth MOS tube M26, the gate of the twenty-eighth MOS tube M28, and the drain of the twenty-fourth MOS tube M24, the gate of the twenty-third MOS tube M23 is connected to the gate of the twenty-sixth MOS tube M26, the gate of the twenty-eighth MOS tube M28, and the drain of the twenty-fourth MOS tube M24. The gate of the fourteenth MOS tube M24, the drain of the twenty-sixth MOS tube M26, the drain of the twenty-seventh MOS tube M27, and the drain of the twenty-eighth MOS tube M28 are connected, the gate of the twenty-seventh MOS tube M27 is connected to the gate of the twenty-ninth MOS tube M29, the source of the twenty-fourth MOS tube M24 is connected to the drain of the twenty-fifth MOS tube M25, the source of the twenty-eighth MOS tube M28 is connected to the drain of the twenty-ninth MOS tube M29, and the source of the twenty-ninth MOS tube M29 is connected to the source of the twenty-fifth MOS tube M25; The signal of the first input terminal is input to the gate of the twenty-second MOS tube M22 and the gate of the twenty-fifth MOS tube M25 , and the signal of the second input terminal is input to the gate of the twenty-seventh MOS tube M27 and the gate of the twenty-ninth MOS tube M29 .

10. The high-precision time-to-digital converter based on a memristor according to claim 3, characterized in that: The delay of the first delay unit of the first delay chain is different from that of the first delay unit of the second delay chain.

Images